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2015-03-17t132: Add TTB_BUFFER to resource reservedFurquan Shaikh
TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while performing a wipe in depthcharge. Hence, marking it as reserved BUG=None BRANCH=None TEST=Compiles successfully and boots upto depthcharge. Error wiping memory tables is fixed. Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210000 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e Reviewed-on: http://review.coreboot.org/8681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rush: Update rush Kconfig fileFurquan Shaikh
Update rush Kconfig file to include TPM and RAMSTAGE_INDEX options BUG=None BRANCH=None TEST=Compiles successfully. TPM works. Ramstage boots successfully. Original-Change-Id: Ie55260c710ffcb6a2e04c8658ca6dd3cdec6b6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209978 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0088f5aade8533c6ed235de25934d47cd0743a67) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5c4a54b74546de73eee7e7bae072cc712ce1838f Reviewed-on: http://review.coreboot.org/8680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rush: Add ec_dummy file to enable vboot compilationFurquan Shaikh
BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ic11bef85e5c7635000582f87727cd9a33b0b36e3 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 3d3f0494d8758ef5040384f63d023c042686bd2c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie15781d10a366b68f0db97378ccb348a4f074995 Reviewed-on: http://review.coreboot.org/8679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rush: Pull in chromeos.c from nyan into rushFurquan Shaikh
Hardcoded values are set for developer,recovery mode. Change as per requirements BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles succesfully for rush Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3 Reviewed-on: http://review.coreboot.org/8678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17Tegra132: Configure CPU clockJimmy Zhang
Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible from AVP, the first place that can change CPU clock is after CPU has been brought up, ie, ramstage in this case. CPU initial clock source is set to PLLP by MTS. BUG=None TEST=Norrin64 and A44 Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209698 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89 Reviewed-on: http://review.coreboot.org/8677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17t132: Add monotonic_timer.c to rmodules_armFurquan Shaikh
Update VBOOT_STUB_DEPS to include monotonic_timer.c BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I3cc559fa21c444da1a7976e4952ea4941c2a1428 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209972 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8096ae56c4df4013cfc798944b98dd1078c8b451) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c13617b96fd872d1eaa9278de6647eccb795c3 Reviewed-on: http://review.coreboot.org/8674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rmodules: Make rmodules inclusion for vboot dependent on romstage_archFurquan Shaikh
Currently, the rmodules inclusion for vboot is dependent on ramstage_arch. This change adds dependency on romstage_arch, since vboot is associated with romstage. Inclusion based on ramstage_arch is left as is in case someone needs it in ramstage. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for link, rush and nyan Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209568 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc Reviewed-on: http://review.coreboot.org/8673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17coreboot classes: Add dynamic classes to corebootFurquan Shaikh
Provide functionality to create dynamic classes based on program name and the architecture for which the program needs to be compiled/linked. define_class takes program_name and arch as its arguments and adds the program_name to classes-y to create dynamic class and compiler toolset is created for the specified arch. All the files for this program can then be added to program_name-y += .. Ensure that define_class is called before any files are added to the class. Check subdirs-y for order of directory inclusion. One such example of dynamic class is rmodules. Multiple rmodules can be used which need to be compiled for different architectures. With dynamic classes, this is possible. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for nyan, rush and link. Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209379 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295) Some of this cherry-pick had already been committed here: commit 133096b6dc31163f59f658e15f2eb342a0de2ac6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c Reviewed-on: http://review.coreboot.org/8672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17soc/ipq806x: Replace GPT with fine grained DGT timer.Deepa Dinamani
Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 Reviewed-on: http://review.coreboot.org/8596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17coreboot: x86: enable gc-sectionsAaron Durbin
Garbage collected sections allow for trimming the size of the binaries as well as allowing for not needing to config off unused functions. To that end, on a rambi build the following differences are observed: $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf) --- /dev/fd/63 2015-03-10 12:07:27.927985430 -0500 +++ /dev/fd/62 2015-03-10 12:07:27.927985430 -0500 @@ -6,9 +6,9 @@ There are 4 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0 - LOAD 0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0 - LOAD 0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0 - LOAD 0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560 0 + LOAD 0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0 + LOAD 0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0 + LOAD 0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888 0 Section to Segment mapping: Segment Sections... $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf) --- /dev/fd/63 2015-03-10 12:08:16.855985880 -0500 +++ /dev/fd/62 2015-03-10 12:08:16.851985880 -0500 @@ -5,8 +5,8 @@ There are 1 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align - LOAD 0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E 0x10 + LOAD 0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E 0x10 Section to Segment mapping: Segment Sections... - 00 .rom .text + 00 .rom The following warnings needed to be applied to CFLAGS_common because for some reason gcc was miraculously emitting the warnings with the unrelated *-sections options: -Wno-unused-but-set-variable Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-17rockchip/rk3288: Fix whitespaceKyösti Mälkki
Change-Id: I6c3c1e871de33b4d0e968b254bbcf125cee9fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8704 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-17haswell: Fix monotonic timer integrationStefan Reinauer
In some previous attempt to enable monotonic timers on all platforms, the LAPIC monotonic timer was selected for Haswell devices, despite the fact that LAPIC timers are not used in coreboot on Haswell (See haswell Kconfig) and there already was a monotonic timer implementation enabled that just needed to be added for SMM as well. Change-Id: I6beb2977864e507956636860ed463e1991cea1ed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8702 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17Intel common SPI: Fix compilation breakage from refactoringStefan Reinauer
When the Intel SPI drivers were refactored, compilation for Chrome OS devices broke, because ELOG uses the SPI driver in SMM. Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8701 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17elog: Fix compilation with CONFIG_CHROMEOS enabledStefan Reinauer
On ChromeOS devices the ELOG section size and offset are provided by the FMAP, rather than KConfig. Some upstream refactoring broke compilation in that case. Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17cpu/amd/model_10xxx: Move GFXUMA size calculation to separate functionTimothy Pearson
This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8663 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-17lib: Add Kconfig option to enable/disable auto fallback controlTimothy Pearson
Under certain conditions, e.g. automated testing, it is useful to have the payload (e.g. Linux) reset the reboot_bits CMOS value. This allows automated recovery in the case of coreboot starting properly but the payload failing to start due to bad configuration data provided by the coreboot image under test. Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd Reviewed-on: http://review.coreboot.org/8698 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-03-17Makefile.inc: Use -Og when compiling with GDB supportStefan Reinauer
From GCC's documentation: Optimize debugging experience. -Og enables optimizations that do not interfere with debugging. It should be the optimization level of choice for the standard edit-compile-debug cycle, offering a reasonable level of optimization while maintaining fast compilation and a good debugging experience. Change-Id: I9a3dadbf8e894cb28e29d7b2f4e9add252e7bbb3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17crossgcc: Add x86_64 to list of supported architecturesStefan Reinauer
You can build your new toolchain with: $ cd util/crossgcc/ $ ./buildgcc -d /opt/cross -p x86_64-elf -j 16 or $ make crossgcc-x64 Change-Id: I8eb584166294578d2b33c63e94ed3aca9b5de4f4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8668 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-16northbridge/amd/pi: Create common agesawrapper.cDave Frodin
This removes the mainboard agesawrapper.c file from binarypi based boards and creates a common one. Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()Dave Frodin
This makes the change to the cpu/amd/pi/00730F01 that was made for the cpu/amd/agesa based boards in: commit 48518f0d AGESA: Add amd_initcpuio() and amd_initmmio() These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). The equivalent change has already been made for cpu/amd/pi/00630F01. Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8670 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16mainboards/amd: Fix incorrect reboot_bits locationTimothy Pearson
Change-Id: Iead07df714f4f1bbaae6b564431fb4edf7b18ac2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-16northbridge/i945/gma: fix build error with native graphics initFrancis Rowe
Tested on an X60, Native graphics init still works perfectly. Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/8696 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-03-16coreboot: rk3288: Add a stub implementation of the rk3288 SOCjinkun.hong
Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-16genbuild_h.sh: use the last git commit as timesource if availableAlexander Couzens
Change-Id: I1472265adac9406a86da22839199ec6bbdaa0c69 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8619 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-15google/butterfly: Drop MRC.bin in favor of native raminitAlexandru Gagniuc
I thought this wasn't going to work, and observing the timC detection failure of early tests, I was getting somewhat discouraged; however, this works. I've tried it with all possible permutations of the following memory modules: * 2 GiB single-rank DDR3-1600 * 4 GiB single-rank DDR3-1600 * 4 GiB dual-rank DDR3-1600 I did notice a limited number of memtest errors during one of the runs, but they were in an address range that is otherwise marked as reserved. I wrote that off as "maybe something was doing MMIO there just when memtest was poking the address range". I was not able to reproduce that error. Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-03-15mainboard/asus/kfsn4-dre: Use Fallback boot image by defaultTimothy Pearson
Change-Id: Ib58550acda63132e35a526c72ac7d987b457cea5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15mainboard/asus/kfsn4-dre: Change default debug level to SpewTimothy Pearson
This brings the KFSN4-DRE in line with other boards in the tree. Change-Id: I9216130f51ed0576871fd27ca6ae4610c5f5810e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8683 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15northbridge/amd/amdht/h3finit.c: Fix boot failureTimothy Pearson
GIT hash 586d6e introduced a regression that causes boot failure with an f0011449 AMD stop code. Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8685 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-14OxPCIe952: Fix read8/write8 argumentKyösti Mälkki
This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-13Use a common boardid.h instead of per board copiesVadim Bendebury
There is no point in duplicating boardid.h per board - they are all the same. Let's keep a single instance in the common include directory and let the linker report a problem if one tries using this function on a board where it is not supported. BUG=chrome-os-partner:30489 TEST=verified that coreboot builds fine for nyan_big and nyan_blaze. Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209699 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962 Reviewed-on: http://review.coreboot.org/8666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13libpayload: ipq808x: stale interrupt shall not be cleared unconditionallyYogesh Lal
The serial driver hangs in cases when FIFO has more than single word to be processed. Easiest way to reproduce is to paste a string of greater than 4 characters in cli. Clearing the RXSTALE interrupt without draining all the characters from FIFO leads to the issue as the driver is dependent on msm_boot_uart_dm_read function to reinitialize for next transfer. Logically the driver is organized in such a manner that next transfer never gets initiated till rx_data_read < total_rx_data. Clearing the RXSTALE without consideration of total number of characters (or words) unprocessed makes the msm_boot_uart_dm_read to return on the first if conditional. Thus the driver is stuck forever. A quick fix is to avoid clearing the stale interrupt. Reset is handled whenever a new transfer is initialized in msm_boot_uart_dm_init_rx_transfer. BUG=chrome-os-partner:29542 TEST=manual -Paste a string greater than 4 characters in cli. Original-Change-Id: I016afb01a77cd14764f0176f6bf144fb29796c2f Original-Signed-off-by: Yogesh Lal <ylal@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209512 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 61528884ad2c0a8e146054bbfeb01a3bc73b9692) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I936af5daa52a25f62133bdf9fb44f0b68cf34e88 Reviewed-on: http://review.coreboot.org/8667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13northbridge/amd/amdht: Allow mainboards to set HT frequency limitTimothy Pearson
This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8464 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-13siemens/mc_tcu3: Fix build and ACPI IRQ bridge entryKyösti Mälkki
Propagate commit d08057a change to this new FSP platform. Change-Id: Ie83c7f3573c189f4e4576c971dbc12099bb7b123 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8662 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-03-13nyan: Remove broken setup_display() from romstageJulius Werner
This patch removes a chunk of romstage code from Tegra and all Nyan boards that was supposed to enable some LCD power rails early, but never really worked. The dev_find_slot() function can only find PCI devices, which the CPU cluster is not. Since we're done with Nyan-RO and the ramstage display code is fine as it is, there is no point in trying to fix this... but we should remove it from ToT lest someone uses it as a blueprint to add more dead code to future boards. BRANCH=None BUG=None TEST=None Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207720 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8deedea5e9787848aae3064509c611bc349313cc Reviewed-on: http://review.coreboot.org/8638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-13northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSPAlexander Couzens
This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even though this capability is supported on nehalem it doesn't make sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by: BITS Tested-on: lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8659 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITYAlexander Couzens
BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8658 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13coreboot t132: Remove empty function cpu0_config_and_resetFurquan Shaikh
This function is not used/required in t132. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Iba5ea3c14cc9facbf2a86aa08021edb9907f92da Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209425 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit c615136aa82d457540eb1f1308c9e986dbc9bce7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id92d464db24298dd888cbc022204379eb8aa8aba Reviewed-on: http://review.coreboot.org/8652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13coreboot t132: Stop running AVP at the end of romstageFurquan Shaikh
Stop running AVP at the end of romstage until event conditions are met (JTAG, GIC_IRQ or LIC_IRQ). BUG=chrome-os-partner:30831 BRANCH=None TEST=Compiles successfully and boots till last known good checkpoint. Original-Change-Id: Ia221f08b27ac0c60a66d588e351677144cc6a322 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209424 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit df4e8b4c8a1002443a936bd0563fbc9e0710f489) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I59f7702bd50a1039b8723e9cb12b8d714e353d37 Reviewed-on: http://review.coreboot.org/8651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13coreboot arm64: Add int constants to stdint.hFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I395c9b7bbe34c6834abc1a169779639f940121bd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209334 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit da15df16464f4203db08fb02ad4c0a0f94d16724) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I818de7cb0d8a44fb20c2bbea108c15ecc2b724ae Reviewed-on: http://review.coreboot.org/8650 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13tegra132: fix Rx FIFO underruns with slower SPI clockAaron Durbin
The SPI controller operates on packets which can be variable length up to 32-bit packets. It also has the ability to be put in packed or unpacked mode w.r.t each packet. i.e. does a single fifo register hold >= 1 packet. The current programming uses 8-bit packets in unpacked mode which means 4 fifo slots are used for a 32-bit DMA transfter. As the AHB can only operate on a minimum of 32-bit bursts the triggers need to be programmed correctly so that there is room for a full 32-bit DMA transaction. Previously faster SPI clocks just made things magically work. BUG=chrome-os-partner:30779 BRANCH=None TEST=Built and booted through coreboot with 20MHz SPI clock. Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208862 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196 Reviewed-on: http://review.coreboot.org/8649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13tegra132: Add Trust Zone register accessAaron Durbin
The Trust Zone carveout registers are only accessible using a secure access mode. The AVP runs as non-secure all the time. In EL3 the CPU is in secure mode, but when the MMU is enabled the page tables dictate if accesses to certain regions are secure or not. However, ramstage is currently being loaded into non-secure memory and the page tables will live in non-secure memory as well. Therefore, handle all these cases by providing global state which mirrors the TZ register. BUG=chrome-os-partner:30782 BRANCH=None TEST=Built and ran through ramstage with the MMU enabled Resources are read and set accordingly. Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209061 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b Reviewed-on: http://review.coreboot.org/8648 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13t132: Add mmu supportFurquan Shaikh
Add support for mmu initialization and enabling caches. mmu_operations provides functions to add mmap_regions using memrange library and then calls mmu_init for armv8. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until depthcharge load. Goes past all the earlier alignment errors. Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208762 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b Reviewed-on: http://review.coreboot.org/8647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13armv8: Add mmu supportFurquan Shaikh
Add support for initializing and enabling mmu for armv8. Using 64KiB granule and 33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes use of memrange library to get a list of all the mmap regions from the SoC to initialize XLAT table. Currently, all calculations in mmu.h are based on the assumptions that max 33 bits are used in VA and granule size is 64KiB. Changes in these assumptions will have to reflect in the dependent calculations as well. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until "payload not found". Goes past all the earlier alignment errors. Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285 Reviewed-on: http://review.coreboot.org/8646 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-03-13ryu: Add TPS65913 regs/init for VDD_CPU 1.0VTom Warren
Other default slams should be added later to the init table once we know what the kernel touches. But for now, only VDD_CPU is needed. Also slipped in a minor name change in mainboard.c BRANCH=none BUG=none TEST=none, no HW here for me to test on yet Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795 Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/208385 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13tegra132: Add code to setup chip operations and mem resources.Tom Warren
With this memory resource, the payload loading code should be able to create a bounce buffer and load the payload successfully. Adapted from tegra124 soc.c BUG=None BRANCH=None TEST=Built and booted to ramstage on rush. Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208121 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f Reviewed-on: http://review.coreboot.org/8644 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13ryu: Add support for full LPDDR3 SDRAM BCT init via BootROMTom Warren
Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe Reviewed-on: http://review.coreboot.org/8643 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13armv8: correct dcache line size calculationAaron Durbin
The CCSIDR_EL1 register has cache attribute information for a given cache selection in CSSELR_EL1. However, the cache isn't being selected before reading CCSIDR_EL1. Instead use CTR_EL0 which better fits with the semantics of dcache_line_bytes(). CTR_EL0 has the minimum data cache line size of all caches in the system encoded in 19:16 encoded as lg(line size in words). BUG=None TEST=Built. Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208720 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0 Reviewed-on: http://review.coreboot.org/8642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13tegra132: split memory range querying to above/below 4GiBAaron Durbin
The address map code was originally assuming all carveouts would be packed together in the upper end of the physical memory address space. However, the trust zone carveout is always in the 32-bit address space. Therefore, one needs to query memory ranges by above and below 4GiB with the assumption of carveouts being packed at the top of *each* resulting range. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran through coreboot on rush. Original-Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208101 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8d5795fbff36e91906384e10774a32541d358324) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If15ff48d5a4c81731eb364980b30c8086deb1cca Reviewed-on: http://review.coreboot.org/8641 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-12storm: allow to override CBFS_SIZE configuration settingVadim Bendebury
The default CBFS size configuration setting is incorrect in case of Qualcomm SOC targets, as the coreboot blob is much smaller than the actual bootprom. Note that this size also must match the board fmap defined in the appropriate depthcharge board directory. BUG=chromium:394068 TEST=manual . previously failing to boot coreboot image does not fail to load depthcharge anymore. Original-Change-Id: I1b178970b1deee05705490542e4a0c57500379dd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208146 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 01f3561fdee7b5547534e20d423fbbb1b490532c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If573bbc6254cf6786e75970eae3ad2b327a7ecfe Reviewed-on: http://review.coreboot.org/8640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-12t132: handle optional Trust Zone region correctlyAaron Durbin
Provide a default Trust Zone region size of 1MiB, and correctly account for it in the AVP and the arm64 cores. The different path between the arm64 cores and the AVP is because the AVP cannot access the Trust Zone region registers. Therefore the AVP needs to account for the Trust Zone region. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran. Noted Trust Zone region being accounted for. Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208062 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44 Reviewed-on: http://review.coreboot.org/8639 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-12intel/fsp_baytrail: Add PCI Root Port IRQ RoutingMartin Roth
This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-11x86 SMM: Replace weak prototypes with weak function stubKyösti Mälkki
Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-10lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230Nicolas Reinecke
Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio. Verified with schematics. Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8358 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-10console/Kconfig: Enable CBMEM console by defaultPaul Menzel
Currently on AMD boards no romstage messages can be saved in CBMEM, so only messages from ramstage on will be stored in CBMEM. Other than that nothing changes. Enabling CBMEM console by default does not noticeably decrease boot time as the messages are directly written to CAR or RAM. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository, although it is important to have those. Enabling CBMEM console by default improves this situation, so that for all boards at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5350 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8188 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE optionKyösti Mälkki
This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10ARM romstages: Support and fix COLLECT_TIMESTAMPSKyösti Mälkki
Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8021 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-03-10cbmem console: Allow the cbmem console on non-x86 systems again.Gabe Black
If it's not supported on a particular board, either the build will fail or checks within the cbmem console itself should detect the problem. There shouldn't be random memory corruption any more. BUG=None TEST=Built with CONSOLE_CBMEM enabled on nyan and saw that it was actually enabled. BRANCH=None Original-Change-Id: Id6c8c7675daafe07aa4878cfcf13faefe576e520 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 20b486443bfc2d93d72bbc9e496023a00ab9ab30) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I39fbcdff61f6d8f520f2e9d7612dee78e97898b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7748 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-10crossgcc: fix copy-paste mistake on riscv make targetAlexander Couzens
Change-Id: Id618595a321529770964b125f7490dcb08376643 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8637 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-10northbridge/amd/pi: Remove superfluous logic operandDave Frodin
Commit 2e0cf14 corrected this for pi/00730F01/northbridge.c. This commit fixes it for pi/00630F01/northbridge.c. Found-by: Clang Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8289 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-10AMD Bald Eagle: Add northbridge files for new AMD processorBruce Griffith
Also fix a typo in a config option for SteppeEagle. Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7247 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-10x86: simplify early_variables.h headerAaron Durbin
The CAR macros and the associated functions are only employed under the following conditions: - chipsets which have CAR - compilation during romstage Therefore clean up the build-time conditionals to use those 2 constructs. Change-Id: I2b923feeb68f2b964c5ac57e11391313d9c8ffc5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8634 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-10qemu: 2.1+ smbios tables supportGerd Hoffmann
Starting with version 2.1 qemu provides a full set of smbios tables for the virtual hardware emulated, except type 0 (bios information). This patch adds support for loading those tables to coreboot. The code is used by both i440fx and q35. Change-Id: Id034f0c214e8890194145a92f06354201dee7963 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/8608 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-10util/inteltool: Support reading RCBA of NM70 southbridgeAlexandru Gagniuc
Change-Id: Ia90f967a4988214c719f374a49233bb6fade11b0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8481 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09Add and consistently use wrapper macro for romstage static variablesJulius Werner
x86 systems run their romstage as execute-in-place from flash, which prevents them from having writable data segments. In several code pieces that get linked into both romstage and ramstage, this has been worked around by using a local variable and having the 'static' storage class guarded by #ifndef __PRE_RAM__. However, x86 is the only architecture using execute-in-place (for now), so it does not make sense to impose the restriction globally. Rather than fixing the #ifdef at every occurrence, this should really be wrapped in a way that makes it easier to modify in a single place. The chromeos/cros_vpd.c file already had a nice approach for a wrapper macro, but unfortunately restricted it to one file... this patch moves it to stddef.h and employs it consistently throughout coreboot. BRANCH=nyan BUG=None TEST=Measured boot time on Nyan_Big before and after, confirmed that it gained 6ms from caching the FMAP in vboot_loader.c. Original-Change-Id: Ia53b94ab9c6a303b979db7ff20b79e14bc51f9f8 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203033 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit c8127e4ac9811517f6147cf019ba6a948cdaa4a5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I44dacc10214351992b775aca52d6b776a74ee922 Reviewed-on: http://review.coreboot.org/8055 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-09console: Fix broken early_print.h include guardsStefan Reinauer
Make compilation fail if this is included in non-romcc compiles. I am a bit surprised that this ever compiled. Change-Id: I8dfc1229681819d2381821a0195a89b44dd76b6a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8420 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09genbuild_h.sh: set TZ + LANG variable for predictable `date` and `git` outputAlexander Couzens
Change-Id: I10fb0f797b79a2bdbc41c31fe846cc04e26260b3 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8618 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09genbuild_h.sh: derive all timestamp variables from one timestampAlexander Couzens
If not derived it's possible it defines inconsistent timestamps which differ from each other. Change-Id: I090fdce4c4c1c24135ec72818eecb69e168df565 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8617 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD fam10: Drop PCI_BUS_SEGN_BITSKyösti Mälkki
All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09AMD fam10: Fix include of conf.cKyösti Mälkki
Change-Id: I982acb0b36f2cef8281ffbac4511f831f08fc89a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8553 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09build.h: remove variable for the builduser, -hostname and -domainAlexander Couzens
They don't contain any useful information and also block us from having reproducible builds. Change-Id: Ib03887f6a548230de9f75fb308c73a800e180c48 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8616 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-09crossgcc: Unify tool tests, add check for g++ or clangPatrick Georgi
Change-Id: I406f5cfc61bc87ccc2c0b9283b4fbb8cef8dfc1b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/8522 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD fam10: Remove __PRE_RAM__ from ramstage-only codeKyösti Mälkki
Change-Id: I41aba81def13c99671eb609dd1e76a9a45299622 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD fam10: Always have AMDMCTKyösti Mälkki
Also drop some more #if UNUSED_CODE. Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD K8: Fix allocation size for HyperTransport linksKyösti Mälkki
There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: Id8a7db3ffb4111eb31e70ea14fd522b70368dd8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8550 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09AMD K8: Move the test for connected HyperTransport linkKyösti Mälkki
Change-Id: I7f8cbfcae7ec2a49e91ceda1eecdcf76b2137d8b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8549 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09google/samus/acpi/mainboard.asl: Correctly align commentPaul Menzel
Fix up commit 00aedc5e (samus: add acpi resource for supporting RT5677 codec). Change-Id: I98b8c6f1a46f9f3bfd79da92bb070cebe8f20dc0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8234 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09cpu/Kconfig: Make in-tree microcode generation dependent on BLOBs repositoryPaul Menzel
Since commit ee894357 (cpu/intel (non-FSP): Use microcode from blobs repository), selecting the option to generate the microcode from tree fails without allowing to use the BLOBs/ 3rdparty repository, which is the default setting. Therefore, only show the option, if the user has selected the option to allow the use of the BLOBs repository. Change-Id: Ide20da0f946aae43dc2c8cdce54941c704d3d288 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8627 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09broadwell: enable PCIe endpoint CLK power managementKane Chen
BUG=chrome-os-partner:31424 BRANCH=none TEST=build only, due to I don't have broadwell system with wifi to test need somebody help me to verify Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/220743 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8448 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09device/pciexp: Add support for PCIe CLK power managementKane Chen
Set PCIe "Enable Clock Power Management", if endpoint supports it. BUG=chrome-os-partner:31424 BRANCH=none TEST=build and boot on rambi, check Enable Clock Power Management in link control register is set properly Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/220742 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> [Edit commit message.] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8447 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09coreboot: fix munged license textAaron Durbin
At some point the license text for a file was incorrectly changed. That license was then copied and pasted. I'm sure it was myself. Anyhow, fix the bustedness. Change-Id: I276083d40ea03782e11da7b7518eb708a08ff7cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-08device: drop i915 specific headers from resource allocator includesStefan Reinauer
src/include/device/ is the place for include files of the resource allocator. Hence, drop the i915 include file copies and use the ones supplied with the i915 driver instead. The only remaining user of this was the Intel Whitetip Mountain 2 reference board, all other occurences have been previously fixed already. Change-Id: Ib9f72df4e8f847597508971e9dbf671f49019767 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8140 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-08crossgcc: Add RISC-V supportPatrick Georgi
Change-Id: If1e0f7ed21f67d7a185dad251ede81ddbc18c4e5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/8629 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-08crossgcc: Update toolchainPatrick Georgi
Update GCC to 4.9.2, binutils to 2.25. Change-Id: Iae9763163b7f42c55a39e26b4beedee67d14a6e4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/8628 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-08crossgcc: Add mipsel-elf as supported targetPatrick Georgi
Change-Id: Icd8050d9193f9957468cfa13901ec14e993e50de Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/8630 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-07northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and laterTimothy Pearson
The BKDG for K10 revision D and later processors recommends a smaller MCT burst write queue depth when using unganged memory. TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431 processors. Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-07AGESA: Move agesawrappers related to HAVE_ACPI_RESUME supportKyösti Mälkki
This change brings all agesawrappers in a single file to make it easier to understand the actual execution flow. Change-Id: Ifbb2b16e4cccfaa17aaf10887a856797be9b6877 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8605 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07AGESA: Use same HeapManager for all BiosCallOutsKyösti Mälkki
We do not allow platforms to mess around with memory layout. Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2Kyösti Mälkki
Make the build tolerate re-definitions. Change-Id: Ia7505837c70b1f749262508b26576e95c7865576 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8609 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07t132: add Kconfig option for MTS microcode directoryAaron Durbin
In order to make sharing of the location of MTS microcode easier provide a Kconfig option that is the path to the files. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built rush coreboot. Original-Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207839 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6f1de0e7fd312c1d6798e65d4b43d586f0994337) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I660cb9d8bd13c765c89b54b0807b5b3ee836e807 Reviewed-on: http://review.coreboot.org/8614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-07tegra132: add preboot MTS to bct generationAaron Durbin
The preboot MTS microcode needs to be supplied within the bct so the BootROM can load it. The size of the bootblock space in SPI needed to be extended to accomodate the extra length. BUG=chrome-os-partner:29059 BUG=chrome-os-partner:29060 BRANCH=None TEST=Built rush with updated cbootimage with t132 support. Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204940 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11 Reviewed-on: http://review.coreboot.org/8466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-073rdparty: Update submodule to get Tegra 132 binariesMarc Jones
Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8613 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-06AMD Fam10h: Only create _PR scope if it is filled inPatrick Georgi
The former pstates_algorithm() function has two early exit points now, and so it might never get around to writing pstates data. Change-Id: I19ca937375c6d33b78bd5b1859fa5c25473be9b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/8610 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-06Move generation of build.h into a shell scriptMartin Roth
Moving the routines that create build.h into a script offers several advantages. We can create more complex functions to run and we don't have to deal with both bash and Make at the same time. This script combines what is currently in Makefile.inc with a couple of updates. - Update how it determines whether to use git for the timestamp - Move the git revision string generation inside the routine that checks to see if we have git. - Add a timeout for the domain name check. Change-Id: I93c131e8d01a0099eb13db720fa865c627985750 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8428 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05AMD Fam10h: sanity check some CPU dataPatrick Georgi
If a certain register returns crap values, we determine core_power using an uninitialized variable. That doesn't sound healthy. Change-Id: I1e890b78bfcc3bf0255a3d4f6561a783134b1719 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8508 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-05storm: Provide ability to build ap148 variantVadim Bendebury
With BOARD_VARIANT_AP148 configuration option enabled the image will be built for 512MB DRAM instead of 1024MB and the mainboard_part_number field in the lb_mainboard entry will be set to "AP148" instead of "Storm". BUG=chrome-os-partner:30440 TEST=manual . built and booted both AP148 and proto0 all the way to reading the kernel . verified that the config file includes correct part number and memory size . verified proper machine IDs reportted when starting the kernel Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207427 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a Reviewed-on: http://review.coreboot.org/8590 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-05arm64: provide early SoC initializationAaron Durbin
Some of the SoC's need an early hook to configure certain registers. One example of this is on t132 where ramstage is the first thing being ran on the arm64 core and it is the only entity that can configure certain registers required for the rest of ramstage. Therefore, provide the opportunity for the SoC to implement such requirements. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran through coreboot. Original-Change-Id: Ib352f3788872f888581b398c9b394b7c4e54b02a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208061 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 2c50e2b39e75d1383e8e573c576630a5b7313349) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I38df63e46c5c21b2d319fc9eb42053c3a0d61bc8 Reviewed-on: http://review.coreboot.org/8595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05rush_ryu: Add new mainboardAaron Durbin
This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05tegra132: add support for TZ carve-outAaron Durbin
The TrustZone carve-out needs to be taken into account when determining the memory layout. However, things are complicated by the fact that TZ carve-out registers are not accessible by the AVP. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and booted to end of ramstage. Noted that denver cores can read TZ registers while AVP doesn't bother. Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494 Reviewed-on: http://review.coreboot.org/8593 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-05coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at initFurquan Shaikh
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR registers should be done with proper bitmask. BUG=None BRANCH=None TEST=Compiles successfully and verified that the RES bits are preserved across register writes. Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207815 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9 Reviewed-on: http://review.coreboot.org/8592 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 03:29:48 +0000