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2022-01-21mb/system76/*: Enable measured bootTim Crawford
Tested by checking PCR-2 data is recorded in cbmem log. Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-21mb/prodrive/atlas: Configure GPIO as per Atlas boardLean Sheng Tan
Update GPIO settings as per schematics v3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I685d0b7274e3a6e707fec37d051f4818860169ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-21mb/system76/gaze15: Set _UID for touchpad devicesTim Crawford
The _UID must be unique as these devices use the same _HID. Fixes BSOD when booting Windows 10. Change-Id: I67fda892a496dc9e5a6fa5e133ff0b35cde8fce7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-21mb/google/brya/var/gimble{4es}: Decrease touchscreen T3 timing to 200msScott Chao
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to the delay until the kernel driver accesses the device, delaying only 200ms in the ACPI method is also sufficient to meet the 300ms requirement. BUG=b:210772498 BRANCH=none TEST=build and test touchscreen function on DUT. TEST=suspend, wake DUT and check touchscreen function. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-21soc/intel/common/gpio: Add PCH `Pad Configuration Lock` optionsSubrata Banik
This patch provides the possible options for PCH to allow `Pad Configuration Lock`. `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake Point (TGP) and Alder Lake Point (ADP) PCH. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-21soc/intel/common/gpio: Use const variable to get gpio bitmaskSubrata Banik
This patch introduces a `const bit_mask` variable to hold the gpio PAD mask value prior to sending the lock configuration command using the sideband interface. Additionally, this patch fixes the PAD lock overridden issue as below: Without this code change every consecutive PAD lock operation resets other bits in that register as below: After Locking pad 2 , pcr_read=0x4 After Locking pad 3 , pcr_read=0x8 After Locking pad 4 , pcr_read=0x10 After Locking pad 5 , pcr_read=0x20 After Locking pad 6 , pcr_read=0x40 After Locking pad 7 , pcr_read=0x80 After Locking pad 8 , pcr_read=0x100 With this code change all previous lock bits are getting preserved as below: After Locking pad 2 , pcr_read=0x4 After Locking pad 3 , pcr_read=0xc After Locking pad 4 , pcr_read=0x1c After Locking pad 5 , pcr_read=0x3c After Locking pad 6 , pcr_read=0x7c After Locking pad 7 , pcr_read=0xfc After Locking pad 8 , pcr_read=0x1fc BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I342a666aa2d34bcc8ba33460396d1248f0c0f89f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60999 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-21soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR configCurtis Chen
ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them into the same group core "ADL_P_282_482_28W_CORE". BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21mb/google/brya/var/kano: Prevent camera LED blinking during bootJim Lai
Camera LED blinks as sensor is being probed during kernel boot, which misleads user to belive camera has been turned on. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:214155527 TEST=Build and boot Kano to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Jim Lai <jim.lai@intel.com> Change-Id: I92f1e88d0fcce49660a95d4402c8c4161e320168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61109 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-21mb/google/puff/var/dooly: Add fw_config probe for ALC5682-VD/ALC5682-VSTony Huang
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:210501484 BRANCH=puff TEST=build Change-Id: I84bc378d6b00828366309be7dbf56a61702a14da Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-01-21lib/cbmem_console: Move copy_console_buffer up in the fileRaul E Rangel
This will make the method available earlier. This is needed for the next CL. BUG=b:213828947 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iee911a2debcfbf4309d2e866401b74f2a6c18feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-21soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-21soc/intel/icl: Rework on HECI1 disable configsSubrata Banik
The only option to make HECI1 function disable on Ice Lake SoC platform is using SBI under SMM mode. Hence, this patch makes DISABLE_HECI1_AT_PRE_BOOT=y default and selects `HECI_DISABLE_USING_SMM` config for Ice Lake. Also, drop `HeciEnabled` from chip configuration and guard heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-20soc/amd/picasso/bootblock: drop unused includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I837e1f8727adefb9227ac7df2ff715245957be2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-20soc/amd/cezanne,picasso: factor out common early non-car cache setupFelix Held
This implementation is the same for all SoC that select SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR CPU support code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-20soc/amd/cezanne/include/espi.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I393feab8550a7124ab2982ff3d256e3491d27b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-20soc/amd/common/vboot: Verify the size of the transfer bufferRaul E Rangel
This will verify that signed verstage binaries and the bootblock code executing agree on the transfer buffer struct size. BUG=b:213828947 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I597e38fe0a37416ffd3bc01fd974fa8f6610a88c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-20mb/google/brya/var/banshee: update gpio settingsIvy Jian
Configure GPIOs according to schematics BUG=b:214871796 TEST=emerge-brya coreboot Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id6862ff442310953b4749cef7880814f3c3f6d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-20mb/google/brya/var/banshee: Add SODIMM supportEric Lai
Banshee will use SODIMM. Add memory.c to override baseboard. BUG=b:208910227 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I4d2fe986b786b3553b67910b589fce12647ee69a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-20mb/google/brya: Add MEMORY_SODIMM and MEMORY_SOLDERDOWN configEric Lai
MEMORY_SOLDERDOWN puts SPD in cbfs and read part number from CBI. MEMORY_SODIMM puts SPD cache in FMAP. BUG=b:208910227 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idab48293fb5b584ecb4c8f270d2c376456954553 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-20mb/google/brya: Create banshee variantIvy Jian
Create the banshee variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:214871796 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_BANSHEE Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ib4f943a109f945204a9b0a8de9b99580bf01c87e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-20libpayload/Makefile.inc: Fix ar calls to support llvm-arJakub Czapiga
llvm-ar does not support "open" script command, and fails with an error. This patch fixes it by removing lines `$(AR) rc <object-files>` and it puts them as "addmod" commands. This way all object files and archives can be packed into one archive. Change-Id: I0c53d1d613b5edc321e268d1d996fac3146680f8 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-20efi_datatype: Add typedef for EFI_PHYSICAL_ADDRESSAnil Kumar
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ie09e337ee1790a06689681fca087edcfd89d215f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-19soc/intel/alderlake: Add method to determine the cpu typeSridahr Siricilla
set_cpu_type(): It determines the CPU type (big or small) that is executing the function, and marks the global_cpu_type's array slot which is corresponds to the executing CPU's index if the CPU type is big core. get_cpu_index(): It determines the index from LAPIC Ids. This is required to expose CPPC3 package in ascending order of CPUs' LAPIC ids. So, the function returns CPU's position from the ascending order list of LAPIC ids. TEST=Tested CPU index calculation, core type determination on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-19mb/google/brya/var/{taeko, taeko4es}: Add gpio.c in romstageKevin Chang
Add file gpio.c in romstage. BUG=b:213828931 TEST=Build FW and system can power on normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ie868fe7ada9deb8918d6c7ba538332cbe539ee44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-19arch/riscv: Fix some SMP related headersKyösti Mälkki
Change-Id: I58419450dbe34741b4f5b4920f435fdb91e9df22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-19src: Remove unused <stdbool>Elyes HAOUAS
Change-Id: I8567a567d979bcc0c1c710f6f231d7ecdc82b126 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-19soc/intel/alderlake: Rework the GPIO PAD Pin numbersSubrata Banik
This patch creates a `relative increment by 1` macro to let SoC gpio pad configuration to be more flexible while adding support for newer PCH SoC. With this changes adding GPIO controller support for PCH-N would become really simple without too much of code duplication. For example: ADL-N has added `GPP_I` pins into community 1 hence, the additional code for `PCH-N` whould appear incremetal to ADL-P. > #define GPP_B 0x0 > #define GPP_T INC(GPP_B) > #define GPP_A INC(GPP_T) > #define GPP_R INC(GPP_A) > #define GPD INC(GPP_R) > #define GPP_S INC(GPD) > if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) > #define GPP_I INC(GPP_S) > #define GPP_H INC(GPP_I) > #else > #define GPP_H INC(GPP_S) > #endif > #define GPP_D INC(GPP_H) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-19mb/google/cherry: add configuration for dojoKevin Chiu
BUG=b:211528578 TEST=emerge-cherry coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I3bd9803b4e47882df9fe351229478e4cb1630363 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-19mb/google/dedede/var/bugzzy: Add SAR sensorSeunghwan Kim
Present the Semtech SX9360 SAR sensor that protects the LTE antenna. The sensor is connected to i2c bus I2C1. BUG=b:194318328 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59609 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-19driver/i2c: Add sx9360 driverSeunghwan Kim
Add driver for setting up Semtech sx9360 SAR sensor. The driver is based on sx9310.c. The core of the driver is the same, but the bindings are slightly different. Registers are documented in the kernel tree: Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml [https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/] Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-183rdparty/amd_blobs: advance submodule pointerRaul E Rangel
This adds the following commits: * 22ce1b5 cezanne: Upgrade SMU to 64.60.0 * dd37ad2 cezanne: Update ABL to 0x1B096070 * 01fbf5d cezanne: Update SMU to 64.58.0 * f638765 cezanne: Update ABLs to 0x1A296070 BUG=none TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8f51cb007ce4127428b7b81095fb2c7afb33e608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-18soc/amd/{picasso,cezanne}: Enable CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel
This will help debugging verstage failures. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are printed before bootblock messages. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia60991b3e81c19c24ceb69193840dde873ef3346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-18mb/intel/adlrvp: Add wake events for AC connect/disconnectKrishna Prasad Bhat
Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP. BUG=None BRANCH=None TEST=Verify board wakes from S0ix on AC connect/disconnect. Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-18soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat
Add eMMC device into chipset.cb and keep it `off` by default. eMMC device is applicable only for Alder Lake N SOC. Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat
Add eMMC device ID for Alder Lake N SOC. Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18mb/intel/adlrvp_n: Configure EC in RW GPIOKrishna Prasad Bhat
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). BRANCH=None BUG=None TEST=Issue manual recovery and confirm DUT is entering recovery mode. Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18src/include/acpi: Move CPPC_PACKAGE_NAME macro definitionSridhar Siricilla
The patch moves the CPPC_PACKAGE_NAME macro definition from file acpi/acpigen.c to include/acpi/acpigen.h file since the CPPC_PACKAGE_NAME method will get called from cpu/intel/common in a later patch. TEST=Built the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-18mb/google/brya/var/brask: Turn on I2C1 for TPMAlan Huang
The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch turns on I2C1 and turns off I2C3. BUG=b:211886429 TEST=Test if proto 1 can boot into Chrome OS successfully. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I0e94c900b48adf10880aae2abb47e08d1bd9e19b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-01-18Documentation: gpio: Fix tableSubrata Banik
This patch fixes the indentation issue introduced with commit 0c1c2dec (Documentation: Capture anomalies between pad and lock reset type). BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib6974cda26e6f7968688a2a7c30c7351d212a780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-18soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen
Host device id 0x4619 is missed in few coreboot tables so that coreboot can't recognize and config it properly. Document Number: 690222 BUG:b:214665785, b:214680767 Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-17sb/intel/common/firmware: Reword me_cleaner warningAngel Pons
That vendor firmware still works after applying `me_cleaner` doesn't mean that coreboot will also work with the same broken ME firmware. Instead, one should first test coreboot with the original, unmodified ME firmware to make sure coreboot works properly, and only then consider using `me_cleaner` with coreboot. Otherwise, one would end up with a non-booting or otherwise misbehaving system when trying to use coreboot and `me_cleaner` without having tested coreboot with the original ME firmware beforehand, which is hard to diagnose as the problem may only happen when the ME isn't running normally. Change-Id: I1626d747a99969faf7db37c10cf7d87e3977744a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-17Update chromeec submodule to upstream mainzhixingma
Updating from commit id 4c21b57eb: 2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions) to commit id e486b388a: 2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change) This brings in 2212 new commits. Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: I4437f09c3193ec7c89f7f9550940a0fa5464a511 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Thejaswani Putta <theja427@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2022-01-17mb/google/auron: Remove addition of EC firmware to buildTim Wawrzynczak
In https://crrev.com/c/3069716, the samus EC firmware was removed from the `main` branch, therefore in order to update the `chromeec` 3rdparty submodule, the automatic build and inclusion of samus EC firmware into coreboot's `master` branch has to be dropped as well. Change-Id: I6fcdd3b7925b6ec33ba48892ed750c29bb60634c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-17cr50: Increase cr50 i2c probe timeoutRob Barnes
Turns out 150ms isn't enough in the worst reset conditions. On guybrush the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50 is woken up and initialized early during S0i3 resume. Occasionally the CR50 isn't ready before the probe times out. BUG=b:213828947 BRANCH=None TEST=suspend_stress_test -c 1000 Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
2022-01-17drivers/intel/fsp2_0: Add FSP 2.3 supportAnil Kumar
FSP 2.3 specification introduces following changes: 1. FSP_INFO_HEADER changes Updated SpecVersion from 0x22 to 0x23 Updated HeaderRevision from 5 to 6 Added ExtendedImageRevision FSP_INFO_HEADER length changed to 0x50 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 Following changes are implemented in the patch to support FSP 2.3: - Add Kconfig option - Update FSP build binary version info based on ExtendedImageRevision field in header - New NV HOB related changes will be pushed as part of another patch Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-17mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17mb/google/brya/var/taeko4es: Enable Bayhub LV2 driverKevin Chang
Some SKUs of google/taeko4es have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 TEST=Build FW and checking SD card reader register is correct. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I3d2ea3db9df38e7b0cac4c32e1fca579ff43e5bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHzSeunghwan Kim
When using the default initial core display clock frequency (648MHz), Jasper Lake board might have a rare stability issue where the startup of Chrome OS in secure mode may hang during re-initializing display in kernel graphic driver. Bugzzy didn't show this problem so far, but Intel recommends slowing the initial core display clock frequency down to 172.8 MHz to prevent this potential problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for bugzzy. BUG=None BRANCH=dedede TEST=Build firmware and check the DUTs can boot up in secure mode well. Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-17pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly
Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-17soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake and ensures disable_heci1() is guarded against this config. Also, makes dt CSE PCI device `on` by default. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-17Revert "mb/google/dedede/var/beadrix: Remove SD controller"Teddy Shih
This reverts commit bcd7873ea80be0ee576a10e6a11b7dcf8294ffb5. Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. ================ error log ================ ... Starting depthcharge on Beadrix... src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5. =========================================== BUG=b:204882915 BRANCH=None TEST=Build and boot into OS. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17mb/google/dedede/var/beadrix: Add memory part and generate DRAM IDTeddy Shih
This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:204882915, b:210123929 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibff150bb4e742f32641da661cfca6594d18c52e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60242 Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17mb/google/brya/var/agah: update gpio overrideTony Huang
Configure GPIOs according to schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: Icfd1e09761e51aca9c23f3ab340adac7a66a3ada Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17console: Add Kconfig to dump pre-bootblock cbmem contentsRaul E Rangel
Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not have the ability to log to the UART, so their console messages are inaccessible until the boot processes gets into the payload or OS. This makes it difficult to debug verstage. This feature will dump the pre-bootblock CBMEM console immediately after the bootblock console is initialized. I chose to do this in console_init instead of bootblock_soc_init because I wanted to have the pre-bootblock contents dumped before the coreboot bootblock starting message is printed. BUG=b:213828947 TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped to the UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-17console/cbmem: Add cbmem_dump_consoleRaul E Rangel
This function is similar to cbmem_dump_console_to_uart except it uses the normally configured consoles. A console_paused flag was added to prevent the cbmem console from writing to itself. BUG=b:213828947 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3fe0f666e2e15c88b4568377923ad447c3ecf27e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-17src: Remove unused <cbfs.h>Elyes HAOUAS
Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-17drivers/i2c/tpm/Kconfig: Reduce visibility of some configsArthur Heymans
I2C bus and address of the TPM are typically fixed on hardware so there is no need to be able to configure this in menuconfig. Change-Id: I1b6afa68fe753fb76348e0461209d218b14df7cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-17oprom/yabel/io.c: Fix building for ENV_X86_64Arthur Heymans
Unknown if yabel works for X86_64 but now it builds. Change-Id: Iacdb9fde91a992b5010120f5824383ca4aebdd1a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-17oprom/realmode/x86.c: Fix building for ENV_X86_64Arthur Heymans
Not tested on hardware. Change-Id: I8ce8d56da326aeff5ff9b400ded02d4309372519 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-16soc/intel/common/cse: Add helper API for CSE SPI Protection ModeSubrata Banik
This patch checks if CSE's spi protection mode is protected or unprotected. Returns true if CSE's spi protection mode is protected, otherwise false. BUG=b:211954778 TEST=Able to build and boot brya with this change. Calling `cse_is_hfs1_spi_protected()` in coreboot is able to provide the SPI protection status. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/common: Abstract the sideband accessJohn Zhao
The existing Sideband access is with the PCH P2SB. There will be future platforms which access the TCSS registers through SBI other than the PCH P2SB. This change abstracts the SBI with common API. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-16soc/intel/denverton_ns: Add the Primary to Sideband Bridge definitionJohn Zhao
This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-15arch/x86/spinlock.h: Support systems with >128 coresArthur Heymans
Each time the spinlock is acquired a byte is decreased and then the sign of the byte is checked. If there are more than 128 cores the sign check will overflow. An easy fix is to increase the word size of the spinlock acquiring and releasing. TEST: See that serialized SMM relocation is still serialized on systems with >128 cores. Change-Id: I76afaa60669335090743d99381280e74aa9fb5b1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60539 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-15libpayload: Install vboot headers and add include paths to lpgccJakub Czapiga
New CBFS API uses commonlib/bsd/cbfs_serialized.h, which includes vboot's vb2_sha.h. And, because vboot's includes are not available in libpayload's installation directory nor in lpgcc paths, it was causing compilation errors. This patch fixes this issue. lpgcc will look for `vboot` directory like it is doing for `include` directory to create correct paths. However, if payload will be built using libpayload's build dir as a base, then vboot headers from 3rdparty/vboot will be used, as there is no way to pass VBOOT_SOURCE from makefile to lpgcc. Moreover, this patch moves VBOOT_SOURCE to the main Makefile to make it available for installation target, to install headers from vboot directory provided by caller. Change-Id: I68dd7e1545cfcaf24547d8a9fe289447c79da222 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reported-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-14util/cbfstool: Port elogtool to libflashromEdward O'Callaghan
This also uncouples cbfstool from being overly Chromium specific. However the main objective is to not subprocess flashrom any more and instead use the programmatic API. BUG=b:207808292 TEST=built and ran `elogtool (list|clear|add 0x16 C0FFEE)`. Change-Id: I79df2934b9b0492a554a4fecdd533a0abe1df231 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-01-14mb/google/brya/var/redrix{4es}: Add host device event supportWisley Chen
Adding this host event to the EC SCI event and wake masks allows the system to generate an SCI and/or wake when this event happens. BUG=b:206012072 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4f48244a4fca750a9de2ecc20f24786034d45b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/redrix{4es}: Set tcc_offset value to 3Wisley Chen
The redrix thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:200134784 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ifb63d63bc741b2a402328f256b43bc83e0a88a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/anahera{4es}: Set tcc_offset value to 3Wisley Chen
The anahera thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:214088543 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14mb/google/brya/var/felwinter: Update USB Type-C PLDEric Lai
After kernel change landed on Chromium tree. https://lore.kernel.org/r/20210407065555.88110-5-heikki.krogerus@linux.intel.com USB driver will use PLD to match the Type-C port. PLD needs to start from 1. BUG=b:214460183 TEST=boot into OS without kernel panic. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1493e46f8881b2f688f41f32755d4cf5a87e7656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-14tests: Fix tests code and comments styleJakub Czapiga
This patch applies clang-format settings to most of tests files. Some files were fixed "by-hand" to exclude some lines, which whould be less readable after automatic style fixing. Moreover, some comments (mostly in tests/lib/edid-test.c) were adjusted to match coreboot coding style guidelines. Change-Id: I69f25a7b6d8265800c731754e2fbb2255f482134 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-01-14mb/google/brya/var/felwinter: Update audio_amp fw config field nameEric Lai
https://github.com/thesofproject/linux/pull/3271 Felwinter will use the OEM string for SOF tplg loading. Update the name that match to the kernel driver. BUG=b:210061842 TEST=dmidecode can show AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib6114d047762ba26071c9cdc6c43d80f933c1eb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61070 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14mb/google/brya0: Enable CNVi DDR RFIM for brya0 variantRonak Kanabar
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for brya0 variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=b:201724512 BRANCH=None TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value. Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-01-14mb/google/brya: move SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to commonEric Lai
ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem and prefetch mem. BUG=b:206739931 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14libpayload: Fix legacy CBFS code after recent refactoringJulius Werner
The goal when adding the new CBFS API in CB:59497 was that the old CBFS code would be left completely untouched and just moved to the side a bit, so that it could continue to work for the payloads that use it until they all have time to transition to the new CBFS API. Unfortunately, between the different iterations of the patch something went wrong with that and the final committed version of cbfs_legacy.c does differ in some parts from the original code, including a changed macro definition that breaks decompression support. This patch restores all the legacy CBFS files to exactly what they used to be (other than the necessary changes in cbfs_core.h to avoid double definition clashes). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-01-14soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14libpayload/libcbfs/Kconfig: Make CBFS_VERIFICATION depend on VBOOT_LIBJakub Czapiga
CBFS_VERIFICATION was depending on the VBOOT instead of on VBOOT_LIB, which made enabling CBFS_VERIFICATION impossible. VBOOT is not available, like in the main coreboot, but is was changed to VBOOT_LIB, and was not correctly adjusted in patch instroducing CBFS_VERIFICAITON option. Change-Id: Ie23bad5f0ed3faf17a2ed7a3ad99310ee803edd2 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-14mb/google/brya/var/agah: update overridetreeTony Huang
Init basic override devicetree based on initial schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: I7b7badacce27dd7da4f138c6f2465af518715e7f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60837 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-14Makefile: Defer normalizing configuration for reproducible buildsPatrick Georgi
The call to genbuild_h needs to happen after xcompile is imported so that genbuid_h can use iasl as chosen by xcompile. Move the entire section down to keep things together. TEST=no more error that util/crossgcc/xgcc/bin/iasl isn't found. Change-Id: Ia7afd32bd120e5405e65825144b0c30d69931a22 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner
Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner
Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-14src/{drivers,lib}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifad13ef418db204cf132fe00f75c6e66cd2bc51b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-13mb/google/brya: Adjust CSE RO and Data partition in the CSE regionSridhar Siricilla
The patch adjusts CSE region's internal partitions' (CSE RO and Data partition) sizes to match with sizes of MFIT generated CSE Region's internal partitions. BUG=b:213993778 TEST=Generate coreboot for Brya and verify with MFIT generated coreboot. Cq-Depend: chrome-internal:4452789 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-13mb/google/brya: Variants with ESx SoC use NEM for CARSubrata Banik
This patch ensures all brya variants with Alder Lake ESx SoC are using NEM by default for CAR set up. Default CAR configuration for QS SoC is eNEM. BUG=b:168820083 TEST=Able to build and boot brya0 variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-13Documentation: Capture anomalies between pad and lock reset typeSubrata Banik
This patch documents the recommendation as per Intel GPIO BWG on GPIO PAD lock configuration. As per GPIO BWG, it's recommended to change the Pad Reset Config for lock GPP as `Power Good` so that pad configuration and lock bit can be reset at the same time. Refer to Intel doc:630603 for details. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3faf5dfc28c8c2dbc322db80a59f44a29002673c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-01-13soc/amd/*/chip.h: add missing gpio.h includeFelix Held
Since we need the GPIO defines in the devicetree settings, include gpio.h in each SoC's chip.h file which will indirectly include the soc-specific soc/gpio.h header instead of having it indirectly included via soc/i2c.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro
The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-13mb/google/brya/var/felwinter: Update ELAN touch HIDEric Lai
Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008. BUG=b:214010928 TEST=touch screen is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-13soc/mediatek: Fix include guard naming for emi.hYu-Ping Wu
Fix the name of the include guard for soc/mediatek/common/include/soc/emi.h. BUG=none TEST=emerge-corsola coreboot BRANCH=none Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-01-13console/cbmem_console: Rename cbmem_dump_consoleRaul E Rangel
This function actually dumps cbmem to the UART. This change renames the function to make that clear. BUG=b:213828947 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc314c530125e5303a06b92aab48c1e1122fd18c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12tests: Move EDID test header to include/tests/libJakub Czapiga
Move header to path with all other test headers to make include paths unambigous. Change-Id: Ie2dbb055df658272424df95f58d84caaeba3fc8f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12mb/google/brya/var/taeko: Modify power sequence for SSD deviceKevin Chang
In order to avoid having the FSP fail to detect the SSD device downstream of the RP, its PERST# must be deasserted earlier in the boot flow, therefore move PERST# deassertion to a romstage GPIO table. BUG=b:213828931 TEST=Build FW and run stress exceed 1000 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik
This patch replaces hardcoded `4` (next offset Tx state) with `sizeof(uint32_t)` for calculating 'Tx state offset'. Also, add checks to detect the specific GPIO lock action between `LOCK_CONFIG` or 'LOCK_TX'. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff712b16808e0bc99c575bb2426a4f84b89fdb73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-12sc7180: Update video mode active horizontal/vertical/total calculationsVinod Polimera
Remove vbp & hbp as the names are misleading and use edid variables to simplify the video mode active and total calculations. Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12mb/google/glados/variants/sentry: Increase CPU critical temp threshold to 105CSumeet Pawnikar
During certain kind of test scenario, observed that CPU temperature spikes till 98C and based on current thermal critical policy temperature threshold of CPU set to 98C, it initiates the system wide abrupt shutdown. To avoid this kind of abrupt system shutdown, update cpu critical temperature threshold from 98C to 105C. BUG=b:213476881 BRANCH=glados TEST=Built and booted on glados Change-Id: I56df9285b3c247866a5bfa6dc59d1856544de41c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12device/pci_device.c: Make sure the PCI bus has a deviceArthur Heymans
Some SOC add PCI root busses structs at runtime without adding a device struct to the bus because pci_scan_bus does it. An example would be xeon_sp which has multiple root busses. TEST: ocp/deltalake boots again. Change-Id: I81d9c94652e34dbf9e8cec64fc34ef0042563037 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 02:04:39 +0000