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2022-09-20mb/google/dedede: Resume from suspend on critical batteryIvan Chen
This patch makes dedede EC wake up AP from s0ix when the state of charge drops to low_battery_shutdown_percent. Demonstrated as follows: 1. Boot OS. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 4. 4. System resumes. BUG=b:244253629 TEST=Verified on dedede Change-Id: I39234d2b9e739383b5f96be49077f8c9831fa0fa Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-20soc/intel/alderlake: Explicitly disable Energy Efficiency TurboJeremy Compostella
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo Updateable Product Data (UPD), enabling the Energy Efficient Turbo feature by default. This feature prevents the cores from entering Turbo frequency under heavy load. As a result of this FSP change, coreboot explicitly disables this feature to stay consistent with commit `caa5f59279e Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"'. BRANCH=firmware-brya-14505.B BUG=b:246831841 TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20mb/intel/adlrvp: enable ECT for LP5 memoryZhixing Ma
On ADLRVP with LP5 memory, MRC team recommends enabling ECT(Early Command Training) to avoid hang during boot process. BRANCH=firmware-brya-14505.B TEST=Booted to OS on ADLRVP with LP5 memory. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20mb/google/brya/variants/skolas: Set power limit valuesSumeet Pawnikar
Skolas board is based on Raptor Lake SoC, not Alder Lake. The code change sets CPU power limit values as performance configuration based on various Raptor Lake SoC SKUs as per the document #686872. BUG=b:242869605 BRANCH=None TEST=Built and tested on skolas board Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20qualcomm/sc7280: initialize tu struct with zerosVinod Polimera
Coverity is throwing a bunch of "maybe uninitialized" errors for tu struct. Initialize the tu struct with zero. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: Ie249ad4f53abc91376445420712364a28618a15a Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-09-20mb/google/brask/variants/moli: enable ddc on DDI_PORT_2Raihow Shi
Enable ddc on DDI_PORT_2 for support DP++. BUG=b:240382609 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I475e3c0278cfa92ab40ad84f6da580b4cded9933 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-20soc/intel/alderlake: Add power state thresholdsGaggery Tsai
This patch adds power state 1/2/3 threshold setting interfaces and pass the settings to FSP. BUG=b:229803757 BRANCH=None TEST=Add psi1threshold and psi2threshold to overridetree.cb and enable FSP log to ensure the settings are incorrect. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-20mb/google/dedede/var/boten: Turn off camera during S0ixKarthikeyan Ramasubramanian
Add a variant specific S0ix hook to fill the SSDT table to disable and enable camera during suspend and resume respectively. BUG=b:206911455 TEST=Build Boten BIOS image. Ensure that camera is disabled during suspend and enabled during resume. Change-Id: I3229b22b8d8651bf2d9df25b10ce6749efde7cf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-09-20mb/google/rex: Add WWAN ACPI supportIvy Jian
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. BUG=b:244077118 TEST=check cbmem -c \_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3) \_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL) check PXSX Device is generated in ssdt. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-20mb/google/nissa/var/xivu: Add supported new memory partIan Feng
Add new ram_id:3 (0011) for memory part K3LKCKC0BM-MGCP. DRAM Part Name ID to assign K3LKCKC0BM-MGCP 3 (0011) BUG=b:247039096 TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I78d2e501b9d8d801a3d149002f638125bf4275f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-09-20cpu/intel/haswell: Update Broadwell ULT µcode updatesAngel Pons
The µcode updates for Broadwell come from coreboot's blobs submodule and have not been updated in at least 7 years. Use the µcode updates available in the intel-microcode submodule. This change forgoes some µcode updates for old Broadwell ULT/ULX steppings with CPUID 0x306d2 and 0x306d3, as well as an old µcode update for Haswell ULT/ULX CPUs with CPUID 0x40651 in favor of a newer intel-microcode revision that was already being used: when the µcode updates are concatenated into one file, the newer µcode update revision would be placed before the older revision, so the latter would never be used. Change-Id: I67f8a58552bd211095c183e6f7a219d60e3be162 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-20cpu/intel/haswell: Hook up Crystal Well µcode updatesAngel Pons
Commit 27126f135dad3c0e2f91394e7088b2ff50220146 (cpu/intel/haswell: add Crystal Well CPU IDs) introduced new Haswell CPUIDs but did not include any µcode updates for them. It is unknown how this could have worked as the initial µcode inside the CPU can be quite unstable. Intel CPUs with support for FIT (Firmware Interface Table) can have their µcode updated before the x86 reset vector is executed. The µcode updates for Crystal Well CPUID 0x40661 can be found inside the intel-microcode submodule. There are no publicly available µcode updates for Crystal Well CPUID 0x40660 as it is a pre-production stepping, which is not meant to be used anymore. Hook up the available µcode updates for Crystal Well CPUs. Change-Id: If5264f333e681171a2ca4a68be155ffd40a1043b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-20cpu/intel/haswell: Do not include useless µcode updatesAngel Pons
There are two types of Haswell/Broadwell platforms: Trad(itional) with separate CPU and PCH packages, and ULT/ULX where the CPU and PCH share one package. Mainboards can specify which platform type they are using the `INTEL_LYNXPOINT_LP` Kconfig option. There are so many differences between Trad and ULT/ULX that it's not worth doing runtime detection. The CPUIDs are different for Trad and ULT/ULX platforms, and so are the µcode updates. So, including Trad µcode updates in a coreboot image for an ULT/ULX mainboard makes no sense, and vice versa. Adapt the Makefile so that only relevant µcode updates are added. Also, add a few comments to indicate which updates correspond to which CPUs. TEST=Run binwalk on coreboot.rom to verify included µcode updates for: - Asrock B85M Pro4 (Haswell Trad) - HP Folio 9480M (Haswell ULT/ULX) - Purism Librem BDW (Broadwell ULT/ULX) Change-Id: I6dc9e94ce9fede15cbcbe6be577c48c197a9212a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-19mb/intel/mtlrvp: Add board_info.txtTim Wawrzynczak
Builds are failing on upstream master branch because there is no board_info.txt for the Intel Meteor Lake RVP mainboard; this patch adds a basic one so the tree will build. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3356ad65132dc4aaebd5e7d959a2bdb9ab1316b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67711 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-09-19mb/google/brya/var/skolas: Add MIPI WFC supportAlanKY Lee
Modify config settings based on new module KBAE350 spec BUG=b:245640845 BRANCH=None TEST=Build and boot on skolas Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: I8a9bee9bb79bda4e3f1d259716844b42a7fce397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jimmy Su <jimmy.su@intel.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-09-19soc/intel/apollolake: LZ4 Compress FSP-MArthur Heymans
FSP-M is not run XIP so it can be compressed. This more than halves the binary size. 364544 bytes -> 168616 bytes. On the up/squared this also results in a 83ms speedup. TESTED: up/squared boots. Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19Kconfig: Allow x86 to compress pre-ram stages if not run XIPArthur Heymans
On the intel/glkrvp compressed: - romstage: 29659 - verstage: 31303 non compressed: - romstage: 46244 - verstage: 47012 On qemu (with some additional patch to not run XIP) compressed: - romstage: 11203 non compressed: - romstage: 13924 Even with a small romstage the size improvements are substantial, which should result in a speedup when loading the stage. On the up/squared loading romstage is sped up by 9ms. TESTED: successfully boot the up/squared & google/vilboz. Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19mb/intel/mtlrvp: Add flashmap descriptorJamie Ryu
This adds 32MB flashmap descriptor as below: Descriptor Region: 0x0 - 0x3fff (~16KB) Intel EC Region: 0x4000 - 0x83fff (~512KB) ME Region: 0x84000 - 0x8fffff (~8.5MB) BIOS Region: 0x900000 - 0x01ffffff (~23MB) BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ifb572efe56eb7400b8328ba797892738f5927158 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66098 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/intel/apollolake: Add bits of GEN_PMCON2 registerSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes
Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19mb/prodrive/hermes: Add part numbers to SMBIOSAngel Pons
Adjust the EEPROM layout to account for two new fields: board part number and product part number. In addition, put them in a Type 11 SMBIOS table (OEM Strings). TODO: This currently stores the "raw" part numbers, should we add a prefix to the SMBIOS strings? Change-Id: I85fb9dc75f231004ccce2a55ebd9d7a4867fcb93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67276 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/root_complex: Throttle SOC during low/no batteryTim Van Patten
Use dynamic power and thermal configuration (DPTC) via ACPI ALIB calls to throttle the SOC when there is no battery or critically low battery, to enable the SOC to boot without overwhelming the AC charger and browning out. DPTC is not enabled for low/no battery mode with this CL. It will be enabled for Skyrim in a following CL. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67189 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/acpi/soc: Add DPTC SupportTim Van Patten
Add support for DPTC by calling SB.DPTC() as part of PNOT(). BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19skyrim/overridetree: Add "Throttle" DPTC valuesTim Van Patten
Add the Low/No Battery Mode DPTC values for Skyrim. These values were generated by AMD. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I5f277761cb7379b4344492f95010d8d5ddd689fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67693 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino: Add low/no battery VRM limit registersTim Van Patten
Add DPTC Low/No battery VRM limit registers to throttle the SOC. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/root_complex: Set DPTC VRM limit valuesTim Van Patten
Set the DPTC VRM limit values for normal mode. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I2041a713323f039dcfdacdfa43e74cf450c3c0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67691 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19mb/google/skyrim: Add "Normal" DPTC valuesTim Van Patten
Add the Normal Mode DPTC values for Skyrim. These values were generated by AMD. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino: Add VRM limit DPTC registersTim Van Patten
Add VRM DPTC limit registers. These are required when throttling the SOC for low/no battery mode to prevent the SOC from overwhelming the charger. b/245942343 is tracking passing these additional fields to the FSP and having the FSP configure them. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/acpi: Add low/no battery mode to DPTCTim Van Patten
Update acpigen_write_alib_dptc() to support "low/no battery mode", which throttles the SOC when there is no battery connected or the battery charge is critically low. This is in preparation for enabling this functionality for Mendocino. BUG=b:217911928 TEST=Build zork TEST=Boot nipperkin TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66804 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino/acpi: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. Introduce new CONFIG for Mendocino SoCs similar to what we have for Cezanne. BUG=b:241878652 BRANCH=none Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-19mb/google/rex: Add ELAN6918 touchscreenSubrata Banik
ELAN6918 Power Sequencing seems not perfectly matching with the previous platforms and setting GPP_C06 to high prior to the power sequencing is actually makes it work. Ideally Power Sequencing should be as below for ELAN6918 (in ACPI) `POWER enabled -> RESET deasserted -> Report EN enabled` But below sequence is only working currently: `Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET deasserted (ACPI)` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-19mb/google/brya/var/brya4es: deprecate brya4esNick Vaccaro
The brya4es variant is no longer needed, removing code for brya4es. BUG=b:246611270 TEST=None Change-Id: I9b222f89fe766c63158518713be19d7959451721 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-19mb/siemens/mc_apl1: Do not wait for legacy devices on mc_apl7Werner Zeh
Since there are no legacy devices on the variant mc_apl7 do not wait for them on mc_apl7. Change-Id: Ia4e6c0fb495a347be51bd6604a1d9b73098fb7b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67684 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0Elyes Haouas
Test build for QEMU x86 i440fx/piix4. Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18crossgcc: Upgrade cmake from 3.23.2 to 3.24.2Elyes Haouas
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18cbmem: use aligned_memcpy for reading lb_cbmem_entry informationYidi Lin
The lbtable contains the memory entries that have fields unnaturally aligned in memory. Therefore, we need to perform an aligned_memcpy() to fix the issues with platforms that don't allow unaligned accesses. BUG=b:246887035 TEST=cbmem -l; cbmem -r ${CBMEM ID} Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-17riscv: Enable the newfangled way of selecting instruction setsPatrick Georgi
gcc12+ will require riscv architecture selection to come not only with featurei suffixd charactersa, it also comes with feature_ful suffix_ed words_mith. Much creative, very appreciate. To accommodate for this madness, enable the already existing (but off by default) support for that in our gcc11 build, support using by detecting the compiler's behavior in xcompile and pass that knowledge along to our build system. Then cross our fingers and hope for the best! Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-17security/vboot: Add rollback NVRAM space for TPM 2Miriam Polzer
Create an NVRAM space in TPM 2.0 that survives owner clear and can be read and written without authorization. This space allows to seal data with the TPM that can only be unsealed before the space was cleared. It will be used during ChromeOS enterprise rollback to securely carry data across a TPM clear. Public documentation on the rollback feature: https://source.chromium.org/chromium/chromiumos/platform2/+/main:oobe_config/README.md BUG=b/233746744 Signed-off-by: Miriam Polzer <mpolzer@google.com> Change-Id: I59ca0783b41a6f9ecd5b72f07de6fb403baf2820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-16console: attach smbus console driverHusni Faiz
This patch attaches the smbus console functions to the high level console interface. Change-Id: I3a9bf64e59d529253bfdcdfa565bb2bb92975728 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67341 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16bd82x6x/early_pch: enable smbus in bootblock stageHusni Faiz
SMBus is typically enabled in the ROMSTAGE. To get the BOOTBLOCK console message, the SMBus should be enabled in the BOOTBLOCK stage. Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16drivers/smbus: add smbus console driverHusni Faiz
This patch adds a new smbus console driver and Kconfig options to enable the driver. Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU IDJeremy Soller
The Q0 stepping has a different ID than P1. Reference: CML EDS Volume 1 (Intel doc #606599) Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16soc/intel/alderlake: Set FSP-S GnaEnable based on devicetreeJeremy Soller
Change-Id: Ifd25416c55c4dba1709f74cdedc0c58e881d6266 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16util/kconfig/regex.c: Remove leftoverElyes Haouas
coreboot doesn't support the MIPS architecture anymore. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I404d034949a7786d7971117081537baf27ff2e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-16crossgcc [binutils]: Remove 'enable-plugins' optionElyes Haouas
unneeded 'enable-plugins' option sneaked in..., so remove it. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16crossgcc [binutils]: Remove invalid enable-interwork optionElyes Haouas
'enable-interwork' is not a binutils configure option. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16drivers/usb/hub/acpi.c: Don't use heap for ACPI nameArthur Heymans
Using malloc would increase the heap use each time this function is called. Instead allocate a per struct device buffer inside the chip_info struct. Found by coverity scan, CID 1488815. Change-Id: Ie24870b34338624b3bf3a6f420debdd24a68ffbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64338 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-16mb/google/nissa/var/nivviks: Enable nau8825 ADCOUTEric Lai
Enable nau8825 ADCOUT to make I2S signal meet spec. BUG=b:234789689 TEST=I2S waveform can meet spec timing. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7ea472ac4e4add4e790b9b3fbb6becd40665eb1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-16drivers/i2c/nau8825: Add ADCOUT IO drive strength controlEric Lai
Add a property to control the driving of ADCOUT. BUG=b:234789689 TEST= build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibbedd5838a795ee645a5458b960062c5530ff3b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-16soc/intel/common: Update comment on HFSTS1.spi_protection_modeSridhar Siricilla
The patch updates comment on HFSTS1.spi_protection_mode. The spi_protection_mode indicates SPI protection status as well as EOM status (in a single staged EOM flow). Starting from TGL platform, staged EOM flow is introduced. In this flow, spi_protection_mode alone doesn't indicate the EOM status. For information on EOM status, please refer secton# 3.6.1 in doc# 612229. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-16contributing/coding_style.md: Add missing ">"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I2f2cd20139f4cdb7ba665e9e49a03faea1ac085b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik
This reverts commit 510a55d4eeaeb32047c17328ef238b55b89e7296. Reason for revert: Observed `missing read resource` issue for cnvi device BUG=b:244687646 TEST=No error seen in AP log while booting Google/rex Without this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [ERROR] GENERIC: 0.0 missing read_resources [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done With this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` configSubrata Banik
TEST=Able to build and boot Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I64aab8391f89414754785cea47671f3350324297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16mb/google/rex: Enable `DRIVERS_WIFI_GENERIC` configSubrata Banik
TEST=Able to build and boot the Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iae5317b24856ef2cbd2f36cc28f645826536c21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-15amd/mendocino: Control DPTC with only KconfigTim Van Patten
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-skyrim coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15amd/cezanne: Control DPTC with only KconfigTim Van Patten
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any guybrush boards, similar to .mainboard/google/zork/Kconfig This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-guybrush coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15zork: Control DPTC with only KconfigTim Van Patten
Moving the config value SOC_AMD_COMMON_BLOCK_ACPI_DPTC to soc/amd/picasso/Kconfig and conditionally enabling it for only Morphius boards makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=Build zork Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ic54a9bb491234088be8184bec8b09e2e31ffa298 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15soc/amd: Do SMM relocation via MSRArthur Heymans
AMD CPUs have a convenient MSR that allows to set the SMBASE in the save state without ever entering SMM (e.g. at the default 0x30000 address). This has been a feature in all AMD CPUs since at least AMD K8. This allows to do relocation in parallel in ramstage and without setting up a relocation handler, which likely results in a speedup. The more cores the higher the speedup as relocation was happening sequentially. On a 4 core AMD picasso system this results in 33ms boot speedup. TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM is correctly relocated with the BSP correctly entering the smihandler. Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber
Some PCI IDs were missing, and at least one (SPT's fast SPI device in a generic SPI driver) was wrong. Hence, this patch actually changes behavior depending on the devices actually present in a machine. In this patch the Skylake devicetree is written in a single-line style. Alternative, the device operations could be put on a separate line, e.g. device pci 00.0 alias system_agent on ops systemagent_ops end Tested on Kontron/bSL6. Notable in the log diff is that the CSE and SATA drivers are hooked up now. Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-15sconfig: Allow to specify device operationsNico Huber
Currently we only have runtime mechanisms to assign device operations to a node in our devicetree (with one exception: the root device). The most common method is to map PCI IDs to the device operations with a `struct pci_driver`. Another accustomed way is to let a chip driver assign them. For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI ID lists grew very large and are incredibly error-prone. Often, IDs are missing and sometimes IDs are added almost mechanically without checking the code for compatibility. Maintaining these lists in a central place also reduces flexibility. Now, for onboard devices it is actually unnecessary to assign the device operations at runtime. We already know exactly what operations should be assigned. And since we are using chipset devicetrees, we have a perfect place to put that information. This patch adds a simple mechanism to `sconfig`. It allows us to speci- fy operations per device, e.g. device pci 00.0 alias system_agent on ops system_agent_ops end The operations are given as a C identifier. In this example, we simply assume that a global `struct device_operations system_agent_ops` exists. Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I664f5b7d354b0d9a7144c25604ae4efbdd9ba9a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-15mb/ocp: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie5fc0a8230cdcc24ad1d2d94cc6d019ff10aac48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-15soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-15src/security: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I3def65c016015d8213824e6b8561d8a67b6d5cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-15mb/google/mistral/verstage.c: Change loglevel prefixElyes Haouas
BIOS_ERR is inappropriate since the message is informational. Use BIOS_INFO instead. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I91be3f47ae93c8262e430a06cacec3d2c29ebd58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-15util/ifittool: Error out if microcodes do not fit the FIT tableJeremy Compostella
parse_microcode_blob() returns success when it reaches max_fit_entries microcode. It makes the FIT table size verification in fit_add_microcode_file() useless. This patch makes parse_microcode_blob() error out if max_fit_entries is reached. Note that this size verification is critical as a FIT table only partially listing the microcode patches can lead to boot failures as recently observed on Raptor Lake-P. BRANCH=firmware-brya-14505.B BUG=b:245380705 TEST=compilation errors out when trying to stitch more than CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2022-09-15cpu/intel/haswell: Allow up to six microcodes in the FIT tableJeremy Compostella
Haswell and Broadwell platforms usually stitch six microcode patches. It has worked so far with the default value of four thanks a bug which is being fixed by `util/ifittool: Error out if microcodes do not fit the FIT table' commit. BUG=b:245380705 TEST=Jenkins build without failing on the FIT table size Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I23bf79a3e8918499f6c51e6ef829312d5872181a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-14zork/Kconfig: Move SOC_AMD_COMMON_BLOCK_ACPI_DPTCTim Van Patten
Move enabling SOC_AMD_COMMON_BLOCK_ACPI_DPTC from soc/amd/picasso/Kconfig to mainboard/google/zork/Kconfig and conditionally enable it only for Morphius boards. This reduces which boards/variants have DPTC enabled to only those that actually use it. BRANCH=none BUG=b:217911928 TEST=Build zork Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Iddebcf5dbadae135c8110e2afd9ad76ef7dcc09d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67637 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14acpi/soc: Conditionally include dptc.aslTim Van Patten
Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/amd/cezanne/Kconfig: add defaults for FSP_M_FILE and FSP_S_FILEFelix Held
Now that the FSP binary check logic is fixed to only check the FSP files if ADD_FSP_BINARIES is selected, the default paths for the not yet published Cezanne FSP binaries can be added without breaking abuild. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9950a1fe7bd1b21109cca9631de1a8f1d265d9b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-14soc/amd/common/fsp: only check FSP_M size if ADD_FSP_BINARIES selectedFelix Held
Only check if the FSP_M size is small enough to fit inside the memory region reserved for it if ADD_FSP_BINARIES selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6a115412c113eb0d02b8d4dfc2bb347305f97809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-14util/lint: Add a check for touchpads using the "probed" flagMatt DeVillier
As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag") all touchpads in the tree have been switched from using the 'probed' flag to 'detect.' Add a lint check to ensure no touchpads are added with the probed flag. TEST=manually change one touchpad to use 'probed' flag and ensure lint check catches it. Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14mb/amd/gardenia: deselect HAVE_PIRQ_TABLE and drop incorrect irq_tablesFelix Held
This file isn't correct, since the Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-14mb/google/kahlee: drop unused and incorrect irq_tables.cFelix Held
This file is neither included in the build nor correct, since the Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14 function 4. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0daed891984faed9fbc36f0215edfc56e0ae14a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-14mb/google/skyrim/winterhold: Use 'detect' vs 'probed' for touchpadsMatt DeVillier
As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag") all touchpads in the tree have been switched from using the 'probed' flag to 'detect.' Winterhold was added in between the time that patch was pushed and merged, so switch these instances over too. Change-Id: I34e1265ecd6409f720ae486926c5078f626fc693 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67487 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14cpu/amd: Move locking SMM as part of SMM initArthur Heymans
Locking SMM as part of the AP init avoids the need for CONFIG_PARALLEL_MP_AP_WORK to lock it down. Change-Id: Ibcdfc0f9ae211644cf0911790b0b0c5d1b0b7dc9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64871 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14cpu/amd/smm: Move MP & SMM init in a common placeArthur Heymans
Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/amd/common: Add common function to get cpu countArthur Heymans
This is the same for all supported AMD hardware. Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14soc/amd: Recalculate the field power in PSS table entryZheng Bao
Being divided by 1000 causes data loss and the loss is expand by muliplication. So we just set a lower divisor before muliplication. BUG=b:185922528 Change-Id: Ib43103cc62c18debea3fd2c23d9c30fb0ecd781b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-143rdparty/opensbi: Update to latest ToTPatrick Georgi
That's 3 years of development, including adapting to new, shiny, Cascade of Attention-Deficit Teenagers[0] induced incompatible assembler syntaxes. Signed-off-by: Patrick Georgi <patrick@coreboot.org> [0] https://web.archive.org/web/20220824045741/https://www.jwz.org/doc/cadt.html Change-Id: I8606700149ca74e93b85d78546a29df2916d39b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-14soc/amd/mendocino: Add support for separate RW A/B partition SPL fileFelix Held
Add support for having different Security Patch Level (SPL) table files in the read-only and the read-write A/B partitions. This allows the SPL table file in the main or RO FMAP partition to only cover the embedded firmware binaries in that partition and have a separate SPL file in the RW A and B partitions that covers the embedded firmware binaries in the RW partitions. BUG=b:243470283 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-14mb/google/dedede/variants/shotzo: Turn off LAN power in S0ixTony Huang
Turn off the LAN power which is controlled by GPP_A10 in S0ix states. For an USB device, the S0ix hook is needed for the on/off operationas to take place. BUG=b:245426120 BRANCH=firmware-dedede-13606.B TEST=emerge-shotzo coreboot check LAN LED off in S0ix states check LAN function ok after suspending 500 loops check SSDT table has MS0X entry Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x41) } Else { \_SB.PCI0.STXS (0x41) } } } Change-Id: I3fcab4a73239b4f006839c0c81e9b4cc74047b77 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-14crossgcc: binutils: Remove invalid enable-multilibs optionElyes Haouas
Looks like somewhere after the original implementation it was renamed to --enable-multilib without the s. 'enable-multilibs' is not a valid option for binutils. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-14soc/intel/cannonlake: Read HPR_CAUSE0 registerAngel Pons
Log the Host Partition Reset Causes (HPR_CAUSE0) register, as done on newer platforms. Change-Id: I35261cefae67649fb7824e5ef3d7eb10add36a53 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-14console/vtxprintf.c: Use | operator for bit operation instead of +Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I478265dcd070dcf3fb2cf2c535b6ca1d86b9a3f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9cf4097518034fa4c3ae1899840ae3a276936f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67581 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Set PLLs to hardware default valuesGarmin Chang
Some PLLs are not used in firmware, so we should keep them as hardware default values. If their modules want to set them, the corresponding drivers should set them in the kernel stage. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9bee18005ffed7fc1785c7fd3c0370c8293064ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/67547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Fix indention in pll.cGarmin.Chang
BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I567d1ded1c3b5e36a25026cec697d43d92d5524c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67546 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Change vpp_sel default mux for 4k supportGarmin Chang
vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source: 1. Change vpp_sel source to mainpll_d6 to run at 416MHz. 2. Change ethdr_sel source to univpll_d6 to run at 416MHz. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I24f133b9b383fd019983cb29a213b47717148e97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14mb/google/geralt: Raise little core CPU frequency from 500MHz to 2GHzRex-BC Chen
To improve boot time, raise little CPU from 500MHz to 2GHz at romstage (before DRAM calibration). FW logs: Check CPU freq: 1999968 KHz, cci: 1600012 KHz TEST=cpu freq and cci freq run correctly. BUG=b:244251006 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ic1bed53669baa15f797c9a952455376a39d29cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67544 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/mediatek/mt8188: Fix some wrong settings for PLLsGarmin Chang
The observed CPU big core frequency is double compared with the current PLL setting. Therefore fix the wrong setting for PLL register APMIXED_ARMPLL_BL. Moreover, we also fix some wrong settings for other PLLs. TEST=CPU frequency of big core CPU is correct and bootup correctly. BUG=b:244215537 Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-14mb/google/rex: Add audio parts ALC5682I-VS and MAX98357Eran Mitrani
BUG=b:232573696 TEST=Able to verify audio playback on Google/Rex with this change. Change-Id: Ia8dfc79e7e4d27828726145156c870733d716899 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66919 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/intel/mtl: Fix GPIO group pad base for ACPIKapil Porwal
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15 kernel pintrl driver: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. BUG=b:232573696 TEST=Tested on Google Rex board. After this change, driver rt5682s is able to claim pinctrl IRQ 358 corresponding to GPP_B06. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake/retimer: Change loglevel prefixIvy Jian
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:244687646 TEST=emerge-rex coreboot before [ERROR] USB Type-C 0 mapped to EC port 0 after [INFO] USB Type-C 0 mapped to EC port 0 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-14soc/intel/meteorlake: Enable TcssDma1EnIvy Jian
Adding support enables/disables TcssDma1En by usb4_params. BUG=b:244687646 TEST= TcssDma1En is enabled as expected. before patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [INFO ] PCI: Static device PCI: 00:0d.3 not found, disabling it. after patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [SPEW ] PCI: 00:0d.3 [8086/0000] bus ops [DEBUG] PCI: 00:0d.3 [8086/7ec3] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I9cd8fc3819f533e9581fea19d4da48283888cc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67534 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake: Enable tbtPcie2/3Ivy Jian
Adding support enables/disables tbtPcie2/3 by usb4_params. BUG=b:244687646 TEST= TRP2/3 are enabled as expected. before patch [INFO ] PCI: Static device PCI: 00:07.2 not found, disabling it. [INFO ] PCI: Static device PCI: 00:07.3 not found, disabling it. after patch [DEBUG] PCI: 00:07.2 subordinate bus PCI Express [DEBUG] PCI: 00:07.2 [8086/7ec6] enabled [DEBUG] PCI: 00:07.3 subordinate bus PCI Express [DEBUG] PCI: 00:07.3 [8086/7ec7] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-13mb/google/dedede: Generate MS0X entry and provide variant hookTony Huang
BUG=b:245426120 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot check SSDT table has MS0X entry Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) {} Else { } } } Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-13mb/google/poppy/nami: Add 'detect' flag for Elan touchpadMatt DeVillier
Add the 'detect' flag to the Elan touchpad, so coreboot can determine which touchpad type is present at runtime and generate the correct ACPI entry for it (the Synaptics touchpad already has the flag). Test: build/boot google/nami, verify touchpad works under Linux/Windows Change-Id: I437d1d470552d55496dfe611f441331127c64250 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 12:34:26 +0000