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2022-11-17soc/intel/common/block/sgx/Kconfig: Add missing default symbolElyes Haouas
default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB. Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/amd/common/pi/def_callouts.c: Fix log messagesElyes Haouas
It is no longer necessary to explicitly add "Warning" in front of BIOS_WARNING message. Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing modeReka Norman
As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, 1 and 2 are already checked. Add a check for 3 as well. Also add logs for each individual criteria so it's easy to tell why the overall Manufacturing Mode is set or not. BUG=b:255462682 TEST=On a nivviks which has not gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO After: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Manufacturing Vars Locked : NO On an anahera which has gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES After: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES [DEBUG] ME: FPFs Committed : YES [DEBUG] ME: Manufacturing Vars Locked : YES Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69324 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/alderlake: Update ME HFSTS register definitionRizwan Qureshi
Update Alder Lake CSME HFSTS registers definitions as per Intel doc #627331 revision 1.0.0, section 3.4.8. Follow up CLs will use the bit definitions for performing various checks. TEST=build and boot nivviks platform Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/starlabs/starbook/kbl: Drop redundant option codeAngel Pons
Commit 9bbc039c457774dbeb44ea37ecc6507144d49b61 ("soc/intel/skylake: Hook up FSP hyper-threading setting to option API") already hooks up the `hyper_threading` CMOS option in SoC code, so there's no need to do it from mainboard code. Change-Id: I602452266a8465cced12454f800ea023f382ba6f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69522 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/supermicro/x11-lga1151-series: Fix CMOS optionsAngel Pons
The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17sb/intel/i82801dx: Improve LPC device early initKyösti Mälkki
Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17sb/intel/common: Fix GPE0 related register conflictKyösti Mälkki
When ACPI GPE0 block was extended to 64 events or 8 bytes, ACPI PM register space was slightly modified. After adjustment, PM2_CNT register moved to 0x50 where register SS_CNT was previously defined to be. For platforms that have a valid use for PM2_CNT==0x50 in their FADT, remove overlapping definition of SS_CNT. On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status() incorrectly addressed also GPE0_EN register. For a bit cleaner implementation, define GPE0_HAS_64_EVENTS. Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-17sb/intel/common: Drop duplicate smi_set_eos()Kyösti Mälkki
We have equivalent southbridge_smi_set_eos(). Change-Id: I03a48f0ec9efac2a220aa4ca502a5f504d78c585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17mb/emulation/qemu-q35: Split smm_close() and smm_lock()Kyösti Mälkki
Change-Id: I6d8efe783e6cc5413c3fd0583574a075a2c3876b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEGKyösti Mälkki
If TSEG is not enabled, smm_region() should not reserve the region, so add a test for T_EN flag in ESMRAMC. For the SMM_ASEG case this moves CBMEM immediately below top-of-ram. Change-Id: I2da4b846d0767afe00e98fdee375914c1875ddf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17soc/intel/meteorlake: Enable FSP multiphasezhaojohn
This patch changes the UPD EnableMultiPhaseSiliconInit to enable the Meteor Lake FSP multiphase flow. BUG=b:247670186 TEST=Able to build and boot Google, Rex with MultiPhaseSiInit Enable. [SPEW ] Executing Phase 1 of FspMultiPhaseSiInit [DEBUG] FSP MultiPhaseSiInit src/soc/intel/meteorlake/ fsp_params.c/platform_fsp_multi_phase_init_cb called [DEBUG] port C0 DISC req: usage 1 usb3 1 usb2 2 [DEBUG] Raw Buffer output 0 00000211 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded [DEBUG] port C1 DISC req: usage 1 usb3 3 usb2 4 [DEBUG] Raw Buffer output 0 00000431 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67741 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-17Revert "mb/google/herobrine: Remove NVMe from device tree"Shelley Chen
This reverts commit d164feb72602da958b644643b44e754f04a1f281. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69720 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17Revert "soc/qualcomm/sc7280: Remove NVMe init"Shelley Chen
This reverts commit 1b07797a7b79ea6c11421b61b9cf14b92cb91c66. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VDIan Feng
ALC5682-VS/ALC5682-VD use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682I-VS: _HID = "RTL5682" ALC5682-VD: _HID = "10EC5682" BUG=b:246491349 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing modeSridhar Siricilla
As per Intel doc #729124 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, #1 and #2 are already checked. Add a check for #3 as well. TEST=Build and boot MTL RVP Snippet from coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-17soc/intel/meteorlake: Update CSE firmware status registersSridhar Siricilla
The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs the firmware status details as per the new register definition. TEST=Build and boot the coreboot on Rex Snippet from coreboot log with the patch: [DEBUG] ME: CPU Debug Disabled : NO [DEBUG] ME: TXT Support : NO Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/meteorlake: Hide PMC and IOM devicesKapil Porwal
Hide these ACPI device so Windows does not warn about missing device drivers. Port of commit 907c85ad48dd ("soc/intel/alderlake: Hide PMC and IOM devices"). BUG=none TEST=Verified _STA method from ACPI tables in OS. USB-C drive is detected in OS. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic62172bee9120d260a3cd60770ef780cb7dce860 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69576 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00vjadeja-intel
Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:255481471 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/nissa/var/yaviks: Enable ISH driver and firmware nameWisley Chen
Enable ISH driver and set firmware name as "adl_ish_lite.bin" BUG=b:242291814 TEST=boot into kernel, and check dmesg "ISH firmware intel/adl_ish_lite.bin loaded" Change-Id: I4badabba1a0cfceb77fc91f21953496152f19615 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69606 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69275 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16util/testing: Move check of intel-sec-tool to separate targetMartin Roth
Testing for the presence of intel-sec-tools doesn't need to happen inside the what-jenkins-does target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6faa5bd5292ac5cceba9a64fe81939c0e25b9f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-16mb/google/brya/var/agah: Add Power Limits for RPL SKUTarun Tuli
Add power limits for the RPL SKUs of Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-16mb/google/brya/variants/volmar: Update ELAN touchscreen timingRen Kuo
ELAN updated the datasheet, the HID/I2C protocol's T3 delay time is 150ms now. Modify the volmar's delay time to follow the requiremnet. BUG=b:257073343 TEST=Build firmware and measure the T3 timing of resume and boot up on volmar DUT. Run Suspend/Resume with UI test and got pass. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-16mb/aopen/dxplplusu: Iterate CPUs for ACPI MADTKyösti Mälkki
Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-16cpu/x86/smm: Use common SMM_ASEG regionKyösti Mälkki
Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-16arch/x86: Disable clang build if using verstage_before_bootblockMartin Roth
Clang isn't working so well with the ARM code yet. This is still breaking builders after fixing the compiler warnings. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69701 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-16Documentation: Add some more acronyms to the listMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2022-11-16arch/arm/armv7: Don't set gcc specific options for clang buildsMartin Roth
Clang doesn't understand the -Wa,-mno-warn-deprecated option. Remove it for now. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9f91d6ec2db247e901ba9bc41bc4b888bbe43236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-16drivers/intel/fsp2_0: add log level parameter to fsp_print_guidFelix Held
Not all functions that call fsp_print_guid print their output with the BIOS_SPEW log level, so introduce a new log level parameter so that the caller of fsp_print_guid can specify which log level fsp_print_guid should use for printing the GUID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/amd/common: Don't set gcc specific options for clang buildsMartin Roth
Clang doesn't understand the -Wstack-usage=40960 option. Replace it with -Wframe-larger-than=40960. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16mb/google/skyrim/var/winterhold: Update DPTC setting for SMTEricKY Cheng
Follow Dynamic Thermal Table Switching proposal to initialize thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:232946420, b:258572474 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-16mb/google/skyrim: Create crystaldrift variantChao Gui
Create the crystaldrift variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_CRYSTALDRIFT Signed-off-by: Chao Gui <chaogui@google.com> Change-Id: Ibb3ebaa7e4af1a03173b93b8c4fbd342f7cd7100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/zork: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on zork, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in commit 22683fab (mb/google/skyrim: Use detect vs probed flag for touchscreens) Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69457 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/zork: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard tables set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors the change to skyrim in commit f90ff456 (mb/google/skyrim: Implement touchscreen power sequencing) Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SBSubrata Banik
This patch uses index 0x10 for IOE P2SB memory resource allocation instead of static 0. Additionally, switches to `mmio_resource` from `mmio_resource_kb`. TEST=Able to build and boot Google/Rex and observed log as below. Without the code change: [SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 0 With the code change: [SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-16mb/google/nissa/var/craask: Correct G2 touchscreen HIDTyler Wang
Correct G2 touchscreen HID to GT75CH02. BUG=b:235919755 Test=Dump the SSDT on craask and check the HID had been modified. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16configs: Buildtest 64bit amd/picassoArthur Heymans
Change-Id: Ia7b9925ab0a594a0ec26746cbe938f7cf2aa0118 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16soc/amd/picasso: Add support for 64bit buildsArthur Heymans
Tested on google/vilboz (running the PCI rom with yabel). Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-16mg/google/zork: Add functionality to set GPIOs in romstageMatt DeVillier
Add (empty) baseboard GPIO tables, getter functions, and call to gpio_configure_pads() in romstage, in preparation for adding touchscreen GPIO configuration/power sequencing. Change-Id: If0f626dbc7e601c2f49759e49a0baf027bf25f96 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69482 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/kahlee: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors similar changes made for skyrim, guybrush, and zork. TEST=tested with rest of patch train Change-Id: Id235815904dfc093549a1ed529e19974010977c7 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69547 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/kahlee: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on barla/liara, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: I142a6cdb6e8cef51fd925d34362a19a8736982a5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69548 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/kahlee: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_romstage_gpio_table() to baseboard_romstage_gpio_table() since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This mirrors similar changes made for skyrim, guybrush, and zork. Change-Id: I772bd2d74fd6778ffaa1e0809cc53f8d43b153f3 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69546 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/kahlee: Disable touchscreen GPIO export in CRSMatt DeVillier
Disable GPIO export in ACPI _CRS for touchscreens which set the register "have_power_resource." This eliminates the error: [ERROR] I2C: <bus:addr>: Exposing GPIOs in Power Resource and _CRS TEST=build/boot barla/liara, verify touchscreen functional, no error in cbmem log. Change-Id: Ifa8248755f346df37faf7a3182651bf190b0c33d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69549 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/brya/var/agah: Set GPP_H13 to reset on PLTRSTTarun Tuli
GPP_H13 should be reset when going to S5. Update it to do so on PLTRST BUG=b:240617195 TEST=Measured on Agah that PP3300_SD_X goes off in S5. Change-Id: I959f92f2c486e0ca5cb4269b271c163b4c4925d4 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69340 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/brya/var/gaelin: Configure DRIVER_TPM_I2C_BUSRaymond Chung
Add TPM I2C bus for gaelin in Kconfig. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and can boot to OS. Change-Id: Idaac11111a9ba7df0929267567e4730b2811f5f0 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68886 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2022-11-15mb/emulation/qemu-q35: Use ioapic helper functionsKyösti Mälkki
Change-Id: I1b7f4935b6901525b2f3b2a8405c5678aaee7515 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69525 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/emulation/qemu-q35: Cleanup includesKyösti Mälkki
Change-Id: Ib36d855e1dce8eb800bc077c1e444768c444fef8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69524 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/nissa: Add SD_BOOT fw_configReka Norman
Some nissa devices want to disable boot from SD card. Since nissa has a single shared depthcharge target, add a program-wide fw_config to allow disabling it. BUG=b:253003881 TEST=With depthcharge change, set SD_BOOT_DISABLE on nivviks and check SD card is not initialised in depthcharge. Change-Id: I1a3a533e4e74e48d9ce4a9678b812cb62ce2066b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69541 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/nissa: Remove SI_ME subregionsReka Norman
The SI_ME subregions were added to support using the CSE stitching tools (cse_serger). Use of the stitching tools has been reverted and probably won't be re-enabled soon, so the subregions are not currently used by anything. They also don't match the actual region sizes chosen by the FIT tool, so remove them to avoid confusion. The other option would be to manually keep them in sync with the sizes chosen by the FIT tool, but this would be extra manual effort without much benefit. BUG=None TEST=Build and boot on nivviks Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/geralt: Enable RTC for eventlog timestampsLiju-Clr Chen
Without RTC, the timestamps in the eventlog are currently all '2000-00-00 00:00:00'. Enable RTC to get the correct timestamps. localhost ~ # head /var/log/eventlog.txt 0 | 2022-10-15 22:59:38 | Log area cleared | 4088 1 | 2022-10-15 22:59:38 | Memory Cache Update | Normal | Success 2 | 2022-10-15 22:59:45 | System boot | 0 3 | 2022-10-15 22:59:46 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown localhost ~ # localhost ~ # date Sun Oct 16 01:42:59 PDT 2022 localhost ~ # BUG=b:233720142 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69432 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/brya/var/marasov: Add memory config for marasovFrank Chu
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69149 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-15mb/clevo/cml-u: Fix CMOS optionsAngel Pons
The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69521 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/amd/gardenia,pademelon: rewrite IRQ mapping handlingFelix Held
Gardenia and Pademelon had the same mainboard_picr_data and mainboard_intr_data data arrays. Compared to Kahlee there were 4 differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68852 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/google/kahlee/mainboard: rewrite IRQ mapping handlingFelix Held
Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD SoCs to allow making the largest part of the corresponding code common for all AMD SoCs in the coreboot tree. The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the data tables which is the PIT IRQ which looks very wrong to me, so it was changed to PIRQ_NC. Since the ASF and likely also the SDIO controller are unused, this shouldn't change runtime behavior. The data tables also had non 0 and non 0x1f entries in the following locations the internal BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37, 0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the description in the BKDG says that it controls the IRQ mapping of another internal PCI device, but that PCI device doesn't exist in the SoC. TEST=No obvious IRQ-related breakage on google/liara Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68851 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15soc/intel: Add Meteor Lake IGD device id 0x7d45Ravi Sarawadi
Add new IGD device. Reference: EDS Vol 1 (640228) Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-15mb/google/brya/var/marasov: use i2c1 for TPM for marasovFrank Chu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the marasov variant. BUG=b:254365935 TEST=FW_NAME=marasov emerge-brya coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I4d155fb35424d1ec12e825ca0aab233bd3cd607e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69376 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15drivers/wifi: Fix DSM parsing issueMeera Ravindranath
commit b6ebcdfde58a77bea03a67b376401b9f0f3edefb restructured the DSM implementation which resulted in a regression and DSM values gets filled with junk values. This CL fixes this issue and passes the right pointer to the dsm ids structure. BUG=b:256938177 TEST=Build, boot Nivviks and check if the DSM values are parsed correctly in the SSDT dump. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I88782b0b7dde1fca0230472a38628e82dfd9c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69427 Reviewed-by: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-15mb/google: Fix log messagesElyes Haouas
Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'. Change-Id: Id31c25f5b8686f951ab4f331682b82ff327d5e78 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15mb/google/nissa/var/craask: Remove RFIM settings for CraaskTyler Wang
Request by RF team, remove RFIM related settings to disable it. BUG=b:239657092 Test=RF team test on DUT and check it's disable Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I1eb4d93c2821cb067628dc1228c6c522d292c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15testing/Makefile.inc: Fix removing clang buildsArthur Heymans
The directory names were wrong. Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69568 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-14soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversionArthur Heymans
Explicitly cast integers to fix building for long mode. Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-14nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetreeArthur Heymans
Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-14drv/intel/fsp2_0/hand_off_block: rework fsp_find_extension_hob_by_guidFelix Held
Use the new fsp_hob_iterator_get_next_guid_extension function in fsp_find_extension_hob_by_guid instead of iterating through the HOB list in this function. TEST=AMD_FSP_DMI_HOB is still found and the same type 17 DMI info is printed on the console. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d4ce14c8a5494763de3f65ed049f98a768c40a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14drivers/intel/fsp2_0/hand_off_block: use iterator in fsp_find_range_hobFelix Held
Drop the find_resource_hob_by_guid implementation and use the new fsp_hob_iterator_init and fsp_hob_iterator_get_next_guid_resource functions in fsp_find_range_hob. TEST=Mandolin still finds the TSEG range HOB and uses the correct TSEG location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I00786cbeea203fba195ddc953c3242be544a7d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14soc/amd/*/root_complex: use FSP HOB iterator functionsFelix Held
Use the newly added functions to iterate over the FSP HOBs to report the resources used by FSP to the resource allocator instead of open coding the iteration over the HOBs in the SoC code. TEST=Patch doesn't change reported resources on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14drivers/intel/fsp2_0/hand_off_block: add functions to iterate over HOBsFelix Held
Introduce iterator function to go through the HOBs that will be used in follow-up commits both from the rest of the common FSP HOB access code and from SoC-specific code that needs to access specific HOBs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If86dde2a9f41d0ca7941493a92f11b91a77e2ae0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14cpu/cpu.h: Remove unused functions prototypesArthur Heymans
These were dropped with LEGACY_SMP_INIT. Change-Id: Iecaf9ba3d31d22311557b885b31e98a0edd74d96 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-14device/Kconfig: Don't allow native mode in x86_64Arthur Heymans
This option is not working so don't advertise it. Change-Id: I910162756a567289b2484a5445360a3197ae848c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14arch/x86/Kconfig: Move AMD stages arch to common codeArthur Heymans
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE needs to be build as x86 stage. Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14mb/google/nissa/var/pujjo: Modify touch screen hid to ELAN901CLeo Chou
Modify touch screen hid for Pujjo board. BUG=b:258586760 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-13arch/x86/mpspec.c: Drop weak write_smp_table()Kyösti Mälkki
Creating MP table is not useful when it does not include the interrupt routing entries. Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69489 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13drivers/generic/ioapic: Drop poor implementationKyösti Mälkki
This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13mb/gigabyte/ga-945gcm-s2c,skl: Drop HAVE_MP_TABLEKyösti Mälkki
The weak implementation of write_smp_table() is not useful without DRIVERS_GENERIC_IOAPIC and related entries in devicetree.cb. No interrupt routing entries are present in the generated MP table. Change-Id: I71a209e95ae1fe8c1c90b61c6ac0fb0e7bcc7eca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69490 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13mb/asus/p5gc-mx: Drop HAVE_MP_TABLEKyösti Mälkki
The weak implementation of write_smp_table() is not useful without DRIVERS_GENERIC_IOAPIC and related entries in devicetree.cb. No interrupt routing entries are present in the generated MP table. Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13acpi: Update default processor string from decimal to hexMarc Jones
Update the default processor sting from decimal to hex to increase the default number of Processor NamedObjects from 100 to 256 ie: CP00-CP99 is now CP00-CPFF This fixes MADT table generation for system up to 256 cores. Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: Id60a39d99fa77d1d89ad655ddecdebcc8a422f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13inc/dev: Add definitions for Link Capability and Slot CapabilityTim Chu
Add definitions for Link Capability and Slot Capability and these definitions may be used in smbios type 9. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Id66710d5569a7247d998cab20c2e41f2e67712cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13mb/google/zork: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13soc/amd/picasso: add mb_pre_fspm() definition and weak implementationMatt DeVillier
On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage for PCIe reset (currently set in bootblock) and touchscreen power sequencing (not yet implemented, but will be later in the patch train). Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69452 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13util/superiotool: Add SMSC MEC5035Nicholas Chin
Also comment out the SMSC FDC37M602 which has a conflicting ID and has never had the LDN/register layout anyway. Tested on a Dell Latitude E6400 Change-Id: I5b1900e6ef599c422a1d6eca7a2ac4691d56d874 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69481 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13util/superiotool: Add Nuvoton NCT6685D/NCT6686DNicholas Chin
There doesn't seem to be a datasheet available for the NCT6685D, but there is one for the NCT6686D. The 85D seems to return the same ID as the 86D, and the registers do seem to be returning valid data other than LDN 0xf which returns all 1s. The LDN and register layout appears to be identical to the NCT6687D-W. Tested on a Lenovo ThinkCentre M900 with a NCT6685D. Change-Id: I4de0e7b86422a14ab9ccb15b7571597611d755d5 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13util/xcompile: Fix building for clang + 64bitArthur Heymans
-malign-abi does not exist on clang (v15.0.0) and the -ccc-gcc-name variable is not needed anymore. TESTED: This also boots on qemu q35 Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-13mb/emulation/qemu: Move packed attributeMartin Roth
The jenkins build complains about this now that clang has been added. src/mainboard/emulation/qemu-q35/cpu.c:37:1: error: attribute '__packed__' is ignored, place it after "union" to apply attribute to type declaration [-Werror,-Wignored-attributes] __packed union save_state { Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id8faa24239505d808d09c00d825344edc7c4b7d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-12util/testing: Buildtest with clangArthur Heymans
Some platforms correctly build and boot with clang. Add this to our CI. Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12drivers/ipmi/ocp: Fix building with clangArthur Heymans
Fix the following warning: error: use of logical '&&' with constant operand [-Werror,-Wconstant-logical-operand] Change-Id: I9a2f03a0e05088a780ce1e829859421b461032ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69437 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12arch/x86/memmove: Add 64bit versionArthur Heymans
The 64bit handles 64bit input variables properly. TESTED: Both qemu and real hardware can use LZ4 properly which use this code. Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12soc/intel/elkhartlake: Enable 'scan_bus' on TSN GbEMario Scheithauer
For extern ethernet PHY access it is necessary to enable the 'scan_bus' functionality. Change-Id: I88050df2059ec7e0b27a132bca626eaef3d5dfb0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69385 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12security/tpm: improve tlcl_extend() signatureSergii Dmytruk
Until now tcg-2.0/tss.c was just assuming certain buffer size and hash algorithm. Change it to accept digest type, which the call sites know. Also drop `uint8_t *out_digest` parameter which was always `NULL` and was handled only by tcg-1.2 code. Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68745 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-11-12mb/google/brya/var/agah: Add RPL Support to AgahTarun Tuli
Enable RPL support for Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12amdfwtool: Add definition of instance for PSP entryZheng Bao
Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12mb/google/rex: Add Write Protect GPIO to cros_gpiosIvy Jian
This will enable crossystem to access WP GPIO BUG=b:258048687 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12mb/google/brya/variants/volmar: Disable the unused FP padsRen Kuo
Disable the unused fingerprinter(FP) gpio for zavala by fw_config FPMCU_MASK field. BUG=b:250807253 TEST=build firmware and veriify the FP function on volmar DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12mb/google/brya/var/marasov: Enable ISH driver and firmware nameSubrata Banik
BUG=b:234776154 TEST=Build and boot Marasov UFS, copy ISH firmware to host file system /lib/firmware/intel/adl_ish_lite.bin check "dmesg |grep ish", it should show: ish-loader: ISH firmware intel/adl_ish_lite.bin loaded Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12mb/google/brya/var/marasov: Select ISH driverSubrata Banik
This patch ensures that Marasov selects the ISH driver for devices with UFS enabled. BUG=b:256566011 TEST=Able to build Marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MITMacpaul Lin
This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8195 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66625 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali
This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12ec/google/chromeec: Simplify error handling for GET_VERSIONCaveh Jalali
We don't need to check the lower level error code to determine if an EC call succeeded. Simply check the return value of the call. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iaf0795b0c1a2df0d3f44e6098ad02b82e33c5710 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69372 Reviewed-by: Boris Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12ec/google/chromeec: Simplify get_uptime_info error handlingCaveh Jalali
google_chromeec_get_uptime_info() doesn't need to return an error code from the lower level calls for the caller to interpret. It is more appropriate to return a success/failure boolean. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I3e27b8b4eed9d23e6330eda863e43ca78bb174a3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69371 Reviewed-by: Boris Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12lib/ramtest.c: Update ram failure post codeMartin Roth
coreboot already has a ram failure post code defined, but the ram test functions weren't using it, and were using 0xea instead. This changes those failures to display 0xe3, the value defined in post_codes.h by POST_RAM_FAILURE. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 11:29:21 +0000