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2016-01-14arch/x86: add missing license headersMartin Roth
These were mostly written as part of the coreboot project, so get the standard coreboot license header. memmove.c came from the linux kernel, so also gets the standard coreboot v2 license header, but gets the added attribution that it was derived from the linux kernel. Unlike many coreboot files, this file may not be re-licensed as GPL V3. Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12916 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14soc/braswell: Add CPUID for D0 steppingDivya Sasidharan
Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14ec/: add missing license headersMartin Roth
thermal.asl was written as part of the coreboot project, so gets the standard coreboot license header. ec_commands.h came from the chrome ec tree, so gets the BSD license from that tree as mentioned in the header that has been replaced. Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14acpi/: add missing license headerMartin Roth
These were mostly written as part of the coreboot project, so get the standard coreboot license header. Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12917 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14arch/x86/include: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12912 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14soc/braswell: Fix P-state tableSubrata Banik
Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth
The read and write routines take a number of bytes to write, which should be 1,2, or 4. We now return an error if an invalid size is specified. Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12936 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14xcompile: More updates on ARM64 Erratum flagsMartin Roth
I tried to handle the checking for the config flag internal to xcompile, but the config flags don't appear to have been loaded into the environment by make at that point. This does update the if to check if the flag is even set before putting anything into .xcompile though. If the LDFLAG isn't set, there's no point in appending anything. Also removes the LP version of the erratum config flag, which was a copy/paste mistake from $(CONFIG_LP_COMPILER_GCC). Change-Id: I3d8b0328c85310393a120741a498bc18867a6f54 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14mb/lenovo/x200: Add panel power sequence valuesNico Huber
Values are taken from the vendor BIOS of my X200s. Notable effect: Stops display from flashing during native graphics init / Linux mode setting. Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14nb/intel/gm45: Backport configuration of panel power timingsNico Huber
Register settings are the same as on newer chips (compare sandy- bridge), just at different locations. Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14nb/intel/gm45: Drop unnecessary panel power handlingNico Huber
Skip everything but the final setting of PP_CONTROL, i.e. triggering the power up. The settings with PANEL_UNLOCK_REGS are useless as no lockable registers were touched in between. Also the loop waiting for the panel power up to finish was a no-op as the registers with the power timings were never filled (see follow-up commits). Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14cbfstool: Change FMAP granularity to 16 bytesStefan Reinauer
Instead of looking for an FMAP at every byte, only search down to a granularity of 16 bytes, reducing the time for a cbfstool call by 0.3s when no FMAP is found. Signed-off-by: Stefan Reinauner <reinauer@chromium.org> BUG=none BRANCH=none TEST=time ./cbfstool coreboot.rom add -f locale_de.bin -n locale_de.bin -t 0x50 -c lzma is 0.3s faster than before. Change-Id: Icb4937330e920ae09928ceda7c1af6a3c5130ac7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc92d838ba9db7733870ea6e8423fa4fa41bf8fe Original-Change-Id: Idbaec58a199df93bdc10e883c56675b419ab5b8e Original-Reviewed-on: https://chromium-review.googlesource.com/317321 Original-Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/12932 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14cbgfx: add error code to cbgfx_initDaisuke Nojiri
cbgfx_init can fail for multiple reasons. These codes help debugging cbgfx_init. BUG=chromium:502066 BRANCH=tot TEST=Tested on Glados Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315550 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14Makefile: Add 3rdparty to CPPFLAGS_commonJimmy Huang
In some occasions, Coreboot may need to include the header file from 3rdparty directory. By adding 3rdparty directory to Coreboot include path, we can include 3rdparty header file directly. BRANCH=none BUG=none TEST=build pass Change-Id: I8ed68bd330eae1211736a91b213c5dc0af2f7fa9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d6a86b3488ebbc9d8f5f46e922106b71034e7127 Original-Change-Id: Ib8e9f059f88a8c6767f872af8760e91186ae5ec3 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315021 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12929 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14cbfstool: fix address truncated problemHC Yen
In parse_elf_to_stage(), it uses 32-bit variable to handle address. The correct address type is Elf64_Addr. Use uint64_t to prevent address to be truncated. BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I1abcd16899a69b18dd10e9678e767b0564b2846e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ebc1aae0ae4ca30802a80a4a4e2ae0c0dad4d88a Original-Change-Id: I21f8057ddf13e442f1cf55da6702c3449ba0cc35 Original-Reviewed-on: https://chromium-review.googlesource.com/292553 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12927 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14mainboard/lenovo: reserve century byteAlexander Couzens
The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/11853 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14cbfstool: reorder help textPatrick Georgi
hashcbfs was spliced in a line early, mixing up 'extract' and 'cbfshash' help texts. Change-Id: I86d4edb9eec0685a290b2dd4c2dc45d3611eba9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12922 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-13arch/arm64: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13arch/arm: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I74438e8032c84f4190ef49f306969f7157234001 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13utils: Remove old license text from help & disclaimer fileMartin Roth
The license text that we decided to remove was removed from the headers of these files, but was still left in the help text. Remove it from those locations as well. Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in KconfigMartin Roth
Because these platforms haven't been getting build testing, they've missed out on some of the improvements that the other platforms have gotten. Enable MAINBOARD_HAS_LPC_TPM so that they will build. Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13intel/northbridge/sandy: raminit code cleanupPatrick Rudolph
Remove redundant call to dram_mrscommands(). Change-Id: I157915b4432093c556b538433e3337db1e9c525f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13[WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUMENico Huber
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12421 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13northbridge/intel/x4x: clean up includesMartin Roth
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h - Move TPMBASE and TPM32() definitions into iomap.h - Use "" style include for x4x.h in nortbridge files. - Move includes of .h files out of x4x.h and into the c files that need them. - Protect function definitions in bootblock. Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13cbfstool: Remove duplicate code lineWerner Zeh
Remove duplicate line which sets baseaddress parameter. Change-Id: Idfbb0297e413344be892fa1ecc676a64d20352bf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12904 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-12util/lint: Add lint script to run kconfig_lintMartin Roth
The lint target in the makefile relies there being a script using this particular naming format, so add a shell script front end to run the kconfig linter. Change-Id: I029c1cd3bbf3837c9f1d86c391ae5cabfa53685d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12903 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12util/lint/kconfig_lint: Run through perltidy to fix whitespaceMartin Roth
Change-Id: I7f04156fff0b65ea262b12961ce76ef329d358ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12902 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12lint: rename lint-006-checkpatch because board name is lint-006Martin Roth
Checkpatch should be 007. Change-Id: Ib71c50ad1a63a3a743391cd8fea9f79cd08ef6f3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12901 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12Makefile: Add toolchain version checkMartin Roth
This is an initial check for the coreboot toolchain versions. It currently checks binutils, gcc, clang, and iasl. The other components are slightly more difficult to test, but should follow on shortly. If the toolchain is not the correct version, make will halt with an error. Change-Id: I41daf6c4545c01dc21231d78fd081bbcf77c4726 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12846 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2016-01-12amd/cimx/sb800/pci_devs.h: Update guard #define nameMartin Roth
Change-Id: Ieae41cab97293831a0c49c3b472b9e6c62ba36c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12899 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-12google/guado: initial upstream migrationMatt DeVillier
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream, using google/auron and google/panther as refs. TEST=built and booted guado with full functionality Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12800 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-12Makefile: Correct spelling in help messageWerner Zeh
Correct wrong spelled "subnit" in help message. Change-Id: Iadbf483835ee4c1b6e3faa454d1cae2660b99c5e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-12nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` styleNico Huber
Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12883 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-11autoport: Add missing castsVladimir Serbinenko
Change-Id: I04abdd48f5e2440756f9b03041d46c773f200368 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-10fsp1_1: Remove #if protection in header - It's not neededMartin Roth
There's nothing in these files that needs to be hidden if GOP support is disabled. Removing this allows skylake to build when GOP support is turned off. Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12859 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-01-10lenovo/x220: Enable USB 3 controllerMarian Tietz
Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot@gmail.com> Reviewed-on: https://review.coreboot.org/12882 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-09buildgcc: Print out all missing tools then haltMartin Roth
Instead of printing out a single tool that needs to be installed each time buildgcc is run, print out the entire list of tools to be installed, then halt. Change-Id: I7761760eef3c45ba371f882a4f987408945bb3e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltageMartin Roth
I think this has a fairly low likelyhood of happening, but if AGESA can't determine the voltage of the memory, it assignes a value of 255 to the variable that it later uses to read from an 3-value array. There is an assert, but that doesn't halt AGESA, so it would use some random value. If the voltage can't be determined, fall back to 1.5v as the default value. Fixes coverity warning 1294803 - Out-of-bounds read Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08fsp_baytrail: Add additional PCI space above 4GBMartin Roth
This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-01-07intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07mainboard: Drop abuild.disabled files for Braswell boardsStefan Reinauer
Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07buildgcc: Don't request that optional tools be installedMartin Roth
Previously, when we tested for g++ and two different versions of clang, if the earlier versions were not found, buildgcc would still request that they be installed. This obviously isn't needed, and isn't the desired outcome. Now, if one of the first tests fails, nothing gets printed. If all the tests fail, it tells you to install either g++ or clang. Change-Id: I71359f59c4c6bee3c3c55e4e6105f11e6ca51527 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12852 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07src/vendorcode/amd: correct spelling of MTRRPaul Menzel
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07f14: Increase AP stack to 8k on 64bitStefan Reinauer
This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/11025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07google/cyan, intel/strago Kconfig: Only ask to display SPD onceMartin Roth
Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Quote variables to prevent globbing and splitting.Martin Roth
Quoting variables prevents word splitting and glob expansion, and prevents the script from breaking when input contains spaces, line feeds, glob characters and such. See shellcheck warning SC2086 Change-Id: Ib6ca46b64a621c4bea5c33ac312f2824b0386235 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12845 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Use local variables in the test functionsMartin Roth
Using the local variables instead of positional parameters helps readability. - Add and use the local variables in testcc. - Use the existing local variables in testld. Change-Id: Ice13288b830a7aa043b360eaee8e36f060589a18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12844 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: use $() instead of backticksMartin Roth
While the backtick syntax isn't actually deprecated, the $() syntax is preferred. Since both styles were being used in this script, settle on the new standard for all cases. Change-Id: I33770d666781b4fa34c909411e0d220c2540dbb4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Only include arm64 erratum check in arm64 sectionMartin Roth
Clean up the output file a bit by only including the erratum for arm64 into the that architecture section instead of every architecture. Change-Id: Ib6276f12aee5deb92a03e1c4fa2ad57db46bdc8f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12842 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Put compiler variables outside of 'if' to allow checkingMartin Roth
In order to be able to check the compiler versions, we need to be able to access the compiler variables. Move the original assignments outside of the GCC check, and assign either the GCC or CLANG compiler to the actual CC_ environment variable later. This ends up with the same value set, while allowing the compiler versions to be checked. Change-Id: Iffad02d526420ebbdfb15ed45eb51187caaa94fb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Separate flags from clang executableMartin Roth
We already have a CFLAGS variable - Use it for all of the flags. Change-Id: I22b4c5cf24b8743e85ffab29ddcccdc6c732ea3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12840 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Add XGCCPATH to clang compilerMartin Roth
The XGCCPATH prefix is on all the other tools and compilers, so add it to clang as well, so it can be found correctly. Change-Id: Ibc250a81433f37bbb0555d32605aebe3a68aaf40 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12839 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Add separation for architectures to improve readabilityMartin Roth
- Add bar at the top of each architecture - Make the architecture name and the TARCH_SEARCH to two lines - Add a second line at the bottom of each architecture - Add a comment about the two blank lines so they don't get accidentally removed. Change-Id: Ib4326bd94fe39b979244816ce54b752d083f6b16 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12838 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07xcompile: Use tabs for indentationMartin Roth
Change-Id: I96a5048050f8016c3c569f20318b4d421a4470a7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12837 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07Makefile.inc: update location of dsdtMartin Roth
The dsdt file moved from the mainboard directory to the top level of the build directory. Remove it from the new location when cleaning. Change-Id: If9f72c78e5c03e0db384b3181c169aa2ecbb5c18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-07intel/fsp1_1: Disable GOP support by defaultMartin Roth
Since the GOP drivers aren't published in the 3rdparty blobs repo yet, disable the GOP support for now so that abuild can build these platforms. Change-Id: Ic98671c163b433ebde89c8bf240ef4b2be393586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12829 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07mainboard/asus/kgpe-d16: Enable romstage microcode spinlocksTimothy Pearson
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failureTimothy Pearson
When microcode updates are enabled, this fixes an issue identical to that described in GIT hash 7b22d84d: * drivers/pc80: Add optional spinlock for nvram CBFS access Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12063 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07inteltool: add NetBSD compatibilityAndrey Korolyov
Tested on NetBSD-7.0/i386 Change-Id: I6a693633d3a80ea07ade233b1b4fd1c5a1412032 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12835 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07viatool: add NetBSD supportAndrey Korolyov
Change-Id: I033044e4b781475d6d60a49a61313a720103ce38 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12836 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07Revert "util/crossgcc: Regenerate MPFR autotools files before build"Timothy Pearson
This reverts commit 68d0e4a5a1e7028227f6fbe086c891955cb7854e. Special handling of MPFR is no longer needed with the latest MPFR release. Change-Id: I96d9ea92cfb74eed6af2ba62254f0678081e2b4f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12833 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07util/crossgcc: Bump MPFR version to 3.1.3Timothy Pearson
The current MPFR version contains a stale config.guess file that requires special handling on ppc64el systems. Bump the MPFR version to the latest release. Change-Id: I5e86c732c09f8a6a43f9812452124d64d337ea3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12832 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06viatool: Add VIA C3 MSRsAndrey Korolyov
Tested on C3/EPIA board and Linux x86 Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06cpu/amd/fam10h-15h: Add tsc_freq_mhz() functionTimothy Pearson
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-06cbfstool: correct add-master-header logic to match runtime expectationsAaron Durbin
The cbfs master header's offset and romsize fields are absolute values within the boot media proper. Therefore, when adding a master header provide the offset of the CBFS region one is operating on as well as the absolute end offset (romsize) to match expectations. Built with and without CBFS_SIZE != ROM_SIZE on x86 and ARM device. Manually inspected the master headers within the images to confirm proper caclulations. Change-Id: Id0623fd713ee7a481ce3326f4770c81beda20f64 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12825 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-06Revert "x86: Align CBFS on top of ROM"Aaron Durbin
This reverts commit 65e33c08a9a88c52baaadaf515b9591856115a77. This was the wrong logic to fix the master header. Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12824 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06Documentation: Add information about patches from other git reposMartin Roth
This is more tribal knowledge that I don't think I've seen written down anywhere else. It's not a huge issue, but when looking through the git log, it helps to be able to differentiate the information from the old gerrit with the information from the new one. Change-Id: I7993bda1e9aab79dc26940aaba9ddc52382ed0df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12804 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06cbfstool: Add 'hashcbfs' command to compute hash of CBFS region.Aaron Durbin
For the purposes of maintaining integrity of a CBFS allow one to hash a CBFS over a given region. The hash consists of all file metadata and non-empty file data. The resulting digest is saved to the requested destination region. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Integrated with glados chrome os build. vboot verification works using the same code to generate the hash in the tooling as well as at runtime on the board in question. Change-Id: Ib0d6bf668ffd6618f5f73e1217bdef404074dbfc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12790 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06cbfstool: keep cbfs master header pointerPatrick Georgi
Adding new files overwrote the header with the empty file (ie 0xff), so carve out some space. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I91c292df381c2bac41c6cb9dda74dae99defd81d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12789 Tested-by: build bot (Jenkins)
2016-01-06cbfstool: Adapt "cbfstool copy" to only use fmap regions.Patrick Georgi
These need to go together, so the commit became a bit larger than typial. - Add an option -R for the copy source fmap region. Use: cbfstool copy -r target-region -R source-region. - Don't generate a CBFS master header because for fmap regions, we assume that the region starts with a file header. Use cbfstool add-master-header to add it afterwards, if necessary. - Don't copy files of type "cbfs master header" (which are what cbfstool add-master-header creates) - Leave room for the master header pointer - Remove -D command line option as it's no longer used. BUG=chromium:445938 BRANCH=none TEST=Manual test on image and integration test w/ bundle_firmware changes. CQ-DEPEND=CL:313770,CL:313771 Change-Id: I2a11cda42caee96aa763f162b5f3bc11bb7992f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12788 Tested-by: build bot (Jenkins)
2016-01-06cbfstool: Use buffer over offset/size pair for cbfs_copy_instancePatrick Georgi
This allows adding support for FMAP based cbfstool copy more easily. BUG=chromium:445938 Change-Id: I72e7bc4da7d27853e324400f76f86136e3d8726e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12787 Tested-by: build bot (Jenkins)
2016-01-06commonlib: Add function to hash contents of a CBFS region.Aaron Durbin
Provide a common routine to hash the contents of a cbfs region. The cbfs region is hashed in the following order: 1. potential cbfs header at offset 0 2. potential cbfs header retlative offset at cbfs size - 4 3. For each file the metadata of the file. 4. For each non-empty file the data of the file. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized in chromeos cros_bundle_firmware as well as at runtime during vboot verification on glados. Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12786 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-01-06commonlib/cbfs: Add type ids for empty filesPatrick Georgi
We will soon need to handle empty files. Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12785 Tested-by: build bot (Jenkins)
2016-01-06commonlib: Prepare code to be included in cbfstool builds.Aaron Durbin
Some of the files need to be adjusted so that they can be used both in cbfstool as well as coreboot proper. For coreboot, add a <sys/types.h> file such that proper types can be included from both the tools and coreboot. The other chanes are to accomodate stricter checking in cbfstool. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Built on glados including tools. Booted. Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add common cbfs parsing logic to coreboot and cbfstool.Aaron Durbin
To continue sharing more code between the tools and coreboot proper provide cbfs parsing logic in commonlib. A cbfs_for_each_file() function was added to allow one to act on each file found within a cbfs. cbfs_locate() was updated to use that logic. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add function to compute relative offsets from two region_devices.Aaron Durbin
Provide a helper function which returns the relative offset between 2 region_devices that have a parent-child child relationship. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06toolchain.inc: Test for valid toolchain when ANY_TOOLCHAIN is usedMartin Roth
Even when ANY_TOOLCHAIN is selected, a valid compiler for the requested architecture is needed. Change-Id: If1a0a1ca6b726e8e58d29c69de93546510582548 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-05xcompile: Remove warnings about missing tools & architecturesMartin Roth
Let toolchain.inc error out when the architecture or tool is missing. Change-Id: I39a51e5a2c778d6bbc50354807e5e2b717fa9e52 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12682 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-04util/crossgcc: Add ppc64el supportTimothy Pearson
Change-Id: I619f7c3cef7f0aaa6fccb3d52f2ac1f6ace6d0d6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12818 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04util/crossgcc: Regenerate MPFR autotools files before buildTimothy Pearson
The config.guess file included with MPFR is completely obsolete, leading to build failures on ppc64el due to the system architecture not being detected. Regenerate the files from the host system via automake before attempting to build MPFR. Change-Id: I00fc16003906e373d112c25978197ac907adccfd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04util/crossgcc: Bump GMP version to 6.1.0Timothy Pearson
The previous official GMP release (6.0.0) contains a bug that prevents compilation on ppc64el systems. Increase version to the latest version (6.1.0). Bug details: gcc build on ppc64el fails with: (.text+0x4c): undefined reference to `BMOD_1_TO_MOD_1_THRESHOLD' While I don't have an exact commit hash due to Hg use upstream, a missing BMOD_1_TO_MOD_1_THRESHOLD define on ppc64el was quietly fixed in Hg before the 6.1.0 release. Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12811 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04sb/amd/sr5650: Correctly locate CPU MMCONFIG resourceTimothy Pearson
The code committed in GIT hash * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support did not correctly locate the CPU MMCONFIG resource, leading to failures with operating systems and firmware (e.g. SeaBIOS) when the PCI extended configuration space option was activated. Due to the southbridge routing not being set up, MMCONFIG accesses were targetting DRAM and therefore the PCI devices were not being configured. The failure normally manifests as a system hang immediately after PCI configuration starts. Search for the CPU MMCONFIG resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12821 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04toolchain.inc: Update help text, Add TODO.Martin Roth
- Update the help text to be more informative. - Add todo about IASL - we shouldn't require it if the build doesn't use it. Change-Id: Iffeb94f78c1ae7535a8a7b9b0b9f1728301a42b3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-04toolchain.inc: Skip how to use any toolchain if it's selectedMartin Roth
If ANY_TOOLCHAIN is selected, don't bother telling the user how to do what they've already done. Change-Id: I7182d18a91e832aa56638ec64fe8b3b0c38cff7a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04toolchain.inc: Move nocompile around entire check, Comment endifsMartin Roth
Move the check for NOCOMPILE flag around the whole block. There's no need to test COMPILERFAIL if NOCOMPILE is set. Comment the endif lines to make it easier to understand. Signed-off-by: Martin Roth <martinroth@google.com> Change-Id: Id7bb5ca13e6bf1cabf4b7b2ff3256b47b966bac1 Reviewed-on: https://review.coreboot.org/12678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-04toolchain.inc: Test for toolchain when using llvm/clangMartin Roth
Change-Id: I45ed5e289f9bfae90d71938243f921588b256e39 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04genbuild_h.sh: allow coreboot to be a git submoduleBen Gardner
When coreboot is pulled in as a submodule, the .git "folder" is a file, not a folder. Use the '-e' test instead of '-d' to allow for that. Change-Id: I0dd8866b0016f7ba099cdaf4d7db442ff22612b5 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12819 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04Revert "AMD OemS3Save: refactor for Merlin Falcon"Kyösti Mälkki
This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93. Do not mix open-source AGESA and binary PI trees. Once you have working S3 support for binaryPI platforms, add the adapted oem_s3.c file as northbridge/amd/pi/oem_s3.c instead. Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/12282 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-03sb/intel/bd82x6x: Add missing PCIIDs for variants .Vladimir Serbinenko
Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12820 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-12-31nb/intel/gm45: Export low-power and (SFF) optionsNico Huber
Make the low-power and small form factor (SFF) options overridable from romstage main. Also disable both options by default. That's ok as there aren't yet any in-tree users of the GS45 chipset. As a nice side-effect, this adds X200s support to the lenovo/x200 port. Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12814 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-31lenovo/x200: Revise onboard IRQ routingNico Huber
All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I687262556d918311757fda9afda9ebfdd7edf947 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12813 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-31superio/it8772f: Add register to set the default value of FAN speedTed Kuo
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef Original-Reviewed-on: https://chromium-review.googlesource.com/262832 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12799 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31superio/it8772f: Add switch to enable HWM (Hardware Monitor)Ted Kuo
Set up External Temperature to read via thermal diode/resistor into TMPINx register by setting thermal_mode switch. Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034 Original-Reviewed-on: https://chromium-review.googlesource.com/260545 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a) Original-Reviewed-on: https://chromium-review.googlesource.com/262340 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12798 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: memlayout: update GRAM sizeIonela Voinescu
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: I2C: fix base address for I2C clock setupIonela Voinescu
The base address for the I2C dividers (DIV1 and CLOCKOUT) was erroneously set to the toplevel clock controller base address and not to the correct peripherals clock controller base address. Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 02:58:44 +0000