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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The variables defined in this defconfig are incorrectly named, therefore
fix them.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9299be96f8c44d6a87d380f4f942c4d26af7050d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Since the PSE GBE0 MAC has been disabled on this board in
commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb:
Remove TSN GbE 0"), therefore disable the corresponding
GPIOs as well.
BUG=none
TEST=Test link detection and IP assignment on the remaining
ports (PSE GBE1 and PCH GBE0) of mc_ehl3.
Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8df1d93a8b0a0d562c7ae5a9f1a70f2eb26499c9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71976
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Building LinuxBoot with u-root newers releases can
providing a better experience,
Change-Id: Ie98f434c5296b7ba7c3750a766b244c747421baa
Signed-off-by: eliassouza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72465
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds initial romstage code and spd data for LP5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 LPDDR5
Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B
Board ID -
0b0000 - Empty spd hex file
0b0001 - DDR5 (Empty spd hex file)
0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B)
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: I15b352eb246aed23da273e56490c7094eae9d176
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Marasov variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:264838335
TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS
during boot path.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Intel SPR-SP processor has socket type as
PROCESSOR_UPGRADE_SOCKET_LGA4677 which is different
from the socket type of CPX-SP and SKX-SP.
Change-Id: Id2279cc0c1fa3f007d7c081af6f78e5aa98d2f3d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71947
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel SPR-SP (Sapphire Rapids Scalable Processor) chipset
belongs to Xeon-SP family. It was product launched on
Jan. 10, 2023.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifece05e2fbcc454cdee8e849cb4f146c89f54333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Now that we support >1 Xeon-SP, XEON_SP_COMMON_BASE no longer
reflects the socket type. This uses SOC_INTEL_* Kconfig variables and
returns the correct socket type for Cooper Lake-SP.
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I142de5f040f3b76e352f27c00fe9e50787df5712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Intel Sapphire Rapids Scalable Processor was product launched
on Jan. 10, 2023.
Add the FSP/HOB header files corresponding to 2022 ww43 git tag
EGLSTRM.0.RPB.0090.D.03.
Change-Id: I818da37c10f40045d98a9f73e82034c3fe6459e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71948
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training
data after FSP-S instead of FSP-M. For now only SPR-SP server
FSP supports this.
This issue surfaces with SPR-SP, because of the memory type
(DDR5 support) and memory capacity (more memory controllers, bigger
DRAM capacity). Therefore Intel decided to save MRC training data after
FSP-S with SPR-SP FSP.
Change-Id: I3bab0c5004e717e842b484c89187e8c0b9c2b3eb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71950
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PMC registers are quite different between LBG and EBG. Move pmc.h
to lbg directory to differentiate.
Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I43590f0f792fca1c90ee8f8b32e6be47943c59df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72453
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This functionality is used in multiple places, so factor it out into a
function. Compared to acpigen_write_processor_cnot, the buffer size is
decreased from 40 to 16 bytes, but the format string specified by
CONFIG_ACPI_CPU_STRING results in 9 chars and a NULL byte which will fit
into the buffer without any issue. I've seen the CPU devices being put
into another scope within \_SB, but even in that case that would be 14
chars and a NULL byte whist still fits into the 16 byte buffer. For
acpigen_write_processor and acpigen_write_processor_package this doesn't
change any edge case behavior. In the unrealistic case of the format
string resulting in a longer CPU device string, this would have been a
problem before this patch too.
Also drop the curly braces of the for loop in
acpigen_write_processor_package. This makes the code a bit harder to
read and isn't a very good idea, but with the curly braces in place, the
linter breaks the build :(
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d8291a2aaae2011cb185d72c7f7864b6e2220ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72452
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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ACPI_CPU_STRING specifies the format string for the scope of the
processor devices in the generated ACPI code. Also point out that the
resulting string will be truncated to at most 15 chars to fit into the
16 byte buffer used in two functions in acpigen.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fb1db8adeecd783c835a500d28a13b823cda155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72451
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Not all Chrome-EC devices have a keyboard or use Vivaldi for key
remapping, so demote the printk output when the EC doesn't support
it from ERROR to INFO. Adjust the printk text for clarity.
Change-Id: I14059f4e3e56ff891f302601d5acc1bb842cffc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72474
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Renaming origin/master to just master fix error during cloning repo.
Error: Remote branch origin/master not found in upstream origin
Change-Id: Ib5d4bb0277076842f8a8400eb61da9ad23465b66
Signed-off-by: eliassouza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The comment in the header amdfwtool.c was written long time ago and is
needed to get updated.
Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The current CMOS option causes Linux to not boot, as the GRUB EFI
loader will report an incorrect parameter.
Update the CMOS option so that the corresponding UPD is changed when
the wireless is set to disable, so that the root port for the wireless
is also disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I607d700319d6a58618ec95b3440e695c82dff196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the Type-C USB 2.0 interface to a standard port, as the
Type-C macro will not work in Linux (dmesg says the cable is
faulty),
This makes the port work reliably in Linux, tested with:
* Manjaro 21
* Ubuntu 22.04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add functions that allow checking and changing PTT state at runtime.
Can be useful for platforms that want to use dTPM instead and have no
means to stitch ME firmware binary with disabled PTT.
The changing function also checks for the current feature states via
HECI to ensure that the feature state will not be changed if not
needed.
TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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BUG=b:239110778
TEST=Make sure that the output of elogtool is unaffected by this change.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia1a6341abd834dd9ad5f12c9f2eefb0489364a08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72099
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Return generic coreboot error codes from the mb_adjust_cfg
callback used in mainboards instead of '-1' constant and
a driver-specific success-indicating define.
BUG=none
TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3
build correctly.
Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The D-state list lists the devices with the corresponding
D-state that the devices should be in, in order to enter LPM
DPTF is not mentioned in Intel's document 595644 as one of
the devices.
This CL removes it to avoid an error seen after it was added
to that table:
"ACPI Error: AE_NOT_FOUND, While resolving a named reference
package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)"
TEST=Built and tested on anahera and saw the error is gone
BUG=b:231582182
Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Depending on the actual issue and the experience of the contributor,
"Easy projects" might not be an appropriate description for Coverity
issues and similar things.
Thus rename this section to "Small projects" and also update references
to it.
Change-Id: I3bdefd9f37440ab3ae493095b7fb5c76394d2ba1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72447
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I169fa5a89d65d3a71e9cc84638216c7baa3815f1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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add functions for concatenate OP
add debug message containing concatenated string with string, value, or
OPs
Ex1: to print string with another string provided from C side:
acpigen_write_debug_concatenate_string_string("Wait loop Timeout! var=",
name, LOCAL6_OP);
will generate:
Concatenate ("Wait loop Timeout! var=", "L23E", Local6)
Debug = Local6
Ex2: to print string with a value:
acpigen_write_debug_concatenate_string_int("ModPHY enabling for RP:",
pcie_rp, LOCAL0_OP);
will generate:
Concatenate ("ModPHY enabling for RP:", 0x05, Local0)
Debug = Local0
Ex3: to print string with an ACPI OP:
acpigen_write_debug_concatenate_string_op("while Loop count: ",
LOCAL7_OP, LOCAL6_OP)
will generate:
Concatenate ("while Loop count: ", Local7, Local6)
Debug = Local6
TEST=Add above functions in the acpigen code and check the generated
SSDT table after OS boot
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I370745efe3d6b513ec2c5376248362a3eb4b3d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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This CL adds claimed memory regions that were missing for the
resource allocator. See commit ca741055e6b6 ("soc/intel/adl: Add
missing claimed memory regions") for details.
TEST=Booted rex and saw the previously missing ranges getting added
from AP Log (with this CL):
SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000
SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000
SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000
SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000
SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000
SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000
SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000
SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000
SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000
SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000
SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000
SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000
dmesg:
BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved
BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable
BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
BIOS-e820: [mem 0x0000000000100000-0x00000000759c9fff] usable
BIOS-e820: [mem 0x00000000759ca000-0x000000007fffffff] reserved
BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved
BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved
BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved
BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved
BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved
BIOS-e820: [mem 0x00000000fed20000-0x00000000fed83fff] reserved
BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved
BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved
BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable
BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved
Change-Id: I749e7b6e969f8d6314fcd2906acd7de69d4d9f9c
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl5 and observe that POST codes are
displayed before DRAM training.
Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2628d7b25d3fb7467772cb859cb7c8c7865e323c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72480
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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- Update the notes for the 4.19 release.
- Add the intel/icelake_rvp board as being supported on the 4.19 branch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5c283f64efc465d8f70fc19d570c5b7547474e80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72481
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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The Alder Lake PEIM graphics driver executed as part of the FSP does
not wait for the panel power cycle to complete before it initializes
communication with the display. It can result in AUX channel
communication time out and PEIM graphics driver failing to bring up
graphics.
If we have performed some graphics operation in romstage, it is
possible that a panel power cycle is still in progress. To prevent any
issue with the PEIM graphics driver it is preferable to ensure that
panel power cycle is complete.
This patch replaces commit ba2cef5b5493
("soc/intel/common/block/early_graphics: Introduce a 200 ms delay")
workaround patch.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible in the recovery flow
Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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We were using the libgfxinit `Initialize' function with the
`Clean_State' parameter because the more appropriate `Update_Output'
function was not performing all the necessary clean up operations for
the PEIM driver to be successful when libgfxinit was used in romstage.
Thanks to a lot of experiments and some log analysis efforts, we were
able to identify the missing operation and fix the `Update_Output'
function (cf. https://review.coreboot.org/c/libgfxinit/+/72123).
The `initialized' global variable is now unnecessary as we track the
initialization in the Ada code instead.
Since the `Update_Output' function does not return any value, this
patch modifies the `gma_gfxstop' prototype accordingly. This does not
have any impact as the return value was not used anyway.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible
Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch restricts the dump of the vebose graphics output settings
to configuration with the `DEBUG_ADA_CODE' flag set.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Configuration dump is seen only if DEBUG_ADA_CODE is set
Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72418
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add info on where to contribute to Dasharo.
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I1b7e7aa05a0cabc990bddfaf957873402ebe183f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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CLKREQ Pins are intentionally not configured, because there seems to be
a current Issue with FSP, that causes pci devices to not work if CLKREQ
Pins are configured by coreboot. The msi/ms7d25 mainboard seems to have
a similar issue and the cause is also documented in it's gpio.c file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba35076af194de0e85de60ebc93d62fda24e9c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Add the remaining DDR2 code to program the registers for memory
timings, ODT, RCOMP, and refresh mode; and perform receive-enable
calibration.
TEST: DDR2 systems boot
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I6d9a1853fea9e29171d7c2f9ffe7086685c9efad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move DDR3 memory I/O init to its own function and add DDR2 memory I/O
init. Read I/O init is common to both DDR2 and DDR3.
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: Ic4d5130f527249d3a5b98bae778cdf21a1753b04
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Split JEDEC init into common and DDR3 specific parts and add the DDR2
specific init code. This also replaces raw `mchbar_clrsetbits32` calls
with a dedicated `jedec_command` function.
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I7a57549887c0323e5babbf18f691183412a99ba9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial support for DDR2. This also changes GM45 raminit to
internally work in units of 1/256 ns for both DDR2 and DDR3 instead of
the 1/8 ns MTB assumed for DDR3, which simplifies the handling of time
values. DDR3 time values are thus scaled by a factor of 32 accordingly.
TODO:
- DDR2 JEDEC init
- Memory IO init
- Register programming
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I265938d58c30264fd5d4f7b89da7b689058b8cf8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5f91ae1b5904405edd797b57fbeb46609301295c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72434
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop the `hyper_threading` CMOS option from most boards, as it's most
likely not working properly and causing problems. The main reasons to
remove the option are:
* The used enum is backwards (0 ---> Enable, 1 ---> Disable)
* Platform/SoC code does not honor the `hyper_threading` option
Also, remove the now-unused enum used by the `hyper_threading` option.
Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Enable pin 0x18 which is used for the 3.5mm combo jack microphone
detection.
Also, disable 0x17 as it is not used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I05856627c073acaff49ea1ddc048a49a74b6268f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71718
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6a5c54ac46840fc1e03eb15b9ae2ddc34172ec08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72011
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Getting an error from the Kernel on Rex devices:
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI (20210730/dspkginit-438)
FSPI is defined in src/soc/intel/meteorlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
See commit feed8e4bd9dc ("soc/intel/adl/acpi: add FSPI to DSDT") for
the corresponding ADL CL.
TEST=Built and tested on brya by verifying the error is gone.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id8d2a1b5e074f036345e028b117d420bf36a9042
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This function reads out the current value set to output for a GPIO pin.
Ex: GPP_E0 is set to output
int e0_val;
e0_val = gpio_tx_get(GPP_E0);
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
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Fix the comment as "checkpatch" says.
Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Current size of the cbmem premem buffer (8KB) is sometimes insufficient
to contain the complete debug log causing the cbmem console buffer to
indicate overflow.
This patch increases the premem cbmem buffer size to 16KB so that
the complete debug log can be stored in it.
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before, the Intel HDA PCIe device was showing up in the lspci tool, but
Audio wasn't working.
This patch enables the corresponding FSP-M settings to make it work.
Tested on Prodrive Atlas with Themis carrier board on Windows 10 and
Linux 6.1.0-rc3.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I144618c453c1e6a3e759afc7532a4ac4a71814c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Customer needs SaGv to be disabled by default.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8454c267dcc12d2ef7de7bd23296a17294f058a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Currently ASPM cannot be disabled by individual mainboards, if the
soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like
PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by
individual mainboards if needed. This change makes PCIEXP_ASPM one of
these configurable options.
Test: build prodrive/atlas and see that build/config.h lists the
option CONFIG_PCIEXP_ASPM as disabled.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to the
device and since the bridge doesn't have enough MMIO space reserved, the
Linux kernel can't assign resources to it. To fix this problem, enable
the mp2 device in the mainboard's devicetree so that it gets its
resources assigned by coreboot. An equivalent change was verified on
Chausie.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to the
device and since the bridge doesn't have enough MMIO space reserved, the
Linux kernel can't assign resources to it. To fix this problem, enable
the mp2 device in the mainboard's devicetree so that it gets its
resources assigned by coreboot.
TEST=Fixes the resource allocation for the mp2 PCI device.
dmesg output before the patch:
[ 0.210616] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000
[ 0.210631] pci 0000:04:00.7: reg 0x18: [mem 0x00000000-0x000fffff]
[ 0.210641] pci 0000:04:00.7: reg 0x24: [mem 0x00000000-0x00001fff]
[ 0.210649] pci 0000:04:00.7: enabling Extended Tags
[ 0.240570] pci 0000:04:00.7: BAR 2: no space for [mem size 0x00100000]
[ 0.240572] pci 0000:04:00.7: BAR 2: failed to assign [mem size 0x00100000]
[ 0.240574] pci 0000:04:00.7: BAR 5: assigned [mem 0xd05c6000-0xd05c7fff]
dmesg output after the patch:
[ 0.210483] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000
[ 0.210501] pci 0000:04:00.7: reg 0x18: [mem 0xd0500000-0xd05fffff]
[ 0.210515] pci 0000:04:00.7: reg 0x24: [mem 0xd06c6000-0xd06c7fff]
[ 0.210524] pci 0000:04:00.7: enabling Extended Tags
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I680ef9798f2f0e7e0646f0fd30bef58398b7bf19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72197
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer.
Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled.
TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message.
Change-Id: I0273fb14916f213b686270a9dec4c1b47612af4d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71289
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Current size of the cbmem buffer (128KB) is insufficient to contain the
complete debug log causing the cbmem console buffer to wrap.
This patch increases cbmem buffer size to 256KB so that the complete
debug log can be stored in it.
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Change-Id: I2099386dd87a010c3a5937bd896620270f587b1c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71288
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched
on Jan. 10, 2023. The chipset includes Emmitsburg PCH.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.
Its datasheet is Intel doc# 606161.
Add Intel Emmitsburg PCH GPIO pin definitions.
Also common code change is made to support Intel Emmitsburg PCH:
a. Instead of 2 PAD registers per GPIO, it has 4 PAD registers.
b. The register address space may not be contiguous from one GPIO
group to the next GPIO group.
Change-Id: Ia0d9179544020b6abb0be1ecd275a9a46356db8a
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch implements a new API to make the UFS controller function
disabled. Additionally, perform a warm reset post disabling the UFS
controller to let PMC know about the state of the UFS controller
and disable the MPHY clock.
BUG=b:264838335
TEST=Able to build and boot Google/Marasov successfully.
From the AP log, I am able to confirm that UFS is function disabled
using PSF.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I940a634f70f8c97ef1234866d4c5a1ff224c6e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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This patch makes it easy for OEMs to keep a unified AP firmware image
to boot different SKUs with UFS and non-UFS as boot media.
With a unified image while booting on non-UFS SKU is exhibiting S0ix
failure due to UFS remain enabled in the strap although FSP-S is
making the UFS controller function disabled.
The potential root cause of this behaviour is although the UFS
controller is function disabled but MPHY clock is still in active
state.
A possible solution to this problem is to issue a warm reboot (if
boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC
read the function disable state of the UFS for disabling the MPHY
clock.
Mainboard users with such board design where OEM would like to use
an unified AP firmware to support both UFS and non-UFS sku booting
might need to choose this config to allow disabling UFS while booting
on the non-UFS SKU.
Note: selection of this config would introduce an additional warm
reset in cold-reset scenarios due to function disabling of the UFS
controller.
BUG=b:264838335
TEST=Able to build and boot Google/Marasov successfully.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a811d8f4aad41dab6f8988329eaa1d590a4637a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch calls into `pmc_clear_pmcon_pwr_failure_sts()` to clear
GEN_PMCON_x register status bits after determining the
`prev_sleep_state`.
Having those bits being set across reboot might be misleading.
For example: although the last boot was not due to power failure but
the power failure bit still remains the same (unless cleared).
Note: clearing `GBL_RST_STS` bit earlier than FSP-M/MRC having an
adverse effect on the PMC sleep type register which results in
calculating wrong `prev_sleep_state` post a global reset, hence,
just clearing the power failure status bits rather than clearing
the complete PMC PMCON_A register.
BUG=b:265939425
TEST=Able to clear the GEN_PMCON_A register power failure bits aka
BIT16 and BIT14 on google/marasov platform over next boot to avoid
having its persistent effect.
Without this patch:
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
...
GEN_PMCON: d0215238 00002200
With this patch:
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
...
GEN_PMCON: d1001038 00002200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4f5dfe0251aeb85b667fbfc44fbf17b025aec090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Update header files for FSP for Meteor Lake platform to
version 2473_86, previous version being 2431_80.
FSPM:
1. Removed deprecated UPD PcieMultipleSegmentEnabled
2. Address offset changes
FSPS:
1. Removed deprecated UPD ForcMebxSyncUp
2. Address offset changes
BUG=b:261150757
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.corp-partner.google.com>
Change-Id: Ie396ad7ef4da2d1c52d37477bbb0815d2d650841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
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This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This patch converts below chip configs from camel case to snake
case to match with the other chip configs belongs to the chip
structure.
- SaGv
- RMT
Additionally, updated the `sagv` help text and operation as
applicable based on the FSPMUPD.h file (belongs to the vendorcode).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I62e521cf3f46e888e2c995d83ac7dc666de1af82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This patch implements an API named `pmc_clear_pmcon_pwr_failure_sts()`
to clear power failure status bits of PMC General PM Configuration A/B
based on the underlying SoC.
Based on the available PMC register definitions between Sky Lake till
latest Meteor Lake platform, the SoC platform that selects
SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION config has power failure bits
mapped into the MMIO mapped GEN_PMCON_A register where else for the
other SoCs, those power failure bits are belongs to the PCI config
space mapped GEN_PMCON_B register.
BUG=b:265939425
TEST=Able to build the google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icbbe47ccfd489edf9c38f52bdf7cf2de7aa9eedf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72053
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Some boards may want to perform a specific operation before the CSE FW
update final operation begins. For instance, on Brya this new callback
can be used to inform the end-user that an update is in progress.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=Compilation success
Change-Id: Ia4d32a71f3ae61d2e24197fee6b458512f7778a9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72097
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If a CSE update is going to happen and early graphics is supported by
the mainboard, an on-screen text message is displayed to inform the
end user.
CSE update can take a while and an impatient end user facing a black
screen for a while may reset the device unnecessarily.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=On screen text message during CSE update observed on skolas
Change-Id: I28c4fef9345d577be287b76a2a767b5c852ec742
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72098
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 78ee4889dc32 ("soc/amd/cezanne/acpi: Add support for RTC
workaround") added a workaround for the Cezanne silicon. This was copied
to the Mendocino code, but from both the discussion in b:209705576 and
the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/
amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true
Mendocino doesn't need that workaround, so remove it.
TEST=Running suspend_stress_test -c 5 on Chausie shows no errors
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 80b1fa33.
Reason for revert:
"Error: CONFIG() used on unknown value (ENABLE_FSP_ERROR_INFO) at src/soc/intel/xeon_sp/romstage.c:20"
Change-Id: I843322fc9d7ebbc30e9209ae933313f2668bfa40
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch fixes the build failure with 'make -j' where the build
fails at "$(MAKE)... savedefconfig" as that rule doesn't have the
dependency on kconfig/conf.
Normally make takes care of all dependencies, so parallel builds
work well. However if you have recursive make calls, i.e. make
calling make like in these recipes, there is no single make with a
global view of the dependencies anymore, and then multiple "makes"
can try to build the same file concurrently. Adding that explicit
dependency on build/util/kconfig/conf makes sure the recursive make
is only called later when the top-level make already finished
building build/util/kconfig/conf.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id44ab44618b0ddfb3c2472c469499429118bf76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72070
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
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Provide D-states to enter LPM (S0ix) for MTL
Values were copied over from corresponding ADL file (as MTL data
sheet is not yet available).
TEST=Built and tested on Rex by verifying SSDT contents
Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I3138edd8125601b6c9dff5f9252a4bba8385146d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: Idea51d23d30735062f38f10162c77131fbb07776
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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RAID_MISC_ROM_FILE isn't used and there isn't "misc.bin" file.
Change-Id: I4007537ee2d177010f04f733e8a9b7167b0fce73
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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RAID_ROM_FILE isn't used and there isn't "raid.bin" file.
Change-Id: I056c122289f05d662b1b1e5a8cdc0c73915f7249
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I62d3fb4d63262925818712120664ddc8ec80c922
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not
be selected.
Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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After calling FSP MemoryInit API, if there is an error, some FSPs
(such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB.
Check existence of such a HOB and handle it accordingly.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I612393ffac90815606f3f2544bc1518f6912e605
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71952
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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MAINBOARD_BLOBS_DIR is defined the same way by
picasso/cezanne/mendocino/phoenix/glinda and unused by stoneyridge, so
move it to a common area.
This makefile variable is currently only used to locate APCB blobs for
the different mainboards.
Add a Kconfig option to point to the APCB blobs directory. This allows
simple overriding to locations such as site-local.
TEST=Timeless builds
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I0702fdb97fbc2c73d97994ab4d5161ff0f467518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69410
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The dir_location and efs_location have the same meaning. Now the dir
means body.
Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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For future BIOS image entry whose instance = 1.
Change-Id: Iaa40872b270cf9ff289794c8c51c4d8b448d862d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Change-Id: I0a3a3d8b3f898dc147eff54fe4ae2611139951ac
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72143
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs
to be moved to the bottom of the ROM area to cover that space.
The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either
4 or 8MiB, so that's adjusted. To leave some room for the RW_LEGACY
region, the two RW regions are adjusted to 3MiB each, which should be
plenty.
The GBB region had to be moved from the front of the WP_RO region to the
end to avoid conflicting with the EFS, which needs to be inside the
coreboot cbfs area.
Also get rid of AMD_FWM_POSITION_INDEX. The FWM position is no longer
needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update the mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
MT62F1G32D2DS-026 WT:B 4 (0100)
K3KL8L80CM-MGCT 4 (0100)
H58G56BK7BX068 4 (0100)
BUG=b:259467147
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I204e871129a1b15d7c373d579e10a7b9ab6deabe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71906
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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To make the code slightly easier to read, add a comment about the scope
to the #endif of the outer #ifdef block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic2bc83c77750cd8a509f4755fdfa4daaf082d754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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DEFAULT_SOFTWARE_CONNECTION_MANAGER
Needs to be selected for ChromeOS mainboards even for non-ChromeOS
builds, else Thunderbolt/USB4 doesn't work under Windows (and likely
Linux as well).
TEST=build/boot Windows on drobit/banshee, verify TB functional
Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Possible Buffer Overflow - Array Index Out of Bounds. Array
regions size is 256 but 'i' iterates from 0 to 256.
Found-by: Klockwork
BUG=None
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79509146431e4584e50af4477f3f50dc3cf01bcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72138
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c.
Reason for revert: breaks TBT and TypeC display on Brya0
Bug=265375098
Branch=firmware-brya-14505.B
Test=Build and boot Skolas board with Brya0 image. Test TBT
and TypeC display functionality.
Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081
Reviewed-by: Prashant Malani <pmalani@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the APL EDS vol 1 (doc 569262) to be able to implement common
code API to clear the power failure status bits.
Note: as per the EDS those newly added power management failure bits
are RO and shouldn't change any functionality of the existing APL SoC
code. The reason behind adding those macro definitions is to fix the
compilation issue due to code change targeted for the Intel SKL and
Xeon-SP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the DNV EDS vol (doc 558579) to be able to implement common
code API to clear the power failure status bits.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl6 and observe that POST codes are
displayed before DRAM training.
Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Move logic previously used only in the mc_apl2 variant to
the mainboard level so that other variants can also make
use of it without code duplication.
This functionality on the mc_apl6 variant will be enabled
in a follow-up patch.
BUG=none
TEST=Boot on siemens/mc_apl2 and observe that the POST
codes are displayed before DRAM training.
Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I93455f38663cf29d8b5160ac21c94db08eb44fa9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I1542c5662162e919752c334baa9c31cddc5036af
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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