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2023-09-28soc/amd/genoa: Add Kconfig/Makefile to generate PSP imageArthur Heymans
TESTED: AMD onyx reaches x86 code Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28mb/google/rex/var/ovis: Add DPTF configurationJakub Czapiga
Configure PL1 and PL2 are configured for powerformance. Based on values from Intel Meteor Lake UH Power Map document ID:640982 BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/amd/genoa: Add chipset.cbvbpandya
Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362 Signed-off-by: vbpandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78082 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-09-28mb/google/nissa/var/craask: Correct the USB setting by fw_configRen Kuo
Modify the settings: 1)Add fw_config probe on USB type C for "DB_1C_LTE". 2)Add fw_config probe on USB type A for "DB_1A_HDMI". BUG=b:296791122 TEST=build and check USB functions on craask Change-Id: I2775098ab380995e62f264bc51a430762c256c4b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28soc/intel/alderlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/redrix with 32MB (W25Q256JWEIM) SPI-Flash. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-27Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id c6e5fba929ef (2023-09-02): MDN: Update ABL to version WABLMDN3516B01A to commit id ae822f2d0db7 (2023-09-21): MDN: Restore SMU fw version 90.41.0 This brings in 3 new commits: ae822f2d0d MDN: Restore SMU fw version 90.41.0 d4f752a6fa MDN: Restore MP2 fw version 0A.0D.00.06 7b7b04723b CZN: Update VBIOS to version 021 BUG=b:301109173 BRANCH=none Change-Id: I02b39ea94a23f7c25533347f06cd8488711c37cd Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-27Documentation: Update 4.22 release notes with x86 .data sectionJeremy Compostella
Change-Id: I2d6d611df8930ad0c473489eacee9019cbdacb9e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78000 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-27acpi: Fix typosNaresh Solanki
Change-Id: Ie986c1cbbc9bcc7817dfeb04a4be86898b302987 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-27soc/intel/jasperlake: Set GPE_STS and GPE_EN register basesJonathon Hall
Jasper Lake was missing these bases, so attempting to enable an SCI would poke unrelated registers starting from offset 0. Set them so GPEs can be enabled. GPE is used on the Librem 11 for the keyboard dock connector, its sense signal on GPP_D4 raises a GPE which is used to indicate tablet/laptop mode to the OS. The register offsets are documented in the datasheet volume 2 (Intel document 634545), all groups' GPE_STS/GPE_EN start at the same offsets. Change-Id: Ib6b9b9a79e9cc4467e609eaf591ec4e87b78d617 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78097 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26Documentation/external_docs.md: Add link to EGS paperDavid Hendricks
Intel published a technical paper about coreboot on Eagle Stream. The document number is 778593. Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: Ic67f9a69b7e2ea526c3c5a604e38bb939c72feec Reviewed-on: https://review.coreboot.org/c/coreboot/+/78117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-26payloads/edk2/Makefile: Improve dirty repo check, sync submodulesMatt DeVillier
Don't skip checking out the specified edk2 branch if the repo contains untracked files, which may be the case if the EDK2_GOP_DRIVER option is selected. Also ensure the submodule pointers are correct when checking out. TEST=build google/panther with GOP driver option and edk2 payload 2x, switching branches between builds and ensure the correct branch is used each time and submodules are synced with branch. Change-Id: If7040bd5c49209b37a4b308485bf59352197d3b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-26payloads/edk2: Guard MrChromebox's build optionsSean Rhodes
Several of the build commands passed by the Makefile only exist in MrChromebox's fork of edk2. Guard these, and the corresponding Kconfig options, against the selection of the MrChromebox repository. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I41d8d54e5b91990dd9fb88967fcd549a86cf6fe9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78036 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26amdfwtool: Support firmware offsets of larger than 16MiBZheng Bao
The mapped windows is up to 16M. Even if the flash size is 32MB, it is not mapped at 0xFE000000. So using "0xFFFFFFFF - rom_size + 1" to get the "rom_base_address" can only explain well when rom_size is less or equal to 16MB. For larger size, it is not physically correct (Even though it can get expected result). If the flash size is larger than 16M, we assume the given addresses are already relative ones. So we don't need the physical base address any more. This commit is part of a series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: I9eea45f0be45a959c4150030e7e213923510ad68 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-26soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes
Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-26amdfwtool: Add APCB for new combo entryZheng Bao
Besides fw.cfg, each combo entry needs dedicated APCB files. If no new APCB is provided, the main APCB is used for all entries. The combo is fully supported after this. Change-Id: I21c2bf7d98ded43848ae8a8bb61d1ded1a277f88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58620 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26arch/x86/cpu_common: use cpuid_get_max_funcFelix Held
Use cpuid_get_max_func instead of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I590f0c840bc62bbd0b5038c5827367d811e30d10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-26arch/x86/smbios: fix extended CPUID level check logicFelix Held
Before the cpuid(0x80000001) read in smbios_write_type4, it was previously checked in a slightly convoluted way if the result from cpu_cpuid_extended_level was larger than 0x80000001, but the check should be if it is larger or equal to 0x80000001. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabcfdb2b8b90d80baf8f4c4d2fd79f1f44866dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78107 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26arch/x86/smbios: use cpu_cpuid_extended_levelFelix Held
Use cpu_cpuid_extended_level instead of open-coding the same functionality in smbios_write_type4. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8e20726ea17e8ed94d5ff8f6568758fcfa162ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-26mb/google/brya/var/dochi: Add memory configMorris Hsu
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:298337185 BRANCH=firmware-brya-14505.B TEST=FW_NAME=dochi emerge-brya coreboot Change-Id: I182e287423e6f784712c5004a6fe2d12a5b36190 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-26mb/google/dedede/var/taranza: Add power limits for JSL N4500 and N5100Sheng-Liang Pan
Add PLx from JSL PDG (ID: 613095) in taranza devicetree. Add ramstage.c in Makefile.inc and update Taranza power limits in taranza ramstage.c. BUG=b:296004956 TEST=emerge-dedede coreboot and check psys and PLx value on taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-09-26mb/google/rex/var/rex0: Configure I2C5 timingIvy Jian
Configure I2C5 timing in devicetree to ensure I2C devices meet timing requirement. BUG=b:300177424 TEST=Build and check I2C devices timing meet spec. | | I2C5-Before | I2C5-After | |-------------|-------------|------------| | FSMB(KHz) | 445.400 | 343.638 | | TLOW(us) | 1.543 | 2.068 | | THIGH(us) | 0.475 | 0.604 | | THD:STA(us) | 0.603 | 0.711 | | TSU:STA(us) | 0.612 | 0.611 | | TSU:STO(us) | 0.605 | 0.611 | | TBUF(us) | >1.914 | >2.044 | Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26mb/google/nissa/var/pirrha: Add 4th DTT sensorSeunghwan Kim
Add 4th sensor device for DTT tuning. BUG=b:292134655 TEST=Built and verified DTT tool could monitor the new sensor device Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2023-09-25mb/clevo/cml-u: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I8530bb9b89a12ae831a4716bdec8c66c7f3f74a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-09-25supermicro/x11-lga1151-series: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I73844dc4686dd014ec2209e296cc4aff47280e9f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-09-25mb/google/oak: Move common selects to BOARD_GOOGLE_OAK_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_OAK_COMMON. Thus, move all selects to the latter option. Change-Id: Id80b8a9bcad9337c8aa76fa6e5d2c9752b8021b7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-25mb/google/guybrush: Use only one option for common selectsFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_BASEBOARD_GUYBRUSH. Thus, move all selects to the latter option. Change-Id: I570c3cfd3d100ad90e35ec5d89686cb6a4bd8e82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-25soc/intel/xeon_sp: Add HDA disable supportPatrick Rudolph
Currently the HDA device can neither be disabled using softstraps nor can it be disabled by using FSP UPDs. Add code to disable it in coreboot when it's marked as 'off' in coreboot's devicetree. TEST: Device 00:1f.3 is hidden and platform boots into OS without issue. Change-Id: Ifa1422d653cf81ee6faf2bdda27a471c2084642b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77873 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25mb/google/brya: Add SOF driver entries for Nissa-based boardsMatt DeVillier
Facilitates correct profile selection by SOF Windows drivers. Profiles for nokris and quandiso will be added once correct board configs can be determined. TEST=build/boot Win11 on google/craask, verify correct audio profiles loaded, audio functional. Change-Id: Id4582b5dd74a4905ea509813ec99663577360095 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-09-25drivers/sof: Add support for rt5650 speaker/jack topologyMatt DeVillier
Enables correct identification of boards using rt5650 codec for either speaker or headset output (or both) by SOF Windows drivers. Change-Id: Ied9717955fcfca33bd63a34f3f6961deb045239c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25soc/amd/common/graphics: Update VBIOS cache data before hashingMatt DeVillier
On the first boot after flashing, the data read from the FMAP and stored in vbios_data is not valid, so hashing it produces a value which will not match on the subsequent boot, requiring an additional boot before the vbios_data and hash match / before the GOP driver can be skipped. To fix this, update vbios_data before hashing. BUG=b:271850970 BRANCH=skyrim TEST=build/boot google/skyrim with USE_SELECTIVE_GOP_INIT selected, verify that GOP driver execution is skipping on 2nd boot after flashing when booting in normal / verified boot mode. Change-Id: Idc10d752bfa004a34b91307a743c620fb97eeb82 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77727 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-25mb/purism/librem_l1um_v2: Add support for Purism Librem L1UM v2Jonathon Hall
This adds support for booting the Librem L1UM v2 mainboard with coreboot, using binaries from the original BIOS. The following features have been tested on PureOS: - USB: front USB3, rear USB3, USB2 header on board - SATA: 8x SATA ports, one M.2 M-key shared with SATA0 - PCIe: two PEG slots, one PCIe slot from PCH, and one M.2 M-key - Network: 2x GbE - Video: BMC VGA and IPMI - Serial: Physical serial port, provided by BMC SuperIO - Hardware monitor - POST code display - TPM2 These binaries are extracted from the original BIOS: - Intel Management Engine - Intel Firmware Descriptor This was developed and tested on a Librem L1UM v2 using a Core i7-9700 CPU. Native graphics init works for the Aspeed AST2500 BMC. For development, the serial port console works from bootblock. Early init waits for the BMC to finish booting since this is required for serial port output. Change-Id: I990f6024d65098a9553d7d1fe7f36614cc55ea19 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75090 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25mb/google/brya/var/dochi: add generic LPDDR5 SPDs for DochiMorris Hsu
Add Makefile.inc to include five generic LPDDR5 SPDs for the following parts for Dochi: DRAM Part Name ID to assign MT62F1G32D2DS-023 WT:B 0 (0000) K3KL8L80CM-MGCT 1 (0001) H58G56BK8BX068 0 (0000) BUG=b:298337185 TEST=USE="project_dochi emerge-brya coreboot" Change-Id: If0fd4bc950cef484db53b7b21849cfdfdd7816a5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-25mb/google/corsola: Move board-specific selects to board optionsFelix Singer
Instead of selecting board-specific options under the common option and making them conditional, move them to their related board option. Change-Id: If9bea61cb84590e7455add908fa7722c60444503 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25mb/google/corsola: Fine tune LCM ADC voltagesRuihai Zhou
The tolerance of LCM voltage table is too small which leads to wrong panel ID detection. Fine tune LCM ADC voltages based on hardware calculations. BUG=b:300418909 TEST=FW screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id8dec043584f4c552837f70adb491584bfda7acf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-25util: Drop flashrom -p host alias which equals to -p internalHsuan Ting Chen
There is a technical debt in ChromeOS flashrom, `cros_alias.c`, which is to work around ChromeOS calling flashrom with `-p host` instead of `-p internal`. Replace all `-p host` occurrences with `-p internal`. BUG=b:296978620 TEST=none Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I81674213b9a21598002f349ced1130f0844841ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25treewide: Adopt TCG standard namingJon Murphy
Adopt TCG standard naming and definitions for TPM Return codes. BUG=b:296439237 TEST=Build and boot to OS on skyrim BRANCH=None Change-Id: I60755723262ec205a4c134948b0250aac4974d35 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77665 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25Revert "soc/intel/jasperlake: Enable early caching of RAMTOP region"Matt DeVillier
This reverts commit 21e61847c4cf643d79855deba8f58fd45808d571. Reverting as it breaks booting on google/dedede based boards. First boot after flashing is successful, 2nd hangs with the following error: [EMERG] FspMemoryInit returned with error 0x80000003! TEST=build/boot google/dedede (magpie, metaknight) Change-Id: I6a2474617b444414c4248dbeda23ed0915704a17 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-09-25commonlib: Make CBMEM_ID_CSE_BP_INFO little endian, fix id for stringSubrata Banik
This patch fixes the mistake introduced with 'commit 17cea380d985 ("commonlib: Add CBMEM ID to store CSE Boot Partition Info")' where single CBMEM ID name `CBMEM_ID_CSE_INFO` is associated with two different name description. Additionally, use little endian format for `CBMEM_ID_CSE_INFO` cbmem id. TEST=Build and boot google/rex. Able to fix the issue introduced in commit 17cea380d985 while running cbmem --list and verify that the associated name string is proper. Change-Id: I4235f1f6881ab86ccb252065e922d5d526f7f1f7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78110 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-09-24Doc/: Remove an extra spacePatrick Georgi
Change-Id: I462d0bd3e9f3b425631987fa793d29323c3f9d61 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-24Doc/infra: Update my contact informationPatrick Georgi
Change-Id: If7081897d8232e3ac84de0fa76689ad05808996d Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/cherry: Move common selects to BOARD_GOOGLE_CHERRY_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CHERRY_COMMON. Thus, move all selects to the latter option. Change-Id: I080201761d0a06d3b8a5a29de6085dde58960a60 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75085 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/asurada: Move common selects to BOARD_GOOGLE_ASURADA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_ASURADA_COMMON. Thus, move all selects to the latter option. Change-Id: Id80523dce70f13f64a49b71656276c51e80ae5cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75084 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/rex: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id69ea99b452e4214fcc81335a5c961b4da3ce48b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/veyron: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id85503a5ec970ea92c07b99ec7048c521d85c79b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id450a4b6e409a548ee4d79b8b2ebf30ef61a3e27 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78083 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23commonlib: Add CBMEM ID to store CSE Boot Partition InfoKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. In order to backup PSR data before initiating firmware downgrade, CSE Lite firmware supports a command to do this. This command works only after memory has been initialized. So the CSE firmware downgrade can be done only in post-RAM stage. CSE firmware sync actions will be moved to early ramstage to support this. Moving CSE firmware sync actions to ramstage results in cse_get_bp_info command taking additional boot time of ~45-55ms. To avoid this, cse_get_bp_info will be sent in early romstage and the response will be stored in cbmem to avoid sending the command again, and re-use in ramstage. This patch adds a CBMEM ID to store this CSE Boot Partition Info response in cbmem. BUG=b:273207144 Change-Id: I914befadab4ad0ac197435e2a2c4343a796b2b1b Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Move cse_store_rw_fw_version from cse_print_boot_partition_infoKrishna P Bhat D
cse_store_rw_fw_version() stores CSE RW firmware version in global variable or cbmem in romstage and ramstage respectively, based on the stage it is called in. The call to this function is from the cse_print_boot_partition_info() in cse_get_bp_info. In the subsequent patches, the idea is to send the cse_get_bp_info early in romstage and store in cbmem once memory is initialized. So when the cse_fw_sync is called in early ramstage, the stored cse_bp_info_rsp is used instead of sending the CSE get boot partition info command again. To de-link the call to cse_store_rw_fw_version from cse_get_bp_info and to ensure the CSE RW FW version is stored in all cases, moving the function to do_cse_fw_sync. BUG=b:273207144 Change-Id: I0add2c167c85cbddef2ecb4c019061a08562bbdf Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Make cse_bp_info response globalKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. PSR data backup command works only after memory has been initialized. Moving only the downgrade would add complexity of splitting the cse_fw_sync across pre-RAM and post-RAM stages. So the idea is to move cse_fw_sync into ramstage when PSR is enabled. We are introducing a flow to get CSE boot partition info in early romstage and then same data will be stored in cbmem once DRAM is initialized. The CSE BP info data in cbmem will be utilized in early ramstage to perform cse firmware sync operations. This helps in avoiding re-sending the CSE get boot partition info command in ramstage. Having cse_bp_info_rsp as global helps in de-linking cse_get_bp_info from cse_fw_sync. Many functions take cse_bp_info as input parameter. Since cse_bp_info_rsp is global now, we can make use of global cse_bp_info and remove it as input parameter from those functions. BUG=b:273207144 TEST=Verify cse_bp_info_rsp holds value across the stage. Change-Id: I0ee050b49fcae574882378b94329c36a228e6815 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77070 Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2023-09-23soc/intel/meteorlake: Reduce memory test sizeSubrata Banik
Enable upd to reduce size of the memory test. BUG=b:301441204 TEST=Able to build and boot google/rex. w/o this patch: 951:returning from FspMemoryInit 650,922 (79,560) w/ this patch: 951:returning from FspMemoryInit 618,490 (45,621) Change-Id: I903591ec749d270a98895dafb2d8f8d0b287c26a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78067 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-23soc/intel/meteorlake: Hook up UPD LowerBasicMemTestSizeSubrata Banik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure it via devicetree. BUG=b:301441204 TEST=Verified by enabling/disabling the UPD on google/rex. Change-Id: Iec466aeaebd72f222d97f720a85bbb8c27e26325 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78066 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-23vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86Subrata Banik
Update header files for FSP for Meteor Lake platform to version 3323.86, previous version being 3323.84. FSPM: 1. Added new UPDs - AcLoadline - DcLoadline - LowerBasicMemTestSize 2. Address offset changes BUG=b:301441204 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-23arch/x86/cpu_common: use cpuid_e[a,c]xFelix Held
Use cpuid_eax and cpuid_ecx instead of sort-of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0dc2be4f602bf63183b9096e38403ae2f45d959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78058 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23arch/x86/cpu_common: use cpu_cpuid_extended_levelFelix Held
Use cpu_cpuid_extended_level instead of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ea22c3997769179311f3c8822e6d8cc15a8834c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78057 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23vboot: Remove the unnecessary PCR digest checkYi Chou
This PCR digest length check is no longer necessary. Signed-off-by: Yi Chou <yich@google.com> Change-Id: I256938c69be7787f5c8fca3e633ac93a69368452 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78084 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-22mb/google/skyrim/frostflow: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on frostflow, verify unknown device for the fingerprint reader no longer present. Change-Id: I666e92706f698608f2df92c8296cfb615d5ece67 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/guybrush: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on dewatt, verify unknown device for the ACP machine driver no longer present. Change-Id: I44d25fd2ea75593383cbb14f2324d4376b399de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/zork: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on morphius, verify unknown device for the ACP machine driver no longer present. Change-Id: I14347ab6c840066db4ff700eff1aad4cf6faf66b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/nissa/var/quandiso: Update USB port configRobert Chen
1. Support world facing usb camera on usb2_port7. 2. Update MB/DB fw_config to distinguish LTE and non-LTE devices. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0c508475fdc86f0d7357f19684bdaae06e77fc27 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Add P-sensor supportRobert Chen
- GPIO changes: GPP_B5 ==> I2C_P_SENSOR_SDA GPP_B6 ==> I2C_P_SENSOR_SCL GPP_H19 ==> P_SENSOR_INT_L - I2C SX9324 support - Disable GPIOs when sub board LTE not used BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5ed82b125b6c594225efca418017ef42f4f63b9d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-22mb/google/nissa/var/quandiso: Add SD card supportRobert Chen
GPIO changes - GPP_D8 ==> SD_CLKREQ_ODL - GPP_D17 ==> SD_WAKE_N - GPP_H12 ==> SD_PERST_L - GPP_H13 ==> EN_PP3300_SD_X Genesys Logic GL9750 support BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib7c80f43680481c0d1a18662fa494012390a984d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77391 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Disable WCAM supportRobert Chen
Quandiso doesn't support mipi WCAM. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I8a166d0bb1c034f2e3a5af7456500abd078e93f9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77389 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Update initial files based on yavillaRobert Chen
Update files copied from yavilla - fw_config setting - GPIO setting - Kconfig setting - overridetree setting - SPD memory parts - variant setting BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage flash bin file in DUT Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22security/tpm: Remove unnecessary tss_common.hJon Murphy
Remove the unnecessary tss_common.h header from the repo. tss_errors.h is a more appropriate place for the TPM_SUCCESS value, and the other define is only used by tpm_common.c and can be placed there. BUG=b:296439237 TEST=Builds Change-Id: I99cf90f244a75c1eeab5e9e1500e05c24ae0a8e5 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78033 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-22mb/google/dedede: Fix SOF config for unprovisioned audio ampMatt DeVillier
Dedede boards which select AUDIO_AMP_UNPROVISIONED via fw_config use rt1015 for the speaker topology, not max98360a. TEST=build/boot Win11 on google/magpie, verify correct audio profile selected. Change-Id: I5b75bd8fd37d2837de3c5bd25a02411a6982103b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-22drivers/sof: Add support for rt1019 speaker topologyMatt DeVillier
Enables correct identification of boards using rt1019 speaker amplifier by SOF Windows drivers. TEST=tested with rest of patch train Change-Id: I550dc8614e6e21d6d8715c12b7a4af35117497b5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22soc/intel/Makefile.inc: Add comment where CONFIG_CSE_*_FILE are usedReka Norman
commit 06cb756f0202d7 ("soc/intel/common/block/cse/Kconfig: Remove unused symbols") removed these Kconfigs since it's not obvious where they're used. Add a comment to make it easier to grep for their uses. Change-Id: I27d94e8a558d6e73004d45cd2aedd94678d29b94 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78041 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22Revert "soc/intel/common/block/cse/Kconfig: Remove unused symbols"Reka Norman
This reverts commit 06cb756f0202d78d299b30728b6559f6107c43c3. Reason for revert: These Kconfigs are needed by boards which use the CSE stitching tools (i.e. select STITCH_ME_BIN). They're selected by some boards in the downstream ChromeOS repo. They're used in src/soc/intel/Makefile.inc (see the line with `$(CONFIG_CSE_$(2)_FILE)`). Change-Id: Ide6fc74b457439f06b7ef9b37f11d6c9ff226b80 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76719 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/puff: Add VBT for Genesis variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware genesis_13324.283.0 TEST=build genesis with FSP GOP display init Change-Id: If836b214da1350111d7b7d1f24865199f814c521 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-09-22mb/google/puff: Add VBT for Ambassador variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware ambassador_13324.283.0 TEST=build ambassador with FSP GOP display init. Change-Id: I5c47700c5abe7d96112702d48a2b749f1784a494 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78032 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-22mb/google/puff: Set early GPIOs to enable bootblock consoleMatt DeVillier
Without the PCH UART GPIOs set early, there is no serial console output until ramstage. Add them to the early GPIOs for all puff variants. TEST=build/boot google/puff (wyvern) with serial console enabled, verify console output starts in bootblock. Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22soc/mediatek: Move common devapc definitions to common/Nina Wu
Move following definitions to common/ 1) the definition of the bit fields for domain remap 2) the definition of the structure for the permission of all domains Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/brya: Init TPM in bootblock when not using vbootMatt DeVillier
Brya queries the TPM in early ramstage (pre-device init) to determine if the CR50 has support for long-pulse interrupts. If the TPM (and underlying I2C controller) hasn't already been setup in verstage, it will fail to do so in ramstage since the I2C controller has not yet been initialized. To work around this, initialize the TPM in bootblock for the non-vboot case, to ensure the I2C controller is set up when needed in early ramstage. TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem console when initializing TPM in early ramstage. Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/rex/var/rex0: Add entries for SAR Proximity SensorsSubrata Banik
This patch adds ACPI entries for SAR Proximity Sensors as below SAR1 Sensor: - SAR1_INT_L : GPP_E00 - I2C5 7-bit address 0x28 SAR2 Sensor:   - SAR2_INT_L : GPP_E08 - I2C 7-bit address 0x2c BUG=b:297977526 TEST=Able to build and boot google/rex. w/o this patch: Total 6 devices are listed below: > ls -lt /sys/bus/iio/devices/iio:device* /sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/ LNXSYBUS:00/PNP0A08:00/device:07/ /sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 w/ this patch: Total 8 devices are listed below: > ls -lt /sys/bus/iio/devices/iio:device* /sys/bus/iio/devices/iio:device6 -> ../../../devices/pci0000:00/ 0000:00:19.1/i2c_designware.4/i2c- /sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/ LNXSYBUS:00/PNP0A08:00/device:07/ /sys/bus/iio/devices/iio:device7 -> ../../../devices/pci0000:00/ 0000:00:19.1/i2c_designware.4/i2c- /sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 Change-Id: I0a518d58915f9f4dbe58a45c4dc5875abbfda135 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78045 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-09-22coreboot.org-status: Make URLs branch agnosticPatrick Georgi
The primary branch changed names. To remain robust, just use HEAD, which will point to whatever is authoritative. Change-Id: I809ea748a5e51f4eea6bc227fa1fc5c8b07fe2ef Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78015 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/rex: Add new FMD for prod (QS) Meteor Lake siliconSubrata Banik
Intel Meteor Lake QS silicon provides better size optimized pre-x86 reset blobs. This patch creates a new flash layout (FMD) for QS to accommodate those optimizations, and renames the existing FMD for ES (pre-prod) silicon. Comparative analysis between QS and ES flash layout is here: For QS silicon: - SI_ALL reduced from 9MB to 8MB. - SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI layout. - ME_RW_A/B reduce from ~4.5MB to 4MB. - Ensure RW-B slot is starting at 16MB boundary. - Unused space increased by 1MB. For ES silicon: - SI_ALL: 9MB - SI_BIOS: 23MB - ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH). - Unused space 3MB (for release) and 2MB (for debug) layout. Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-09-21MAINTAINERS: Remove Elyes as toolchain maintainerElyes Haouas
I didn't have enough time, so it's reasonable to remove myself. Change-Id: I8f7d87f70916f3d0697b6c38ca6d75f3375bd374 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-21mb/google/geralt: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I590b7fb5f5f52cbf1a61c65f8fac757e36feac5e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/kukui: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I866333a234203dc2da3d4dd8c4f87e4cfa332787 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/myst: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Ia4ed3491e6a32659b957285ab20ad47c9085083c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75025 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/skyrim: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I097d50a7af7c8ea48369806e8bb73734a8e84470 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75024 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/gru: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id7f9b598cc9df51ddf664b851172cc96a710c580 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75023 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/asurada: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I3f4965b8b253983ad1f8db77e1b91860a270c305 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21Documentation: Remove unused build targetsFelix Singer
The options in conf.py for the following build targets are either commented out or contain example values, which suggests that there was no interest in them recently. Their comments also seem more like generated examples. * LaTeX * man pages * Texinfo In order to clean up our configs and scripts for the documentation, remove the configuration options from conf.py for these build targets. Also, remove the build targets responsible for generating a PDF file from Makefile. Don't touch Makefile.sphinx for now though as we usually wrap around it. We may bring these build targets back if there is real interest in them, but it seems only the HTML target was really used. Change-Id: I7df8ea886f94d9b25e8eeb0ccbc2a7392b96a575 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77439 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/guybrush: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: If2c9c52f1e2866082df8e534b1a074639bb62db2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75020 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/oak: Move Selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Idf4a566af3853636945709c88c03fb8e777211c2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/zork: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iaa73bf7f85f840299c467b7d712546d3f72a4e75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/cherry: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id1b0d375670f9e59047eff737bc17e61bf93175e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75016 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/mistral: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I1033a974a818308b31e1334cad5869d2cd81bd9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75017 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I207e25059a9fb9e6a951018e954662931b3f8b93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75018 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/kahlee: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id060f781b87567da2756c89275002b9ea4f4976c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75015 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/zork/morphius: Hide FPR, PENH from Windows OSMatt DeVillier
No drivers exists or are needed, so use devicetree hidden keyword to set the ACPI status to hidden to prevent unknown devices from showing in Windows Device Manager. TEST=build/boot Win11 on morphius, verify unknown devices for the fingerprint reader and stylus detection are no longer shown. Change-Id: I992c0ec8d97c6041e3a268445613bfa42dd8b279 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21drivers/generic/gpio_keys: Write device ACPI statusMatt DeVillier
Allows device to be hidden from OS (Windows) via devicetree 'hidden' keyword. TEST=tested with rest of patch train Change-Id: I81482bd19e24627cab80deed2b9057f45b6ac0a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78037 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21soc/amd/*/cpu: factor out common noncar mp_init_cpusFelix Held
Since all non-CAR AMD SoCs have the same mp_init_cpus implementation, factor it out and move it to a common location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibf4fa667106769989c916d941addb1cba38b7f13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-21mainboard/google/skyrim: Enable wake-on-DPRobert Zieba
Enable wake-on-DP by adding USB mux events to the wake mask. The EC wakes the AP with these events for DP connect/disconnect. BUG=b:294307786 TEST=DP connect/disconnect wakes the DUT appropriately. Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21soc/amd/mendocino: Do not load MP2 Firmware when in ROKarthikeyan Ramasubramanian
Currently MP2 Firmware is not built into RO firmware section but the soft fuse bit to disable MP2 firmware loading is not set. This causes the device to boot loop during recovery mode. Set the bit to disable MP2 firmware loading in RO. BUG=b:259554520 TEST=Build and boot to OS in Skyrim under both normal and recovery modes. Change-Id: I9e4cf4f72e2d36ad3cc33629ddb501ecdbf5eda9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78023 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/rex/var/karis: Enable PIXA touchpadTyler Wang
Karis uses PIXA touchpad, update related settings. BUG=b:294155897 TEST=(1) emerge-rex coreboot (2) Test on karis, touchpad function works Change-Id: I26e3257485c4abe050de7a79c6d3b72dbd048710 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77517 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-21mb/x11-lga1151-series: Add x11ssw-fKieran Kunhya
This board is similar to x11ssm-f but has a proprietary form factor with NVMe and a single x16 slot (potentially bifurcated to 2x x8) and a x4 slot. Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 Signed-off-by: Kieran Kunhya <kieran@kunhya.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-09-20arch/arm64/Makefile.inc: Replace HAVE_ACPI_SUPPORT with HAVE_ACPI_TABLESMaximilian Brune
CONFIG_HAVE_ACPI_SUPPORT does not exist. Replace it with HAVE_ACPI_TABLES. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icc7c00dc19cae4be13e6c8cc0084a69aed8fb8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-20cpu/x86/mtrr/debug: rename variables in display_variable_mtrrFelix Held
Change the name of msr_a and msr_m to the more descriptive msr_base and msr_mask. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6e0010f6d35ccf4288f4e0df8f51ea5f17c98b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78007 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20cpu/x86/mtrr/debug: use MTRR_PHYS_MASKFelix Held
Instead adding 1 to the result of MTRR_PHYS_BASE(index) to get the variable MTRR's mask MSR number, use the MTRR_PHYS_MASK macro. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieecc57feb25afa83f3a53384e5a286f2e4e82093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>