| Age | Commit message (Collapse) | Author |
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HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.
BUG=b:317009620
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED
Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85124
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Since commit e633d370 (soc/intel/cometlake: Enable early caching of
RAMTOP region), cmos.layout for Cannon Lake boards must have a ramtop
entry, add it.
Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77670
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the DEV_PTR macro to resolve devicetree aliases instead of using the
autogenerated reference names from sconfig directly.
TEST=Timeless build did not change
Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85093
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Fix the syntax [1] for the footnote about the onboard memory
configuration so that it renders properly in the generated html.
This also fixes a "Unknown target name" error when building with
newer versions of Sphinx (tested with 8.1.3).
[1] https://myst-parser.readthedocs.io/en/latest/syntax/typography.html#footnotes
Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85412
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add Micron memory part H58G56CK8BX146 to LP5 global list.
And Regenerate the SPD files for the SoC. The specification
is attached in issue tracker.
BUG=b:367841051
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I2a003aad32bca9ae5438973ecf0d7872481fee20
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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ASRock IMB-1222 motherboard [1, 2].
[1] https://www.asrockind.com/en-gb/IMB-1222
[2] commit c1caa33a2de1
Change-Id: Ifa5763e19f917c720bd6b92465eeca04bf09db0c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85364
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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These header files do not seem to be used in coreboot. Presumably
they're left over after the code that used them was removed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ide70239c7c2e93fff548d989735450396308c62b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85370
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The code is simplified by using the mmio.h macros clrsetbits.
Change-Id: Iab71ab4d6e8b6c38e07641dae3b38093690543e8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85325
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to layout restrictions on mc_ehl5, the eMMC interface is limited to
operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the eMMC controller to DDR50 mode
only so that the eMMC driver in OS will choose the right mode for
operation even if the attached eMMC card supports higher modes.
BUG=none
TEST=Boot into Linux and check dmesg output for mmc modes
Change-Id: Ie3214bc3e25e7af706a5c96244d0be50f4bb3094
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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As the functionality is required for other devices, it makes sense to
provide a function for this.
Change-Id: If1f070eebd365de93d4bce13d5201045d3306b17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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As the registers for SD-Card and eMMC are identical, the names of the
register defines should also be kept more general. Therefore change the
defines from 'SD_' to 'MMC_'.
Change-Id: I2e0839a00f1b097f92f4f7774d973196d2d0e9a3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85313
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reserve 70MB memory space for running the OP-TEE image.
BUG=b:317009620
TEST=build pass
Change-Id: I6f75870bdd76e89866508d351b04a0921f30fe4d
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85249
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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kconfig incorrectly builds fatcat instead of feilino.
Modify the kconfig file to successfully compile felino.
BUG=b:379797598
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FELINO
2. Run part_id_gen tool without any errors
Change-Id: Icd76fa97b9879d8f90ae9ee13998b6667f10b39c
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85315
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Modify overridetree based on the schematics revision 20241120.
BUG=b:379797598
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I40362b5c823144b6ab0acb878e58b4f5a295bbdd
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The TCSS configuration now relying on the PD<->PMC communication
for the fatcat board.
This removes the need to override the `TcssAuxOri` UPD setting.
TEST=Booted fatcat successfully. Verified USB-C device detection and
functionality on both TCSS#0 and TCSS#1 ports.
Change-Id: I37d5c6fe68ad529b4da46aad460e5c1bf92179a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices. Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly. Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk. Variants which do not have FP SKUs
will be unaffected.
BUG=b:354769653
TEST=Flash to zork, test FP.
Disable test SKU, flash on zork, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: Ic6dc71013a1c0d5ee5263109eed87a1b31800232
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently only a fixed number of harts/cores can be detected.
This patch adds a Kconfig option which allows to detect the number of
harts at runtime if a SOC or mainboard has a scheme to do so.
As part of that patch SMP logic has been mostly moved to smp_resume,
since it is easier to debug issues at the time smp_resume is called
than it is at smp_pause, since the serial is usually not present at the
time of the first smp_pause call.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The reasoning is that even though vendors currently tend to open source
their OpenSBI implementation, they often do so in their own repository.
So instead of adding all possible source repositories as submodules, we
shall allow specifying a path to an already compiled OpenSBI ELF file.
This is similar of what we currently do on ARM64 with the BL31 binary.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6592ad90a254ca4ac9a6cee89404ad49274f0dea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
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It is unnecessary to look up PMIF controller by mstid in multiple
functions. Just pass `arb` to these functions in order to avoid
redundant calls to get_pmif_controller().
BUG=none
TEST=compiled
Change-Id: I907d6ff029827e4afe4f1d05e39c8dd662c7c45e
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85327
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow schematic(ver.1122A), set GPP_V14 to NC.
BUG=b:380218793, b:366291025
TEST=emerge-rex coreboot pass
Change-Id: I91abc4e07836abb163c8bb28d54a711d2b25375d
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add LAN RTL8125BG related settings based on schematic(ver.1122A).
BUG=b:380218793, b:366291025
TEST=emerge-rex coreboot pass
Change-Id: Icc24f00406d5f91e38725588109c61b7bad099c3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update following fw_config settings:
+-----------+-------------------------+----------------------------+
| Bit 0-1 | DB_USB | 0 --> DB_USB_UNKNOWN |
| | | 1 --> DB_2USBA |
+-----------+-------------------------+----------------------------+
| Bit 2-3 | RETIMER | 0 --> INTEL_HAYDEN_BRIDGE |
+-----------+-------------------------+----------------------------+
| Bit 4-6 | AUDIO | 0 --> ALC5682I_ALC1019 |
+-----------+-------------------------+----------------------------+
| Bit 7-8 | FAN | 0 --> ABSENT |
| | | 1 --> PRESENT |
+-----------+-------------------------+----------------------------+
| Bit 9-10 | MIPI_CAM | 0 --> UF_CAM_HI556 |
+-----------+-------------------------+----------------------------+
| Bit 11-12 | FP_MCU | 0 --> FP_MCU_ABSENT |
| | | 1 --> FP_MCU_NUVOTON |
+-----------+-------------------------+----------------------------+
| Bit 13 | WIFI_TYPE | 0 --> WIFI_CNVI |
| | | 1 --> WIFI_PCIE |
+-----------+-------------------------+----------------------------+
| Bit 14 | KB_TYPE | 0 --> KB_TYPE_DEFAULT |
| | | 1 --> KB_TYPE_CA |
+-----------+-------------------------+----------------------------+
| Bit 15 | PANEL_PWRSEQ_EC_CONTROL | 0 --> WIFI_CNVI |
| | | 1 --> DISABLE |
+-----------+-------------------------+----------------------------+
| Bit 16 | KB_BACKLIGHT | 0 --> KB_BACKLIGHT_ABSENT |
| | | 1 --> KB_BACKLIGHT_PRESENT |
+-----------+-------------------------+----------------------------+
BUG=b:377377766
TEST=emerge-rex coreboot pass
Change-Id: Ic6ab99a05cd6d995dc71b39e002c8ad5b1dafc4a
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85293
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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BUG=b:366291025
TEST=emerge-rex coreboot pass
Change-Id: I8a9de4098739cbcdc09f2ec685c374bee3c236a7
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85248
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate the fatcat_ish variant
The GPP_E07 is not connected on google/fatcat variants using the
Microchip EC AIC.
BUG=b:370984186
TEST=Able to build fatcat/fatcat_ish w/o any error.
Change-Id: I88bd76b2110b4c0742569f1ccb2030ea516b3782
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85223
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Adjusts the EC host command range for the fatcat_ish variant
to 0x800-0x807 & 0x200-0x20f.
This change is necessary because the microchip EC used on the Fatcat
board has a smaller host command range than the ITE/Nuvoton ECs used
on other Fatcat variants.
without this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
with this patch:
[SPEW ] LPC: Trying to open IO window from 800 size 8
BUG=b:370984186
TEST=Able to build fatcat/fatcat_ish w/o any error.
Change-Id: I0d726d60d2a15d2dfaff35f570de479fdc6d15aa
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch adds the "fatcat_ish" board to the fatcat Kconfig.
BUG=b:370984186
TEST=Able to build fatcat/fatcat_ish and verify the correct configs
selected in coreboot.config
Change-Id: I8a49ce54e946dfdfad253ff946da1b37ed50dd0a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85220
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure memory according to schematics revision 20241120.
BUG=b:379797598
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I8420c5cf0421ec9265613c3e1374542a067ce6ed
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85320
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change corrects the indentation and also does the following to have
the ASL code written in a more canonical style:
- Add space between the operator name and "(".
- Use uppercase for hexadecimal values.
Change-Id: Ib946599f8ab4d68b16867912743f4a7a5bc0307d
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85281
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Drive Strength BRI Rsp Object provides information from the OEM
platforms if they have replaced the Bluetooth Radio Interface resistor
to overcome the potential STEP errors on their designs. Based on
configuration, CNV firmware shall adjust the BRI Rsp line drive
strength.
The bri_resistor_value is encoded as follow:
| Bit | Val | Description | Default |
|------+-----+---------------------------------------------+---------|
| 0 | 0 | Device FW default values | 1 |
| | 1 | Override device FW default values | |
| 3:1 | 0 | Reserved (shall be set to 0) | 0 |
| 7:4 | 0 | DSBR override values (only if bit 0 is set) | 0xf |
| 31:7 | 0 | Reserved (shall be set to 0) | 0 |
Possible values:
- 0xf1 (default): indicates that the resistor on board is 33 Ohm
- 0x0 or 0xb1: indicates that the resistor on board is 10 Ohm
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=DSBR methods are added to the wifi device and bluetooth companion
device and they return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e300
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85017
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This feature provides ability to provide Wi-Fi PHY filter
Configuration. A well-defined dedicated filter on particular platform
can be used to perform the maximum Wi-Fi performance.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=WPFC method is added to the wifi device and return the data
supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e270
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84948
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Extended Bluetooth Regulatory Descriptor (EBRD) SAR/RFE are safety
regulations for limiting antenna radiation near human contact. EBRD
provides option to provide up to three sets of TX power limits and
power restrictions.
As the EBRD table is related to the revision 2 of the BRDS, this
commit also adds support for this new revision.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=EBRD method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e250
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84947
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This feature provides ability to set the Bluetooth Dual Mac Mode
setting.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BDMM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e240
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84946
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This feature provides ability to set the Bluetooth Ultra High
Band (UHB) settings per country. The bluetooth UHB country selection
is defined as follow (default is 0):
| Bit | Value | |
|-------+-------+---------------------------------------------------|
| 0 | 0 | No override; use BT device settings |
| | 1 | Force disable BT in all countries that are not |
| | | defined in the following bits |
| 1 | 0 | USA 6GHz BT disable |
| | 1 | 6GHz BT allowed in the USA (enabled only if the |
| | | device is certified to the USA) |
| 2 | 0 | Rest of the World 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Rest of the World (enabled |
| | | only if the device is certified to the rest |
| | | of the world) |
| 3 | 0 | EU countries 6GHz BT disable |
| | 1 | 6GHz BT allowed in the EU countries (enabled only |
| | | if the device is certified to the EU countries) |
| 4 | 0 | South Korea 6GHz BT disable |
| | 1 | 6GHz BT allowed in the South Korea (enabled only |
| | | if the device is certified to the South Korea) |
| 5 | 0 | Brazil 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Brazil (enabled only if |
| | | the device is certified to the Brazil) |
| 6 | 0 | Chile 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Chile (enabled only if the |
| | | device is certified to the Chile) |
| 7 | 0 | Japan 6GHz BT disable |
| | 1 | 6GHz BT allowed in Japan (enabled only if the |
| | | device is certified to Japan) |
| 8 | 0 | Canada 6GHz BT disable |
| | 1 | 6GHz BT allowed in Canada (enabled only if the |
| | | device is certified to Canada) |
| 9 | 0 | Morocco 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Morocco (enabled only if |
| | | the device is certified to the Morocco) |
| 10 | 0 | Mongolia 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Mongolia (enabled only if |
| | | the device is certified to the Mongolia) |
| 11 | 0 | Malaysia 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Malaysia (enabled only if |
| | | the device is certified to the Malaysia) |
| 31:12 | 0 | Reserved Should set to zeros |
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BUCS method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e231
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This feature provides ability to provide Bluetooth Bands Selection
Mode. The bluetooth bands selection mode is defined as follow:
| Bit | Band GHz | Value | Description | Default |
|------+----------+-------+----------------------+---------|
| 0 | 2.4GHz | 0 | Controlled by NIC | 0 |
| | | 1 | Force disable 2.4GHz | |
| 1 | 5.2GHz | 0 | Controlled by NIC | 0 |
| | | 1 | Force disable 5.2GHz | |
| 2 | 5.8GHz | 0 | Controlled by NIC | 0 |
| | | 1 | Force disable 5.8GHz | |
| 3 | 6.2GHz | 0 | Controlled by NIC | 0 |
| | | 1 | Force disable 6.2GHz | |
| 31:4 | Reserved | | NA | 0 |
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BBSM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e230
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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This feature provides ability to provide dual chain setting.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BDCM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e220
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84943
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
This feature provides ability to identify non-LTE platform and disable
BiQuad Bypass filter logic in hardware for Bluetooth usecases reducing
device power consumption.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BBFB method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e213
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The ACPI BPAG method provide information to controls the antenna gain
method to be used per country.
The antenna gain mode is a bit field (0 - disabled, 1 -enabled)
defined as follow:
- Bit 0 - Antenna gain in EU
- Bit 1 - Antenna gain in China Mainland
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BPAG method is added to the bluetooth companion device and return
the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e210
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Pass SD card detect GPIO to payloads for SD card detection.
BUG=b:317009620
TEST=build pass
Change-Id: I1901fd45833f2415c61b61f9e04ebb54440df80a
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85250
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Frost Creek CRB is a reference platform for Intel Atom P5300 and
P5700 (known as Snow Ridge NS and Snow Ridge NX) SoC.
Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83322
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds support for Intel Atom Processors P5300, P5700
product families (known as Snow Ridge NS and Snow Ridge NX).
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
|
|
Add a helper function to get the mem_chip_info entry size.
Change-Id: Ibf2a2006fb3e7772688b80807589e8f2d64d1147
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
The RAPL PL1 limit and MMIO PL1 max values should be set as per
silicon TDP as specified in the PDG doc#646929.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.
Output with 15W silicon as below:
cd /sys/class/powercap/
cat intel-rapl/intel-rapl\:0/constraint_0_max_power_uw
15000000
cat intel-rapl/intel-rapl\:0/constraint_0_power_limit_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_max_power_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_power_limit_uw
15000000
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85184
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Update the TSR1 target's source to CHARGER in Passive Policy.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified the source for TSR1 is updated to Charger in Passive Policy
Change-Id: I43db616fd48fc4659dcba359f17854e14adb6039
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Configure GPIOs according to schematics revision 20241120.
BUG=b:379797598
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I4e9e81af9c3d8807e65ecd552e73305c1d109a2d
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85234
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
|
|
Create the uldrenite variant of the brya reference board
by copying the template files to a new directory named
for the variant.
BUG=b:376781355
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ULDRENITE
Change-Id: Ife666c6f2fe69643033e2ce3b299e7414e16eef1
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85207
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change IPU name to 4 characters: IPU0
While the ACPI device name is 'IPU', some part of generated SSDT looks
for 'IPU_', since by convention, the names less than 4 characters is
padded with underscope ("_"). Please see APCI spec 5.3 ACPI Namespace.
BUG=none
TEST=Boot fatcat board to OS and check that IPU device name is IPU0 in
the SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I60ce2998cb1d97589c0f7544ce8dc92c12a2b8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85274
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit c89ccaf2816a781ae0acb997557aed7d8cf10b7c.
Reason for revert: b:378775630#comment11
Intel believes that the AC only issue should be addressed head-on and
the previous power limit default settings should be maintained.
BUG=b:378775630
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9f8344288a1811bddce702c16a244e3d4a59f195
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85276
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The CSE sync in the payload would allow CrOS devices to render the user notification when updating. Currently, CrOS devices typically take 8-20 seconds to do a CSE sync.
BUG=b:380220737
TEST=Able to build and boot google/fatcat.
Change-Id: I8f1dd2e153ed0f1e671699002cf34a58d758ce2f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85233
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add entries in overridetree.cb required for exposing fan control via
ACPI, which is used then by acpi-fan driver in Linux kernel. This
includes:
1. Fan duty-cycle/rpm table. The RPM numbers were adjusted to the values
reported by ACPI on different duty cycle levels.
2. Dummy Active DPTF policy. This is required to mark the TFNx devices
as active and therefore let the acpi-fan driver probe.
BUG=b:358089775
TEST=Build and flash on redrix and check /sys/class/thermal for TFN1
Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935
Signed-off-by: Stanislaw Kardach <skardach@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85175
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add a variant specific S0ix hook to fill the SSDT table to disable and
enable camera during suspend and resume respectively. For safety concern,
our client LENOVO want us to follow the Boten project to create the function.
BUG=b:378525209
TEST=Build Pujjoga BIOS image. Ensure that camera is disabled during
suspend and enabled during resume. Do the powerd_dbus_suspend and
measure the camera power 3.3V which is disable. And resume will recover.
Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85133
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow latest schematics MB_SCH_1102A to add the DQ map.
BUG=b:372395010
TEST=emerge-fatcat coreboot
Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
Change the ram_id to 1 for MT62F2G32D4DS-020 WT:F based on the
hardware schematic MB_SCH_1102A.
BUG=b:372395010
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85206
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This commit enables the UFS controller on the Google Fatcat mainboard
based on FW_CONFIG.
This change allows the system to utilize the UFS storage device.
TEST=Built google/fatcat with UFS enabled.
Change-Id: Ib32523e7865b2ea23d990b2cf9b7406a4d6ecde3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85192
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch adds a Kconfig option to enable the UFS controller for
mainboards using the Intel Panther Lake-UH SoC.
By default, the UFS controller is disabled as it is not supported by
other SoC configurations. This prevents accidental enabling of the
UFS controller on unsupported platforms.
BUG=b:379828045
TEST=Built google/fatcat with and without UFS enabled.
Change-Id: Ica89ae85582367809128fc6cf0cd5fe5d40a2235
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85191
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change introduces Kconfig guards around the UFS workaround code
in the common ACPI ASL file. This ensures that these workarounds are
only applied when necessary, allowing future SoCs with UFS controllers
to reuse the common ASL file without modification.
By using Kconfig, we can enable or disable the workarounds based on
the specific SoC configuration, providing greater flexibility and
maintainability.
BUG=b:379828045
TEST=Able to compile google/fatcat.
Change-Id: I968b8811e508378a36648bd8234ff0fd7237b00d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85208
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:346600091
TEST=Compilation successful
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e225
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Enum is useful for improving readability because of the meaningful enum
names. Names such as "FREQ_260MHZ = 260", however, don't provide any
extra information of the value itself. Therefore, rename those enums to
PMIF_TARGET_FREQ_MHZ to better reflect its usage.
Change-Id: I420b909a76973a040b96feb2bcb93d3640b086b5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85204
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Rename the arguments of pmif_ulposc_check() and pmif_ulposc_cali()
to make the frequency unit clearer.
Change-Id: I7719fd4dc43edd47bf014af13fb57ad38f43778c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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X2F-N100 is an embedded device/firewall with Intel N100 SoC and
4x 2.5Gb Intel I226-V NICs.
Currently tested and working:
- Payload (EDK2)
- Suspend (S3 state)
- All USB ports
- 4x NICs
- M.2 NVME
- mPCI-E (WiFi/modem)
- 4G USB modem in mPCI-E slot
- PCI-E passtrough to VMs (NICs)
- HDMI/DP output + HDA audio
OS:
- Alpine Linux
- Windows 11 Pro (from USB)
Untested, looks sane:
- Internal USB port on M.2 slot marked as "5G_USB"
Broken/TODO:
- SATA EDK2 reports "Unsupported", drive's not detected.
- Suspend in Windows (statements dreamed up by the utterly deranged)
Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
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Found on tiny firewall appliance from Chinese company named "Topton"
with Intel N100 SoC. This system is fanless so all we need is the
ability to use serial output (RS232 in RJ45 form-factor, called
"Cisco-style" at address 0x3f8), which is working.
Change-Id: I9c27f52785d294a6f7c315b8df47d4dd5b389414
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Add initialization of DPM drvier for DRAM low power mode. This DPM flow
adds 3ms to the boot time, making the total boot time 860ms.
coreboot logs:
CBFS: Found 'dpm.dm' @0x19880 size 0x5b7 in mcache @0xfffdd1fc
mtk_init_mcu: Loaded (and reset) dpm.dm in 0 msecs (1888 bytes)
CBFS: Found 'dpm.pm' @0x19ec0 size 0x7fb5 in mcache @0xfffdd258
mtk_init_mcu: Loaded (and reset) dpm.pm in 3 msecs (43844 bytes)
TEST=Build pass. Check with cbmem -1.
BUG=b:317009620
Change-Id: Ib855e133a30067fc89c88d5c0fb454cc78504ff3
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85122
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we need implement a new DPM loader (said version 2) to run
the blob. Considering the version iteration, rename the original dpm to
dpm_v1.
TEST=Build pass.
BUG=b:317009620
Change-Id: I07afb8f5c23e96aad3c6cb0887cb7efd16ebf296
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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Add version two of the DPM driver for DVFS and DRAM low power feature.
MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we implement a new DPM loader (said version 2) to run the
blob. The new DPM driver includes following features.
- Simplify the DPM loading flow without the needs of waking DPM SRAM up
and initializing bootargs.
- Use the broadcast function to ensure that the DPM load and reset
operations performed on channel A will be synchronized to the other
three channels.
TEST=Full calibration pass.
BUG=b:317009620
Change-Id: I77e1ac252b00ab9c4864cc308f20da4a79714e4c
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85121
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 0)
DRAM-K:
Fast calibration passed in 1119 msecs
TEST=Full calibration pass.
BUG=b:317009620
Change-Id: Ibb18675caa11a828d27860eeab48c49acf6b938d
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85120
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Set DRAMC_PARAM_HEADER_VERSION to 3 for aligning with DRAM blob.
Test=Bootup pass
BUG=b:317009620
Change-Id: I17062bc3b79f60552981d7c604bb5350d8f6199f
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85119
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Commit 755ecc259c42 ("nb/via/cx700: Implement raminit") is missing an
include for static.h and breaks the main branch. Fix it.
Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85232
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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1. Add DB_HDMI_LTE 5 on DB_USB fw_config .
2. Due to refer Nivviks, used GPP_A20/GPP_E20/GPP_E21 as default
to set for NF1. Moreover, set to disable HDMI to NC when
fw_config not for DB_HDMI_LTE.
3. Set related DB_USB fields to probe correct devices.
BUG=b:369509276
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ic5e3b596ff3681f79f31c262e9e59d163e471e3c
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Change-Id: I1268a8f886ff395ff822b14a5427a5031260c541
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83389
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's a slow CPU.
Change-Id: I0bf75f410c1d9134f05a2d11b8d011499a7cf794
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82772
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icba7586145fbfd859d738ecd7a407739a7024ebb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82771
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This brings the old raminit implementation for CX700 back. It was
removed in commit e99f0390b9b8 (Remove VIA CX700 northbridge sup-
port). The code is mostly unchanged, three minor issues are fixed:
* A shift (>>= 2) was missing when reading tRRD from SPD byte 28.
The fixed value matches what the vendor BIOS of a VIA EPIA-EX
board programs. The code also suggests that we are looking for
a small value (<= 19 for DDR2-533).
* We allow the board port to specify which clock outputs should
be enabled now. This is necessary for the VIA EPIA-EX, which
needs the ALL_MCLKO setting (instead of the previously hard-
coded MCLKO2.
* When programming the DQS output delays, we considered the 1~2
rank values only for single-rank configurations. Changing the
`< 2` to `<= 2` brings us closer to the vendor values on the
VIA EPIA-EX.
Otherwise a lot of cosmetics changed. Partly because the original
code was to be #included into another C file, but also to satisfy
checkpatch. Also, all the #if'd code was removed (32-bit width
option, ECC, etc.).
Change-Id: Ibc36b4f314cdf47f18c8be0fcb98218c50938e94
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This northbridge provides a lot of knobs for fine-grained tuning of the
FSB drivers. The programming manual calls this "Host AGTL+ I/O Driving
Control". We program the known good values for use with a VIA C7 CPU,
and warn about use with different CPUs.
The numbers were pulled out of raminit of the original CX700 port.
Originally, there was a write to 0x83 as well, to set bit 1 which
triggers a soft reset of the CPU. It was amidst a table, so it
seems unclear if it was put there intentionally.
Change-Id: I24ba6cfaab2ca3069952a6c399a065caea7b49f2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disable a timer (GP3) that is always running by default. And enable
SMBus, which is useful this early as a console. The SMBus controller
is mostly compatible to the Intel one.
Change-Id: I77f179433b280d67860fc495605b5764ed081a6c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Drop duplicated fields
- Drop fields filled with constant values
- Drop SRAT prefix for sysmemmap entries
- Print all zeros when concatenating two hex numbers
Change-Id: I379aeb6fcd2e28665c7d592b0639db3c1b4caa9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85189
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The power limit parameters were defined for 378775630#comment5
by the power team.
BUG=b:378775630
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I069869fa01dc157cf2544e72468f43ce1bb64035
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85209
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
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Add RAM ID for DDR MICRON MT62F1G32D2DS-023 WT:B
BUG=b:378821948
BRANCH=None
TEST=boot to kernel success
Change-Id: I22e00cffaf6007c64d0c9ffa5f5dde528e3d8952
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Remove "include <bootstate.h>" when it is not used.
Change-Id: Ic27acf9f8dfbbccb8f48a139032b1463e7185030
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85216
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Add initial board commit based on HP 8200 SFF and HP Z220 SFF.
* Add documentation.
Tested on HP 8300 SFF.
Change-Id: Ib5322acc0210f000b53954e2925549358f86d5c8
Signed-off-by: Michał Zieliński <michal.zielinski@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67666
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
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Only advertise C-state C1 and C6.
TEST: On ocp/tiogapass Linux no longer complains about advertised
but unsupported C-states.
Change-Id: I184c337478f97e2d36f6e89b764dbe1da1b91697
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85190
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix ISCLK register definitions
Reference: 813032 - Panther Lake H I/O Registers
BUG=b:357011633
TEST=check camera functionality on fatcat
Change-Id: Ie9f1f639970344eb359dee37914ee26a02dcfb4b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85058
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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This patch updates Kconfig that selects ME specification version for
Pantherlake SoC from version 18 to version 21.
BUG=b:362647201
TEST=Able to build fatcat with SOC_INTEL_COMMON_ME_SPEC_21 selected.
Change-Id: Ibfebd7c093240aa7f1d6337f3e4dd6e5d34bed1d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85187
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch introduces Kconfig support for Intel's Management Engine
(ME), version 21. When 'SOC_INTEL_COMMON_BLOCK_ME_SPEC_21' is selected
it sets the ME_SPEC configuration to 18 because ME version 21 is
compatible with version 18 in terms of Host Firmware status registers.
BUG=b:362647201
TEST=Able to build fatcat after selecting SOC_INTEL_COMMON_ME_SPEC_21
Change-Id: I90c946751ac530dac1af4ff9c3c921b5faf82448
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add const qualifier for input of dev_is_active_bridge so that
dev_is_active_bridge could be used for both struct device * input
and const struct device * input.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ia4231534c87cd13d4e6e4d606733f9eb11221ac1
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This patch enables coreboot to perform CPU feature programming for both
the Boot Strap Processor (BSP) and Application Processors (APs) on
Intel Panther Lake platforms.
This change eliminates the need for the following FSP modules:
- CpuMpPpi
- CpuFeature
By handling CPU feature programming within coreboot, we reduce reliance
on external FSP binaries and improve code maintainability.
BUG=b:376092389, b/364822529
TEST=Built and booted google/fatcat successfully. Verified CPU features
are correctly programmed.
Change-Id: I73321485327f6a02ec8338fcfa1faf1e71008ba6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Create the felino variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:379797598
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FELINO
2. Run part_id_gen tool without any errors
Change-Id: Iff7989c19e775d65d5fb04aa4489854150390a35
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85185
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Walk the devicetree to collect all PCI IOAPICs. When found read
the IOAPIC base address from hardware.
TEST: On ocp/tiogapass all IOAPICs are found and advertised.
Change-Id: I2835c202e56849655795b96bc83862cb18e83fc0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84851
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPX uses the same PCU IDs as SKX.
Change-Id: I1bc96232e120b9cd9cb4f5b7b5df7d7db62fcbc4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84852
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On 1st and 2nd gen Xeon-SP the VTD PCI device is not at DEVFN 0.0.
Fix the DEVFN address and thus fix an assertion in vtd_probe_bar_size().
Change-Id: Ie879e95436af92fca1fee49135938ca2b005d579
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Drop DMAR_X2APIC_OPT_OUT since coreboot is able to enable X2APIC.
TEST: Works fine on OCP/tiogapass, thus drop the opt out.
Change-Id: Ia0443a39a9bf392976cfd1a7ccf6a335d5f0bd70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Set _PXM in ACPI to indicate which socket the PCI domain belongs to.
TEST: Booted on 2S ocp/tiogapass and checked dmesg that PCI domains are
advertised in the correct Proximity Domain.
Change-Id: I39cec0307b0dce0a4da5df5be5095b8d90758997
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Enable GBE and 10GBE region since it's used on vendor firmware.
TEST: Able to include gbe.bin and 10gbe.bin blobs into ROM.
Change-Id: Ia868d6b42e5e557d2abd60be4b2f318a1313b039
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85171
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently coreboot hardcodes the same IOAPIC IDs as used on UEFI native,
however FSP does not program the IOAPIC IDs, except for PCH IOAPIC.
Drop existing code that hardcodes PCI addresses and IOAPIC IDs and
detect the IOAPIC inside the domain automatically, read the IOAPIC
base address and let existing code figure out the IOAPIC ID by reading
it back from HW.
Change-Id: I2543a46dcc4a98ec8629530ca87882a7106c9ed1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84850
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Drop soc_get_stack_for_port() and move a comment.
Change-Id: I9d7615b633b344783150b3e1f3d98634630ed354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84844
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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General Purpose Memory Range registers are only used if extended BIOS
region is enabled now, this patch wraps the related code with Kconfig
item `CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW`.
Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one
of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning
PIRQ for a given device and INT pin.
Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The current design has the emit_wifi_sar_acpi_structures() function
load and unload the SAR binary. Since DSM and Bluetooth SAR data
structures are used outside this function, they are being copied into
data structure located in the calling function stack. This overhead is
unnecessary as loading and unloading the SAR binary could be done by
the calling function.
In addition, we are about to add several Bluetooth related data
structures which, under the current design, would require to add even
more data structure copy operations.
BUG=b:346600091
TEST=Wifi/Bluetooth SAR ACPI tables are identical before and after
this commit
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e207
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change removes the GPIO configuration for Type C DP HPD, as the
Type C port does not require HPD setup.
BUG=b:366156678
TEST=Build and boot google/orisa. Test Type C port for external usb and
DisplayPort functionality.
Change-Id: I59ec5c19dbbd053bda25f4260321220524d785b3
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This change removes the GPIO configuration for Type C DP HPD, as the
Type C port does not require HPD setup.
BUG=b:366156678
TEST=Build and boot google/trulo. Test Type C port for external usb and
DisplayPort functionality.
Change-Id: Iad602c9a15c65d37a37d06d486843f45e341b6bc
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch calls `xhci_host_reset()` function to perform XHCI
controller reset. This is proactively pulled in to avoid any potential
timeouts when PMC sends an IPC command to disconnect the active USB
ports.
BUG=b:364158487
TEST=Build Brox BIOS image and boot to OS. Perform warm reset, cold
reset and suspend/resume cycle.
Change-Id: I33fd3aa13e81c7b1ae1ebf6674cc8ac1437ecc03
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
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Remove <assert.h> when it is not used.
Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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