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2012-12-14libpayload: Initial ARMv7 portStefan Reinauer
This compiles, but it's not tested yet. Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2035 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14libpayload: rename i386 to x86Stefan Reinauer
Change-Id: Ia9170bd3d04e76dbf9321ca7ea4be23b5e468d21 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2033 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-14Fix broken scan-buildMartin Roth
Adding support for the multiple architectures broke the scan-build option. The new CC setting needed to be wrapped and not run again when doing the scan-build second pass. Change-Id: Ieb418f51d44803308040926a4154fb5fdc3ba67f Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2031 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-14AMD S3: Rename generated s3.rom for make cleanZheng Bao
Add prefix coreboot_ to let make clean find it and delete it. Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2029 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-14cbfstool: Align the column of build hint message.Zheng Bao
Change-Id: Ic217450411d7fa4e6c3a053be62d7c948dc7145e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2030 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-13coreinfo: Build libpayload from coreinfo makefileMarc Jones
Build libpayload and install it in the coreinfo directory. Allows coreinfo to be built with a single make command. Change-Id: I56982265555aae16e482b0a0040989c1f5317423 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1995 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-13libpayload: increase the default heap sizeDave Frodin
Coreinfo uses the default heap size and will blow up if the USB keyboard is used. Change-Id: I2ffae330ec34167b2ccfbd4c428e3e8306230f44 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12coreinfo: changes to get the USB keyboard workingDave Frodin
A call to usb_initialize() was needed. Also needed to set several curses flags. One to prevent keystrokes echoing to the display, and one to allow extended keystrokes (like the KEY_F(n)) to be seen when calling getch(); Change-Id: I495b42055a54603e4efb92b2845051434d88432d Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12SB800: Add IMC ROM and fan control.Martin Roth
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800 platforms. - Allows user to add the IMC rom to the build and to configure the location of the "signature" between the allowed positions. - Allows for no fan control, manual setup of SB800 Fan registers, or setup of the IMC fan configuration registers. - Register configuration is done through devicetree.cb. No files need to be added for new platform configuration. - Initial setup is for Persimmon, but may be extended to any cimx/sb800 platform. Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Rename generated hudson_romsig.bin for make cleanMartin Roth
The file generated when the IMC or XHCI binaries are included in the rom was named $(obj)/hudson_romsig.bin. The problem with this is that it doesn't get deleted when the user does a make clean. changing the name to coreboot_hudson_romsig.bin makes this happen. Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1978 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Fix SPI BAR special case in lpc_set_resourcesMartin Roth
There was already a special case for the SPI base address in lpc_set_resources for southbridge/amd/cimx/sb800 and southbridge/amd/agesa/hudson, but it needed to be modified to keep from killing the IMC rom during initialization. As soon as the BAR is disabled by setting the new base address, the IMC dies. The fix is to make sure it's still enabled when setting the new base address instead of setting the new address then re-enabling it. Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER to more accurately describe what we're using. Change-Id: I216d75b722c4332c239d487111a9880eabf59e91 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1975 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Claim the SPI bus before writes if the IMC ROM is presentMartin Roth
The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-12cbfstool: Catch failing parse_elf_to_payload()Stefan Reinauer
Otherwise cbfstool will segfault if you try to add an x86 payload to an ARM image. Change-Id: Ie468005ce9325a4f17c4f206c59f48e39d9338df Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2028 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Fix ARMv7 payload handlingStefan Reinauer
cbfstool was called with the wrong parameters Change-Id: I405d0fd7c84b46da3c98a36fd19ef0034dc175cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2022 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Fix maxim max77686 driverStefan Reinauer
With driver-y going away, the current driver code didn't get compiled in with upstream. Change-Id: I9bff45a35c995888a482bdc22a1573f6bfb88211 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2027 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add support for Google Parrot ChromebookStefan Reinauer
AKA Acer C7 Chromebook See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html for more information. Thank you to Sage Electronic Engineering, LLC for making this possible! http://www.se-eng.com/ Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2026 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Update 3rdparty to it's HEADStefan Reinauer
Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2025 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add support for ENE932 EC w/ Compal firmwareStefan Reinauer
Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2024 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12Add minimal mainboard support for snowRonald G. Minnich
This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2018 Tested-by: build bot (Jenkins)
2012-12-12Fix UART8250 console prototypesStefan Reinauer
and disable IO mapped UARTs on ARMV7 per default Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2021 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-12Fix up Maxim MAX77686 driverStefan Reinauer
... to fit into the naming convention Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2020 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-11Remove un-needed i2c.h includeRonald G. Minnich
When we need i2c for this cpu we will use the coreboot smbus code. Change-Id: I4ba4cc9ae10e5ca830d621ee9c8d9f7bd2129e2f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-11Correct the location of the include fileRonald G. Minnich
The max include file is in src/drivers/power. Change-Id: I2e663b472cade17fc50edbb449c0e54fd4a991eb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2017 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-10Removed an unneeded include fileRonald G. Minnich
This file builds fine without including arch/types.h Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Icd38cf429576a2a1a33ebca84389526feddfc169 Reviewed-on: http://review.coreboot.org/2015 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-10libpayload: Fix use of virtual pointers in sysinfoNico Huber
In I4c456f5, I falsely identified struct cb_string.string as a pointer which it is not. So we don't need phys_to_virt() here. Change-Id: I3e2b6226ae2b0672dfc6e0fa4f6990e14e1b7089 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1987 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-10libpayload: Fix renaming of REG_CLASS_DEV to REG_SUBCLASSNico Huber
REG_CLASS_DEV was renamed to REG_SUBCLASS. Change-Id: I4af476b953b544f680337d815889564f016563eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-09Revert "armv7: use __cpu_to_le32 for endianness of reset vector instruction"Stefan Reinauer
This reverts commit 67ce04ea9a9c7e30dd96b9f36a938b51655e8a44 Change-Id: I2781c9275c03bcabf0211e1b6cd1aa8f13005ae0 Reviewed-on: http://review.coreboot.org/2014 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08crossgcc: Normalize library directoriesPatrick Georgi
Various of the build scripts used upstream can't cope with multilib library paths (eg. lib64), so move things to a place where they can find them, if such paths are used. Change-Id: I0dd9bba9a9eadd92d8704157e868fb37c715ee91 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2013 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08coreinfo: Make better calls to libpayload build scriptsMarc Jones
Set LPGCC and LPAS so that CC and AS are maintained. Clean up the makefile order to check for .config to be easier to read. Use objcopy instead of strip and keep the debug symbols file. Change-Id: I95d6b7a0e3a99a142d3fd6e2ecc61de1d4412402 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1994 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08Clean up libpayload lpgcc and lpas scripts.Marc Jones
lpgcc and lpas are called by payload Makefiles to properly build and link with libpayload. Made lpas use the proper crosscompile AS, as lpgcc does with CC. Added V=1 support to help users debug the build. Fix basename $CC and $AS expansion. Change-Id: Ia4dc8ba53ba7565521a79f1520155f3307b09f85 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1993 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08stddef.h: move to generic codeStefan Reinauer
stddef.h should be fairly generic across all platforms we'd want to support, so let's move it to generic code. Change-Id: I580c9c9b54f62fadd9ea97115933e16ea0b13ada Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2007 Tested-by: build bot (Jenkins)
2012-12-08WIP: Initial ARMv7 architecture implementation in corebootStefan Reinauer
The first ARMv7 CPU we're going to support is the Exynos 5250 used in the Google Snow ChromeBook. Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2004 Tested-by: build bot (Jenkins)
2012-12-08WIP: Add support for non-8250 built-in UARTsStefan Reinauer
Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08cbfs_core.h: support for ARMv7 CBFS master headerStefan Reinauer
Change-Id: I59626200b4a92d90b46625f8dcc2ed28e6376e46 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2008 Tested-by: build bot (Jenkins)
2012-12-08WIP: Initial support for Samsung Exynos 5250 ARM CPUStefan Reinauer
Samsung SoC files, including Exynos5 (a Cortex-A15 implementation). Since this is an SoC we'll forego the x86-style {north,south}bridge and cpu distinction. We may try to split some stuff out before the final version if prudent. Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2005 Tested-by: build bot (Jenkins)
2012-12-08Limit SPI device debug prints with CONFIG_DEBUG_SPI_FLASHMarc Jones
Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH, which would cause long delays durring boot when SPI devices were written. Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1965 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08Fix Yabel compilation on non-x86 platformsStefan Reinauer
Mostly preventing inb/outb being used on non-x86 Change-Id: I0434df4ce477c262337672867dc6ce398ff95279 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08Only include libgcc wrappers on x86Stefan Reinauer
ARM does not need them, and they're causing trouble Change-Id: I6c70a52c68fdcdbf211217d30c96e1c2877c7f90 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2009 Tested-by: build bot (Jenkins)
2012-12-08Makefile cosmeticsStefan Reinauer
align architectures Change-Id: Ie3fe29d830d45e76c183411c04598e82b4b3a010 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2003 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-08Allow PCI option rom execution only on systems with PCI supportStefan Reinauer
... on all other systems it will fail terribly ;-) Change-Id: I7f8d10b71b2dbc798b28aee7c36872685c793fd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2001 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-08abuild: Select correct cross compiler for ARMV7 architectureStefan Reinauer
Change-Id: Ia0dce25a4271299757654ba46baafe6a6673c6d2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2000 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2012-12-08buildgcc: Clean up PATH handlingStefan Reinauer
This puts our installed binaries first in the search path, which is what we really want. ... and remove some dead code Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I91725af6b0fc486bd943d8e25cdce8d3e2503b3c Reviewed-on: http://review.coreboot.org/1998 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-08buildgcc: drop hack to build gcc trunk versionsStefan Reinauer
The focus of the script is to create a supported cross toolchain, and with GOLD and LTO being released features, we don't need this anymore. Change-Id: Ieb7752ce6e143d93414aba5887190f853cbd5a4b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1997 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-07buildgcc: Remove mingw32 hacksPatrick Georgi
After patching them to be more flexible, an even better approach was found: With this change libgcc isn't built at all on mingw32 platforms, so the system headers aren't necessary anymore. Now x86_64-pc-mingw32 builds, too. Change-Id: Ic1406588669d87aee1bcf40ff67af77f2a6ac283 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Raymond Danks <ray.danks@se-eng.com>
2012-12-07abuild: produce valid junit filesStefan Reinauer
If no valid cross compiler is found, the junit file produced by abuild is invalid, missing the closing </testcase> tag. This breaks proper reporting in Jenkins of our ARM board at this moment. Change-Id: I94bfc7f334d33ceeb53451a7c5125058c1f33bd4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1992 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2012-12-07coreinfo: change the foreground/background colorsDave Frodin
The default curses library changed from tinycurses to PDCurses. PDCurses fails to fill the entire active screen with the assigned background colors when it writes 'blank' chars. This will allow the menues to look better until I resolve that. Change-Id: I70b5331d16dd0abaa1f0b02b725571844b7ac15e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-07Add function to map vendor/device to generic VBIOS IDsDave Frodin
Change-Id: I4d7c4ec2b91c97eacf96770c150c2b9a61309053 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-07libpayload: Don't let USB/PC/serial keyboards overwrite each otherDave Frodin
Change-Id: I75c0066cf737e0cecac056487215622e2b3d4467 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-07armv7: use __cpu_to_le32 for endianness of reset vector instructionDavid Hendricks
Change-Id: Ic8f35d7172f6afa933c24774177ed65e6dc579a0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1979 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06Disable CMOS_POST and IO_POST on non-PC80 systemsStefan Reinauer
Because they use outb instructions, they are bound to fail on non-PC80 systems like ARM. Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1974 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2012-12-06crossgcc: Generalize matching for the mingw casePatrick Georgi
With this change, i686-pc-mingw32 is acceptable, too. Change-Id: I924f7ece84e77dc751e5e0318bac1ebc72d39d21 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1972 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-06Unify assembler function handlingStefan Reinauer
Instead of adding regparm(0) to each assembler function called by coreboot, add an asmlinkage macro (like the Linux kernel does) that can be different per architecture (and that is empty on ARM right now) Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1973 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06driver/spi: Add support of MX25L3235DZheng Bao
Tested on Thatcher. Change-Id: I648171ba0d03be1e984c182f6d0f082241e3f51c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06Fix xcompile (again)Stefan Reinauer
After cherry-picking change 1679 it became apparent that there was a small typo in my last xcompile change. With this patch applied, I can now compile the first few files in the tree before GCC dies with In file included from src/arch/armv7/lib/romstage_console.c:23:0: src/include/uart.h:31:6: error: redundant redeclaration of 'uart_init' [-Werror=redundant-decls] Now for some fun... Change-Id: Idbb07f609e4a240238964cc16714639f5ef09914 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1970 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-06Fix xcompile for ARMv7 and our cross toolchainStefan Reinauer
The naming of architectures is highly inconsistent between the different components of the toolchain. In binutils, the file architecture is elf32-littlearch. In GCC it's armv7a-eabi. This patch adds support for different BFD / GCC names Change-Id: Ib644f71e8d8b4964adec73eed23921d3838e8aa7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1969 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-06Drop ARCH_ARM in favor of ARCH_ARMV7Stefan Reinauer
The ARM architecture is really many architectures, and most of them need their own toolchain. After discussing with Ron and David, we decided that we're going to call the architecture of our ARM board armv7.. This patch cleans out the remainders of ARCH_ARM in the tree and moves on to consistent ARMv7 naming. As of now, we only support little endian ARMv7 CPUs. We can fix that for big endian if/when it comes our way. Change-Id: Id70c7ef615f600e4d09961d811e7ac974fce4811 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1968 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06crossgcc: Fix buildgcc on Mac OS XStefan Reinauer
Once again, the compiler we use on Mac OS X had trouble compiling GCC. Switch to llvm-gcc because that one works with Xcode 4.5.2 and gcc 4.7.2. Also drop the -W flags not known to Xcode from the iasl Makefile, and drop the --remove-destination option from the copy, because that does not exist on Darwin. Change-Id: I9f978f65b5ae7edee2ecdcab337772e7a692bd9b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1967 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-05Conditionally include mc146818rtc in console.cDavid Hendricks
get_option() is used to get a config option (debug loglevel) from CMOS. However, not all machines have CMOS, so define a dummy inline function that will return an error code so the caller (console_init()) will use the default loglevel. Change-Id: I6adf371d79164178f40a83f7608289a6a7673357 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1962 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-05crossgcc: Add support for building armv7a toolchainStefan Reinauer
!#%$@ autotools don't support all the platforms gcc and binutils support. If you try to update to the latest autoconf, it will complain that you have to use the older one. If I had a penny for every time autotools broke portability... Change-Id: I479b6c5f64f1def8dca889884e6a2b0e2ffc1fb8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1966 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-01Drop TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I38ea2ed2be4d9240ec8cb6d5dc5b3cc578cdaefb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-01Add include files for samsung s5p-commonRonald G. Minnich
These are from u-boot but have been cleaned up somewhat to remove references to linux include files. Change-Id: I5fe3954a11d8c4aa792620ef5e1a5ee8932b8578 Signed-off-by: Hung-Ti Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1930 Tested-by: build bot (Jenkins)
2012-11-30Rename devices -> deviceStefan Reinauer
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Change TARGET_I386 to ARCH_X86David Hendricks
This renames TARGET_I386 to ARCH_X86 to make it more uniform with other parts of the codebase, e.g. cbfs_core.h from cbfstool. Change-Id: I1babcc941245ed1dde0478a21828766759373a42 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1961 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-11-30fix #if for target architecture in libpayloadDavid Hendricks
This bug was introduced when we copied cbfs_core.h from cbfsutil to libpayload. Change-Id: I9b5d00d0dbdb969644ce46ad6ac2a84b366b5cd7 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1958 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2012-11-30Drop boot directoryStefan Reinauer
It only has two files, move them to src/lib Change-Id: I17943db4c455aa3a934db1cf56e56e89c009679f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1959 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-30src/lib/Makefile.inc: Add license headerStefan Reinauer
Change-Id: If8bce4ebde9101ac9087fcbd43adc0e08c26352d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/1957 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Make set_boot_successful depend on PC80_SYSTEMStefan Reinauer
Set_boot_successful depends on CMOS parts that non-PC80 platforms do not have. For now, make the current path depend on CONFIG_PC80_SYSTEM, and make the alternative empty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I68cf63367c8054d09a7a22303e7c04fb35ad0153 Reviewed-on: http://review.coreboot.org/1954 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Only compile PC80 drivers when CONFIG_PC80_SYSTEM is setStefan Reinauer
Change-Id: Iac2f3ebf68c9c1df296fc81d10ee97053a9d5469 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1956 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30cbfstool: Clean up messagesStefan Reinauer
The output of cbfstool is a little inconsistent in some places. This patch fixes it. Change-Id: Ieb643cb769ebfa2a307bd286ae2c46f75ac5e1c1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1955 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30build system: Treat cmos.default as text filePatrick Georgi
It's a more easily maintainable format than a 128 byte binary blob Change-Id: Ic9b9f53cd025b5f89a21971930fabf6592f95d67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1867 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Supermicro h8scm: add agesa version of supermicroSiyuan Wang
Supermicro h8scm has a C32 CPU socket, the details of this board is: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support family 15 CPU, so we update this mainboard with this patch. This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation. If you want to change the frequency of memory, please edit the macros "BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT" in src/mainboard/supermicro/h8scm/buildOpts.c Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1510 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30AMD SB800: Interrupt routine for PCI slots on PersimmonZheng Bao
Set the correct device number in the pcie interrupt routine in ACPI asl. The device number is decided by which address pin is connected to IDSEL. Table 3-1: IDSEL Generation Primary Address AD[15::11] Secondary Address AD[31::16] 0 0000 0000 0000 0000 0001 0 0001 0000 0000 0000 0010 0 0010 0000 0000 0000 0100 0 0011 0000 0000 0000 1000 0 0100 0000 0000 0001 0000 0 0101 0000 0000 0010 0000 0 0110 0000 0000 0100 0000 0 0111 0000 0000 1000 0000 0 1000 0000 0001 0000 0000 0 1001 0000 0010 0000 0000 0 1010 0000 0100 0000 0000 0 1011 0000 1000 0000 0000 0 1100 0001 0000 0000 0000 0 1101 0010 0000 0000 0000 0 1110 0100 0000 0000 0000 0 1111 1000 0000 0000 0000 1 xxxx 0000 0000 0000 0000 On persimmon, PCI slot 0's IDSEL is connected to AD19, so the device number is 3. Slot 1's IDSEL is connected to AD20, so the device number is 4. Change-Id: Ic0fb7ac1c87ec306bf314e4d2b8c2bdc9031081b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30Persimmon: Disable the unused PCI clocksDave Frodin
Change-Id: I4b735fe4e6441f99236e43b34695fdac95b8888a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1875 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30AMD S3: Leverage the public SPI routineZheng Bao
Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30Create a a new configuration variable for PCIRonald G. Minnich
Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30libpayload: Remove unused FLAG_USED from memory allocatorNico Huber
The FLAG_USED bit in the memory allocator's header type was never read. This removes it to save one bit for the region size so we can have heaps of up to 32MiB. Change-Id: Ibd78e67d79e872d6df426516667c795fd52326d5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1942 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-30libpayload: Fix lookup by label in CMOS layoutsNico Huber
The condition to compare the labels was twisted. Change-Id: I34a665aa87e2ff0480eda0f249bbbea8a8fe68d8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-30Add mainboard hook to bootblockKyösti Mälkki
Change allows to override default bootblock_mainboard_init() with mainboard-specific code. If the default bootblock_mainboard_init() handler is replaced, with one from file BOOTBLOCK_MAINBOARD_INIT, one needs to take care the replacement calls all the necessary bootblock_x_init() functions. Change-Id: Ie8c667cdba7cafe9ed2d4b19ab2bd21d941ad4ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1845 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-30Refactor bootblock initialisationKyösti Mälkki
Makes it a bit easier to implement mainboard-specific behaviour while executing the bootblock. Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-30Add multi-architecture support to cbfstoolDavid Hendricks
This is an initial re-factoring of CBFS code to enable multiple architectures. To achieve a clean solution, an additional field describing the architecture has to be added to the master header. Hence we also increase the version number in the master header. Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1944 Tested-by: build bot (Jenkins)
2012-11-30Lumpy: Need byteorder.h in romstageStefan Reinauer
Not sure why this never triggered an error before. Change-Id: I85d8b3b862492df04163a5f751c7ea4288406860 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1946 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Make libgcc wrappers arch-specific, add ARMv7David Hendricks
Change-Id: Ia0bbd3bec6588219ce24951c0bcebefc6b6ec80e Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1940 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-30Add dummy Kconfig options for armv7David Hendricks
This adds a dummy config for ARMV7 for developing various follow-up patches which rely on ARCH_ARMV7. Change-Id: Id913054d916f41607d10ebc02aaf74082e14b554 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-29Add the maxim MAX77686 power controller.Ronald G. Minnich
Create a new directory in drivers for power controllers. Add the MAXIM MAX77686 power control support. Accessing this controller requires I2C support. Note that this will not build until the I2C usage is changed for coreboot. I'm putting it in mainly because we need it soon and I want to see if the new directory is acceptable. Change-Id: I6c2a6d2165f33b41d2c8e4813222b21d2385e879 Signed-off-by: David Hendricks <dhendrix@chromium.org> SIgned-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1938 Tested-by: build bot (Jenkins)
2012-11-29crossgcc: Only build iasl in acpica.Zheng Bao
Other acpica's modules are not needed. Change-Id: I16846caa922aded8db7c1d9e64c007fb2772ff98 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2012-11-29Drop empty mainboard.cKyösti Mälkki
Change-Id: Idcf9349d96297b8cb0ea1e68769e02659ac16ab8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Drop empty mainboard_opsKyösti Mälkki
Change-Id: I24866142eebcb8fdbc7e21f5b2f364a8d1b264b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Make mainboard_ops and mainboard.c file optionalKyösti Mälkki
This provides weak empty declaration for mainboard_ops. The struct chip_operations is not defined for __PRE_RAM__ so the declaration is also moved upwards in the output. Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1931 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29pirq_route_irqs is privatePatrick Georgi
Change-Id: I120913dac3150a72c2e66c74872ee00074ee0267 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Minor changes to .h files for samsung ARM partRonald G. Minnich
With these changes we have a mostly compiling target. I'm still removing and pruning .h files, but hopefully later today I'll do the last few .h commits and move on to .c Change-Id: Ia82d787496184e028f37d7b67336d61fda75aa94 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-28add .h files for common exynos 5Ronald G. Minnich
Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1926 Tested-by: build bot (Jenkins)
2012-11-28Add .h files for samsung exynos 5250Ronald G. Minnich
Per a conversation with Stefan, these chip-dependent files are moved to the src tree, in the manner of other chips (north and southbridge). Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Reviewed-on: http://review.coreboot.org/1925 Tested-by: build bot (Jenkins)
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Drop driver-y from GM45/ICH9/RK9Stefan Reinauer
This broke because those components were not yet committed when the patch to drop the driver class was made. Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Fix technexion tim5690 board VGA handlerStefan Reinauer
When dropping ramstage.a, unused functions with unresolved symbols are not silently dropped anymore. This makes the tim5690 compilation fail. This fix makes sure we don't compile in the int15 handler code when we don't set CONFIG_VGA_ROM_RUN Change-Id: If6872c983d9fd811eb33259421f94b551f3b9b34 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1929 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-27Enable the FCH GPP port prior to device enumerationDave Frodin
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1873 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Drop duplicate files that prevent building without ramstage.aStefan Reinauer
When dropping ramstage.a duplicate symbols in ramstage will start breaking the build. Hence drop all the duplicate functions implemented by mainboards that have those functions in generic or component code already. Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1865 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-27build system: Split linking into multiple stepsPatrick Georgi
After collecting dependencies for ramstage, add an intermediate step in which object files are linked per directory. The results are then linked into the final binary. This reduces the maximum command line length and might also help with future use of LTO linking. Also adapt the lint test for build dir handling, since printall doesn't provide individual object files for ramstage anymore. Change-Id: Ie40febd8c1eaf4609944eedeab46d870639e53df Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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