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2024-01-10sb/amd/pi/hudson: select HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held
Select HAVE_CONFIGURABLE_APMC_SMI_PORT and implement the pm_acpi_smi_cmd_port helper function. TEST=APU2 still compiles with HAVE_SMI_HANDLER selected and NO_SMM select removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f79d8c1d59aa1b6c1145dd0b1cbc9010a1c57e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10sb/amd/pi/hudson/smhandler: use common APM_CNT_ACPI_* definesFelix Held
The Hudson southbridge code for the AMD binaryPI SoCs had its own ACPI enable and disable APMC command numbers that didn't match the common defines in coreboot, so use the common define here to be consistent with the command numbers in the corresponding FADT fields. Since the only SoC that still would use this code doesn't select HAVE_SMI_HANDLER, this won't fix any observable bug, but better fix this before anyone possibly runs into this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e596071e1b5269b616b7a93151648cb86ae77bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10sb/amd/pi/hudson: drop unused ACPI_SMI_CMD_* definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf02d8bee70fd654b3e71d1ead6dc0414fb6de40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79847 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10sb/amd/pi/hudson: fix gpio.h and smi.h include locationFelix Held
This fixes the following compile error when trying to build the APU2 board with HAVE_SMI_HANDLER selected and the NO_SMM select removed: In file included from src/soc/amd/common/block/gpio/gpio.c:8: src/include/gpio.h:6:10: fatal error: soc/gpio.h: No such file or directory 6 | #include <soc/gpio.h> /* IWYU pragma: export */ | ^~~~~~~~~~~~ Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie06044b12f5cbcc55a2706ec566afd2eb294c62b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79846 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/amd: use apm_get_apmc() in APMC SMI handlerFelix Held
Instead of open-coding this functionality, call the apm_get_apmc() helper function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac6b614d900e51d91a0c155116a5edc29775ea99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10cpu/x86/smi_trigger: use enum cb_err as apm_control return typeFelix Held
Even though the return value from apm_control isn't checked at any of its call sites, using the cb_err enum instead of an integer as return type makes it clearer what the returned value means. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07ced74cae915df52a9d439835b84237d51fdd11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79835 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-10mb/google/cherry: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10mb/google/corsola: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/mediatek: Add common implementation to configure displayYidi Lin
The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/amd/glinda: Increase maximum CPU threads to 24Anand Vaikar
glinda SOC has 24 maximum CPU threads as per PPR documentation(#57254). TEST=Boot logs print the CPU initialization happens for 24 threads. Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-10mb/intel/mtlrvp: define a new config for Chrome ECDeepti Deshatty
Introduce new config MTL_CHROME_EC_SHARED_SPI, tailored for Chrome ECs utilizing an external shared SPI flash. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 Change-Id: I462c34c5adaefa37c652de293152243c58bad7c5 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-10mb/intel/mtlrvp: streamline Chrome EC configsDeepti Deshatty
Chrome EC configuration options that are common among various boards have been consolidated under the "BOARD_EXT_EC_SPECIFIC_OPTIONS" config. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79211 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-09Makefile.inc: Enable Wold-style-declaration command optionElyes Haouas
Warn for obsolescent usages, according to the C Standard, in a declaration. For example, warn if storage-class specifiers like static are not the first things in a declaration. Change-Id: Ida3fa59edb07e4105ef3cfb6a20cb29680699586 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71892 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-09soc/nvidia: Put static keyword at the beginning of declarationsFelix Singer
In order to comply with the more recent style of declarations, put the static keyword at the beginning. Fixes following GCC error when the related flag is set: error: 'static' is not at beginning of declaration [-Werror=old-style-declaration] Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79856 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-093rdparty/vboot: Update submodule to upstream mainFelix Singer
Updating from commit id 7c3b60bb: 2023-12-21 20:34:49 +0000 - (firmware/2lib: Use SSE2 to speed-up Montgomery multiplication) to commit id 32402941: 2024-01-08 19:53:43 +0000 - (treewide: Put the static keyword at the beginning of declarations) This brings in 4 new commits: 32402941 treewide: Put the static keyword at the beginning of declarations 242d198b crossystem: Use external tool the clear the TPM c8a0802f tests: Remove unnecessary vb2_verify_fw.c from TEST20_NAMES list 706088b8 tests: Test HW crypto RSA signature verification Change-Id: I667376dfc3021fa6d213e3d89917ee228fd14a28 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-09mb/ibm/sbp1: Set FSP loglevelPatrick Rudolph
Change-Id: Ia97dbda30f657f0b1568364d712eaea8d134b3b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79791 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-09mb/google/brox: Fix error in DDR DQS configShelley Chen
The DQS mapping for DIMM idx 6 was discovered to be incorrect to what was in the schematics. Correcting the mistake in this CL. BUG=b:311450057,b:300690448 BRANCH=None TEST=tested on device and it passed memory training Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2024-01-09soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integerSubrata Banik
This patch enforces consistent override handling for integer `SOC_PHYSICAL_ADDRESS_WIDTH` config Change-Id: Ib5bdfdb8c2689803c9d3c2bfd353609edae91ab3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-09drivers/mipi: Add support for IVO_T109NW41 panelRuihai Zhou
Add IVO_T109NW41 serializable data to CBFS. Datasheet: T109NW41 R0 Tentative Product Specification.docx BUG=b:319025360 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Id740e3a21f72bbcd6e5c2b56b31ac90f4990d475 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79844 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-08util/lint: Remove the extra `\` in lint-stable-003-whitespaceRuihai Zhou
A following error occurred when I commit, it seems that the extra `\` after `\.md$` is unnecessary. File Binary file src/mainboard/google/guybrush/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/skyrim/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/zork/data.apcb matches has lines ending with whitespace. test failed Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79782 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-08src/arch/x86/exit_car: Add proper x86_64 codePatrick Rudolph
Don't truncate upper bits in assembly code and thus allow loading of postcar stage above 4GiB. Tested on qemu with cbmem_top set to TOUUD. Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-08cpu/x86/smi_trigger: call pm_acpi_smi_cmd_port to get APMC SMI IO portFelix Held
Instead of hard-coding the APMC SMI command IO port in the FADT, call pm_acpi_smi_cmd_port() to get the APMC SMI command IO port. Also update the comment in apm_get_apmc to match what it's doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f36b8a0e93a82b8c6d23c5c5d8fbebb1bc6b0bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-08arch/x86/acpi: call pm_acpi_smi_cmd_port to get APMC SMI IO portFelix Held
Instead of hard-coding the APMC SMI command IO port in the FADT, call pm_acpi_smi_cmd_port() to get the APMC SMI command IO port. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I731c780bc6db7e7fd59688340bab1da86fc93c11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79565 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held
Introduce the HAVE_CONFIGURABLE_APMC_SMI_PORT Kconfig option that when not selected will result in a default implementation of pm_acpi_smi_cmd_port to be included in the build that returns APM_CNT. SoCs that provide their own pm_acpi_smi_cmd_port implementation, need to select this Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-08mb/google/nissa/var/craaskov: Implement touchscreen power sequencingrex_chou
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:317746281 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79764 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08util/ifdtool: Add support for extended region read/write accessReka Norman
Platforms from CNL onwards support up to 16 flash regions, not 12. The permissions for regions [15:12] are stored in extended region read/write access fields in the FLMSTR registers. Currently ifdtool treats these fields as reserved, so they're not modified when locking or unlocking. Add support for extended regions so that they are locked/unlocked by the --lock/--unlock options. This will make the locked/unlocked descriptors generated by ifdtool match those generated by mFIT. BUG=b:270275115 TEST=Without this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 ff 07 20 00 ff 05 40 00 ff 00 00 00 00 00 00 00 00000090 ff 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 00 ff ff ff 00 ff ff ff 00 ff ff ff 00 00 00 00 00000090 00 ff ff ff With this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff Change-Id: Iaa43524d91c399a996ade56f2f613b4110a44aad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-08nb/intel/gm45/raminit: Use read32p()Elyes Haouas
Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom remains identical. Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77971 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08drivers/mipi: Add support for BOE_NV110WUM_L60 panelRuihai Zhou
Add BOE_NV110WUM_L60 serializable data to CBFS. Datasheet: B5NV110WUM-L60 V5.0Product SpecificationRev.P0 BUG=b:308968270 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78956 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-07vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85Kulkarni, Srinivas
Update header files for FSP for Meteor Lake platform to version 3471_85, previous version being 3424_88. FSPM: 1. Add 'DisplayGpioPinMux' UPDs 2. Address offset changes BUG=b:318772151 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-06Documentation/getting_started: Add a FAQ documentMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: Ia324e4800bf9dfc7ad86f4f99272c87ac566304e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79441 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-06soc/rockchip/rk3399/mipi: Remove space before semicolonElyes Haouas
Change-Id: I7e02173c296689ef3143a1079658006ec91c4dc2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77156 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05mb/hp/z220_series: Rename to snb_ivb_desktopsRiku Viitanen
In preparation for adding other similar boards under it as variants. Tested that z220_cmt still builds. Change-Id: I96dec173e0d97d8564bad14778333b8231684ef8 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79434 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05soc/amd/picasso/Kconfig: select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFFFelix Held
Commit 850b6c6254ab ("soc/amd/picasso: add eMMC MMIO device to devicetree") broke both S3 resume on Morphius SKUs that use an NVMe SSD instead of an eMMC and boot on the currently out-of-tree ASRock X370 Killer SLI board. In the latter case, commenting out the power_off_aoac_device call inside the emmc_enable function fixed things. TEST=This fixes S3 resume on Morphius with NVMe SSD and an equivalent change discussed in the patch mentioned above that caused the regression also fixed boot on the ASRock board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Id976734c64efe7e0c3d8b073c8009849be291241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-05soc/amd/common/emmc: add Kconfig option to skip powering off eMMCFelix Held
Add a Kconfig option to skip powering off the eMMC controller via the AOAC block in the case where the eMMC controller is disabled in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0dbe819222972d9bf0789671b031ad83648e8917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79825 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05arch/x86/include/mode_switch: Add more wrapper functionsPatrick Rudolph
Add a protected mode wrapper function that takes three arguments. This is already supported by the called assembly code. Change-Id: Ia8c91eebae17e4ca27e391454c2d130a71c4c9f3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-05northbridge/intel/sandybridge: Enable x86_64 for mrc.binPatrick Rudolph
Enable x86_64 support for MRC.bin: - Add a wrapper function for console printing that calls into long mode to call native do_putchar - Remove Kconfig guard for x86_64 when MRC is being used Tested: Booted Lenovo X220 using mrc.bin under x86_64 and MRC is able to print to the console. Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-05cpu/x86/64bit/mode_switch2: The reverse function to mode_switchPatrick Rudolph
Add another mode_switch assembly function to call x86_64 code from x86_32 code. This is particullary useful for BLOBs like mrc.bin or FSP that calls back into coreboot. The user must first wrap all functions that are to be called from x86_32 using the macro prot2lm_wrapper. Instead of using the original function the wrapped functions must be passed to the x86_32 BLOBs. The assembly code assume that 0-3 32bit arguments are passed to the wrapped function. Tested: - Called x86_64 code from x86_32 code in qemu. - Booted Lenovo X220 using x86_32 MRC using x86_64 console. Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-05vendorcode/google/chromeos: Use unsigned int for "factory_config"Subrata Banik
This patch ensures `chromeos_get_factory_config()` returns an unsigned integer value because factory config represents bit-fields to determine the Chromebook Plus branding. Additionally, introduced safety measures to catch future "factory_config" bit-field exhaustion. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79769 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-05util/ifdtool: Add support for disabling GPR0Reka Norman
On ChromeOS devices with updateable CSE firmware, the GPR0 (Global Protected Range) register is used to ensure the CSE RO is write protected even when the FLMSTR-based protection is temporarily disabled by coreboot to allow updating the CSE RW. For more details see Documentation/soc/intel/cse_fw_update/cse_fw_update.md Therefore to allow modifying the CSE firmware from the CPU, the descriptor must have both the FLMSTR-based protection disabled (which can be done using ifdtool --unlock), and GPR0 disabled. Add an ifdtool option for disabling GPR0. For now I've added support for all platforms for which I have the SPI programming guide. Support for more platforms can be added in the future if needed. BUG=b:270275115 TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked craask image, check the GPR0 field is set to 0. Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04vboot: Add firmware PCR supportYi Chou
To verify the boot chain, we will need to extend the PCR with the firmware version. And the server will be able to attest the firmware version of devices. The "firmware version" here is the RW firmware anti-rollback version, determined by the ChromeOS's signing infra, and will be verified in vb2api_fw_phase3, by comparing it with the version stored in the TPM. This version will be increased when there is critical vulnerability in the RW firmware. According to [1], PCRs 8-15 usage is defined by Static OS. Therefore PCR_FW_VER is chosen to be within that range. Ideally the existing PCR_BOOT_MODE and PCR_HWID should also be allocated in the same range, but unfortunately it's too late to fix them. Because PCRs 11 and 13 have been used for other purposes in ChromeOS, here PCR_FW_VER is set to 10. [1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_05_3feb20.pdf BUG=b:248610274 TEST=Boot the device, and check the PCR 10 BRANCH=none Signed-off-by: Yi Chou <yich@google.com> Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79437 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04Documentation: Update internal URL'sJon Murphy
Update URL's to point to head rather than the deprecated refs/heads/master. Change-Id: I16f0c087762ff049115b67de3ac0b881aa4e4b40 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-04driver/wifi: DDR RFIM _DSM method function 3 report incorrect valueSimon Yang
The DDR RFIM _DSM method function 3 need to return: - 0: Enable DDR RFIM feature. - 1: Disable DDR RFIM feature. BUG=b:302084312 TEST=Build, dump SSDT to check _DSM function 3 return value Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
2024-01-04nb/intel/sandybridge/raminit: Honor SPD's dll_off_modePatrick Rudolph
In DDR3 DLL-Off mode is an optional feature advertised by SPD. Honor the SPD and only use DLL-Off mode when all DIMMs on the same channel indicate support for it. The same is done on MRC.bin. Tested on Lenovo X220: Still boots fine. Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79758 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.aslFelix Held
To avoid code duplication and to also bring the mainboards using the Picasso SoC more in line with Cezanne and newer, factor out the SoC- specific code from the mainboard's dsdt.asl files to the SoC's soc.asl. TEST=Timeless builds result in identical images for Bilby, Mandolin, and Zork/Morphius Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-03mb/intel/mtlrvp: add 512KB SI_EC FMAP regionDeepti Deshatty
This patch introduces the 512KB SI_EC FMAP region for storing the EC firmware, a necessary addition to support EC chips without internal flash memory. As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction with the Microchip EC1723, and the changes are verified. Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 BUG=b:289783489 TEST=build "emerge-rex coreboot chromeos-bootimage" is successful. changes are verified. EC Log: 23-11-06 17:46:49.564 --- UART initialized after reboot --- 23-11-06 17:46:49.564 [Image: RO, mtlrvpp_m1723_v3.5.142816-ec:6596a3, os:f660f7,cmsis:42cf18,picolibc:6669e4] 23-11-06 17:46:54.609 D: Power state: S5 --> S5S4 23-11-06 17:46:54.620 D: Power state: S5S4 --> S4 23-11-06 17:46:54.620 D: Power state: S4 --> S4S3 23-11-06 17:46:54.642 I: power state 10 = S3S0, in 0x0087 23-11-06 17:46:54.642 ec:~>: Power state: S3S0 --> S0 Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79209 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03mb/google/rex/var/screebo: Prevent camera LED blinking during bootJason Chen
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot, preventing privacy LED blink. BUG=b:317434358 TEST=none Change-Id: I43044e64c2c3a645ec0cad2ac903cc19ac89c9af Signed-off-by: Jason Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79803 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-01-03cpu/x86/64bit/mode_switch: Simplify assembly codePatrick Rudolph
Drop the first argument specifying the number of arguments pushed to the stack. Instead always push the 3 arguments to stack and use the first one as function pointer to call while in protected mode. While on it add more comments and simplify register restore code. Tested: - On qemu can call x86_32 function and pass argument and return value. - Booted Lenovo X220 in x86_64 mode using x86_32 MRC. Change-Id: I30809453a1800ba3c0df60acd7eca778841c520f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79752 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64Patrick Rudolph
- Remove pointers in argument list passed to MRC to make sure the struct has the same size on x86_64 as on x86_32. - Add assembly wrapper to call the MRC with argument in EAX. - Wrap calling MRC in protected_mode_call_2arg, which is a stub on x86_32 Tested: Boots on Lenovo X220 using MRC in x86_32 and x86_64 mode. Change-Id: Id755e7381c5a94360e3511c53432d68b7687df67 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-02mb/google/fizz: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/razer: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built razer/blade_stealth_kbl with BUILD_TIMELESS=1 and the resulting binary remains the same. Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/intel/kblrvp: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verificationJeremy Compostella
Enabling SSE2 accelerated RSA signature verification saves 4.7 ms of boot time. | modpow() function call | original | SSE2 Algorithm 2 | |----------------------------+----------+------------------| | coreboot/verstage - step 1 | 6.644 | 3.042 | | coreboot/verstage - step 2 | 1.891 | 0.757 | |----------------------------+----------+------------------| | Total (ms) | 8.535 | 3.799 | BUG=b:312709384 TEST=modular exponentiation is more than twice faster on rex0 Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79291 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-02mb/google/rex/var/karis: Enhance CNVi and PCIe switchingTyler Wang
1. Set PCIe related GPIOs to NC if fw_config use "WIFI_CNVI". 2. Set CNVi related GPIOs to NC if fw_config use "WIFI_PCIE". 3. Remove "ALC5650_NO_AMP_I2S" case in fw_config_gpio_padbased_override(). bt_i2s_enable_pads should not relevant to audio codec/amp, and it is already enabled in "WIFI_CNVI" case. BUG=b:312099281 TEST=Build and test on karis Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79765 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-31libpayload: Remove shell for loops in install Makefile targetPatrick Georgi
They always require special care so that line breaks and variable names are escaped properly. One loop can be removed entirely because install accepts multiple files to install in a target directories, the other loops were filled by find which can just call the commands on its own. Change-Id: I9f9dddfe3f3ceceb6a0510d6dd862351e4b10210 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79523 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-31mb/google/nissa/var/craask: Add ILTK touchscreenRen Kuo
Add touchscreen ILTK for craaskwell. Refer to ILI2901A-A200 Data Sheet_V1.1_20231026. BUG=b:308873706 TEST=build and check touchscreen function on craask Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-12-31mb/google/dedede: Create dita variantSheng-Liang Pan
Create the dita variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:317292413 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DITA Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-12-31vendorcode/google/chromeos: Add API for Chromebook Plus checkSubrata Banik
This patch implements an API which relies on the chromeos_get_factory_config() function to retrieve the factory config value. This information is useful to determine whether a ChromeOS device is branded as a Chromebook Plus based on specific bit flags: - Bit 4 (0x10): Indicates whether the device chassis has the "chromebook-plus" branding. - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus hardware specifications. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-31vendorcode/google/chromeos: Add API to read factory configSubrata Banik
This code leverages the TPM vendor-specific function tlcl_cr50_get_factory_config() to fetch the device's factory configuration. BUG=b:317880956 TEST=Able to retrieve the factory config from google/screebo. Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-31security/tpm: Retrieve factory configuration for device w/ Google TPMSubrata Banik
This patch enables retrieval of factory configuration data from Google TPM devices (both Cr50 and Ti50). This patch utilizes vendor-specific command TPM2_CR50_SUB_CMD_GET_FACTORY_CONFIG (68). The factory config space is a 64-bit, one-time programmable. For the unprovisioned one, the read will be 0x0. BUG=b:317880956 TEST=Able to retrieve the factory config from google/screebo. Change-Id: Ifd0e850770152a03aa46d7f8bbb76f7520a59081 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79736 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-29util/liveiso: Update to 23.11 releaseFelix Singer
The package 'bluezFull' got superseded by 'bluez'. So just remove the related line since 'bluez' is the default. Change-Id: Ibf72c37205017b27012064b311a9510136351c0f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-29util/docker/fedora: Add Dockerfile.baseFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-28mb/google/nissa/var/anraggar: add hook for WiFi SAR tablecengjianeng
As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Cq-Depend: chrome-internal:6790137 Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-28mb/pcengines/apu2/mainboard: add/fix comments on PIRQ tableFelix Held
Align the comments on the PIRQ table entries for the PCI bridge devices to the external PCIe ports with the devicetrees of the different APU boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da Reviewed-on: https://review.coreboot.org/c/coreboot/+/79676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-28mb/pcengines/apu2/mainboard: improve alignment in PIRQ table entriesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If08f7674509c953cf46c4e0d280edc9f863ef2d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79675 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-28mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5Krystian Hebel
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I30cff76abddd3f9a81ac5041260ca7ab1d5244f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-28Documentation: Add Protectli to ships-with-coreboot hw listFilip Lewiński
Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-12-28libpayload: Add VBOOT_X86_RSA_ACCELERATION configJeremy Compostella
Add `VBOOT_X86_RSA_ACCELERATION' Kconfig option to enable SSE2 instruction set implementation of modulus exponentiation which is part of the RSA signature verification process. This option is enabled on CHROMEOS. | modpow() function call | original on rex0 | SSE2 on rex0 | |------------------------+------------------+--------------| | depthcharge - step 1 | 0.547 | 0.288 | | depthcharge - step 2 | 0.152 | 0.081 | | depthcharge - step 3 | 0.164 | 0.079 | |------------------------+------------------+--------------| | Total (ms) | 0.863 | 0.448 | | modpow() function call | original on brya0 | SSE2 on rex0 | |------------------------+-------------------+--------------| | depthcharge - step 1 | 0.693 | 0.248 | | depthcharge - step 2 | 0.172 | 0.065 | | depthcharge - step 3 | 0.223 | 0.067 | |------------------------+-------------------+--------------| | Total (ms) | 1.088 | 0.38 | BUG=b:312709384 TEST=modular exponentiation is about twice faster on rex0 and brya0 Change-Id: I801ebd7839261c6bd07fb218e1e36a7108e219bf Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-12-28mb/google/brox: Add new GFX devicesShelley Chen
Add GFX devices for DDI (eDP and HDMI) and TCP (USC C0 and C2 ports). Copied the PLD placements from USB PLDs. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-27vboot: add VBOOT_X86_RSA_ACCELERATION configJeremy Compostella
Add `VBOOT_X86_RSA_ACCELERATION' Kconfig option to enable SSE2 instruction set implementation of modulus exponentiation which is part of the RSA signature verification process. BUG=b:312709384 TEST=Able to use SSE2 accelerated implementation on rex0 Change-Id: Ib6e39eb9f592f36ad3dca76c8eaf2fe334704265 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79289 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-27arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constantJeremy Compostella
Use the `VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE' constant defined by the vboot project instead of hard-coding the buffer size. Change-Id: I6039fc7cf2439535ca88663806bdcf99ad5089b0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-26drivers/intel/gma: Only show the choice when a VBT is to be addedArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3bb71da8ea47f7365ae3895f5477f2a765256e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-26Update vboot submodule to upstream mainJulius Werner
Updating from commit id c0cb4bfa: 2023-12-08 signer: sign_android_image.sh should die when image repacking fails to commit id 7c3b60bb: 2023-10-13 firmware/2lib: Use SSE2 to speed-up Montgomery multiplication This brings in 3 new commits: 7c3b60bb firmware/2lib: Use SSE2 to speed-up Montgomery multiplication 8bb2f369 firmware: 2load_kernel: Set data_key allow_hwcrypto flag 2b183b58 vboot_reference: open drive rdonly when getting details 6ee22049 sign_official_build: switch from dgst to pkeyutl da69cf46 Makefile: Add support for make 4.3 Also update the implementations of the vb2ex_hwcrypto_modexp() callback to match the API changes made in vboot. Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-26drivers/intel/fsp2_0: Add boot mode stringsMarx Wang
The FSP boot mode showing in serial log is a magic number. In order to let user understand its meaning directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [SPEW ] bootmode is set to: 2 with this change: [SPEW ] bootmode is set to: 2 (boot assuming no config change) Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-26mb/google/myst: Update DXIO descriptor definitionJon Murphy
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26mb/google/skyrim: Update DXIO descriptor definitionJon Murphy
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-26soc/amd/stoneyridge/BiosCallOuts: add missing curly bracesFelix Held
When an if block has curly braces, the corresponding else block should also have curly braces. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-26soc/amd/common/pi/agesawrapper: use is_dev_enabled(DEV_PTR())Felix Held
Since we have chipset devicetrees for all SoCs that include this code in the build, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79672 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR())Felix Held
Since we have chipset devicetrees for both SoCs supported by the Stoneyridge code, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/amd/picasso/fsp_s_params: use is_dev_enabledFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b692aaa2e3f768cc03bca71eff3ceb1a8733ad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79670 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/alderlake: Make C1e configurableSean Rhodes
Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26sb/intel/bd82x6x/pch: Add method to identify PCHPatrick Rudolph
Identify PCH type by LPC device ID. This allows to identify the PCH without including northbridge headers. Tested: Lenovo X220 still boots. Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-26mb/google/zork/dsdt: move LIDS object right after dsdt_top.aslFelix Held
This is a preparation to make the next patch result in identical images for timeless builds and also aligns Zork's DSDT more with Guybrush's DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-26soc/intel/xeon/spr: Enforce POR frequency settingNaresh Solanki
For RMT build, add kconfig option to enforce Plan Of Record restriction on DDR5 frequency & voltage settings. Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-23sb/intel/bd82x6x: Add defines for PCI IDsPatrick Rudolph
Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-23nb/intel/{gm45,sandybridge}: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-23mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460pRiku Viitanen
Extracted from a system running OEM BIOS version F.42. intelvbttool --inlegacy --outvbt data.vbt Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79625 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-23.gitreview: Update default branch from master to mainArthur Heymans
The master is deprecated in favor of the main. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-23sb/intel/bd82x6x: Honor POST code Kconfig optionKeith Hui
This southbridge can route POST codes written to port 0x80 to either LPC or PCI, but currently always route them to LPC. Change it so that POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is selected, LPC otherwise. Rename the static function because POST codes no longer always go to LPC. Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-23mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,the values before Sensor1 and Sensor2 were set too high. Modify the protection temperature to better meet DUT requirements. BUG=b:291217859 BRANCH=none TEST=emerge-rex coreboot Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPDSubrata Banik
This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22drivers/intel/fsp2_0: Log FW Splash Screen feature stateSubrata Banik
This patch implements debug logging to aid debugging and analysis of Firmware Splash Screen feature behavior. BUG=b:284799726 BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/screebo and check the FW splash screen state. [DEBUG] Firmware Splash Screen : Enabled Change-Id: I1ec7badf620e8dbe3d48674d93d640161de6a830 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22soc/intel/cmn/block/pmc: Add previous sleep state strings in logMarx Wang
Previous sleep state showing in serial log is a magic number. In order to let users understand its meanings directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [DEBUG] prev_sleep_state 0 with this change: [DEBUG] prev_sleep_state 0 (S0) Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-22mb/google/rex/var/karis: Adjust touchscreen power-on sequenceTyler Wang
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high should over 5ms. And current measure result is 200us. Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet requirment. Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high: Power on --> 31.7 ms Resume --> 38.7 ms BUG=b:314245238 TEST=Measure the sequence Change-Id: I56e455a980b465f27794b30df058ec0944befc2e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42Jeremy Compostella
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22x86: Separate CPU and SoC physical address sizeJeremy Compostella
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22Revert "cpu/intel/common: Define build time physical address reserved bits"Jeremy Compostella
This reverts commit 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-22Revert "soc/intel/meteorlake: Set build time physical address reserved bits"Jeremy Compostella
This reverts commit 533efb23083afd721d4c268ce0ee8e863e13689a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79664 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22mb/google/nissa/var/gothrax: Add probe for Type-C Port C1 (DB)Yunlong Jia
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board). DB_A is only used for skus without Type-C Port C1. BUG=b:316048649 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ifb702c497740953144b43c56653da16fade1053f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629 Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22mb/google/brox: Fix config errors with 8 GPIOsShelley Chen
Some GPIOs were not configured correctly according to the HW spreadsheet provided by the HW team. * GPP_B5/GPP_B6 use NF1, not NF2 * GPP_B23 should use NF2, no GPI * GPP_D11 should be set to NC * GPP_E21/22 should be using NF (previous NC) * GPP_F17 is a GPO * GPP_F18 should be an interrupt, not a NF BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-22mb/google/brox: Align GPIO reset with HW spreadsheetShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL are to fix the pad's reset field as needed. See "Intel SoCs" section in https://doc.coreboot.org/getting_started/gpio.html for reset definitions. BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 18:53:32 +0000