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2021-10-21mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO DescriptorKarthikeyan Ramasubramanian
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-21mb/google/guybrush: Make DXIO Port Descriptor configurableKarthikeyan Ramasubramanian
Instead of a const port descriptor, make it configurable. This will help to avoid adding duplicate tables for every minor configuration updates. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and cold reboot cycles for 10 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21cpu/x86/mp_init: use cb_err as run_ap_work return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_run_on_aps which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of run_ap_work gets translated to the int values in mp_run_on_aps. This could also be done by a cast of the run_ap_work return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init & bsp_do_flight_plan return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_init_with_smm which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of mp_init gets translated to the int values in mp_init_with_smm. This could also be done by a cast of the mp_init return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as wait_for_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of wait_for_aps to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as apic_wait_timeout return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of apic_wait_timeout to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_permanent_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_relocation_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Remove cpu parameter to ap_initRaul E Rangel
We now pre-populate cpu_info before jumping to the C handler. We no longer need this parameter. I moved the stack alignment closer to the actual invocation of the C handler so it's easier to reason about. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify all CPUs still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MPRaul E Rangel
This will reduce the number of AP init paths we need to support. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and see all CPUs initialized correctly Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errorsRaul E Rangel
There are two possible code sections where the cpu_info macros can be included: .code32 and .code64 Doing a `push %eax` while in a .code64 section will result in a compiler error. This macro manually pushes the 32-bit register onto the stack so we can share the code between 32 and 64 bit builds. We also can't implicitly dereference per_cpu_segment_selector because it's a 32-bit address. Trying to do this results in the following: E: Invalid reloc type: 11 E: Illegal use of 32bit sign extended addressing at offset 0x1b2 If we load the address first, then dereference it, we can work around the limitation. With these fixes, 64-bit builds can now use CPU_INFO_V2. BUG=b:179699789 TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init work as expected. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21mb/google/brya/var/kano: Enable BT offload supportDavid Wu
Enable the CnviBtAudioOffload UPD and program the corresponding BT VPGIOs. BUG=b:202913826 TEST=emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21util/release/build-release: Create cross-toolchain version fileFelix Singer
Add cross-toolchain version file to the release tarball, which can be used for pre-setting the variables used in buildgcc. Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possibleFelix Singer
For reproducibility, a version string is appended to the version of the tools used in the cross-toolchain. Currently, git is used to determine that version string at runtime of this script. There are cases, where it's not possible to determine that version string, e.g. when a release tarball is used, and if so, the version string is just `v_`. Thus, allow pre-setting the variable `CROSSGCC_VERSION`. Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21mb/google/trogdor: determine which panel to use by panel_id for quackingstickSheng-Liang Pan
panel_id 6 for AUO B101UAN08.3. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I076ded9300c2ec1704a566722870bd0d1a20e9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58363 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21mb/google/dedede/var/bugzzy: Add LTE power off sequenceSeunghwan Kim
This change adds LTE power off sequence for bugzzy. BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21mb/google/dedede/var/bugzzy: Enable/disable LTE function based on FW_CONFIGSeunghwan Kim
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG. - GPIO control - USB port setting BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20cpu/x86/mp_init: rework start_aps to fix X86_AMD_INIT_SIPI caseFelix Held
When CONFIG_X86_AMD_INIT_SIPI was set, the second/final SIPI that afterwards checks if all APs have checked in was skipped and if it got so far, start_aps returned CB_SUCCESS despite not having checked if all APs had checked in after the SIPI. This patch makes start_aps skip the first SIPI in the CONFIG_X86_AMD_INIT_SIPI case so we use the proper timeouts and error handling for the final and this case only SIPI and signal the caller an error when not all APs have checked in after the SIPI. A timeless build for lenovo/x230 which is a mainboard that doesn't select X86_AMD_INIT_SIPI results in identical binary, so this doesn't change the behavior of the !X86_AMD_INIT_SIPI case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39438229497c5d9c44dc7e247c7b2c81252b4bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-20google/trogdor: Support Parade ps8640Philip Chen
Support Parade ps8640 as the second source edp bridge for some trogdor board variants/revisions. BUG=b:194741013 BRANCH=trogdor TEST=verified firmware screen works on lazor rev9 Change-Id: Iae5ccd8d9d33d60e4c37011ecffdd7a05af59ab2 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-20mb/google/brya/var/redrix: Enable bt_offload supportMac Chiang
Enable CnviBtAudioOffload UPD and program the corresponding VGPIO pins BUG=b:191931762 TEST=emerge-coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I81bae537d52592e878db56343970de6fc488950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20util/crossgcc/buildgcc: Allow printing only the versionFelix Singer
In preperation to CB:58396, add the parameter `-W|--print-version`, which allows printing the content of `CROSSGCC_VERSION`. In combination with CB:58396, this can be used to pre-set the variable in case of the git history is not accessible. Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-20util/crossgcc/buildgcc: Remove CROSSGCC_COMMITFelix Singer
For reproducibility, the buildgcc script is copied to the destination folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name extension for the script and was introduced when `CROSSGCC_VERSION` didn't contain the commit yet. Since this is not the case anymore, remove it. Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20mb/intel/adlrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: use cb_err as start_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: add final new line to debug messagesFelix Held
Since during AP startup it's not guaranteed that no AP console output will be printed between consecutive printk calls in send_sipi_to_aps, add a new line character to all printks to make sure to have the outputs from the APs on separate lines. For consistency also add a final new line character to the printk call in start_aps. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: factor out send_sipi_to_aps functionFelix Held
Apart from the SIPI number in the debug message the two instances of the SIPI sending code in start_aps are identical, so factor it out into a new send_sipi_to_aps function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: use types.h includeFelix Held
Using types.h as include instead of stddef.h and stdint.h will also provide commonlib/bsd/cb_err.h which will be used in follow-up patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20util/cbfstool/rmodule: Omit undefined extern symbols from reloc tableRaul E Rangel
When using `DECLARE_OPTIONAL_REGION`, it is assumed that REGION_SIZE(name) == 0 if the region was not defined in the memlayout. When using non-rmodule stages (i.e., bootblock, romstage, etc), this assumption holds true, but breaks down in rmodule (i.e., ramstage) stages. The rmodule tool is not currently omitting undefined externals from the relocation table. e.g., extern u8 _##name##_size[]; This means that when the rmodule loader runs, it will rewrite the symbol from 0 (which is the default the linker assumed) to 0 + offset. This is wrong since the symbol doesn't actually exist. Instead we need to omit the relocation so it continues to keep the default value of 0. BUG=b:179699789 TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set to 0. I also see the following printed by the rmodtool now: DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for absolute symbol: _stack_size DEBUG: Omitting relocation for absolute symbol: _program_size DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size As you can see the _watchdog_tombstone will also be fixed by this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20lib/cbfs: Call rdev_unmap on hash mismatchRaul E Rangel
We don't want to leak any mappings. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibcd28ce12cbd5e221e8f4fa910fd8472bedb802f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20kconfig_lint: use just one variable for keeping track of choicesMichael Niewöhner
Instead of using two variables, one for the boolean value and one for the path, use just one with the path. Since an empty string evalutes to false, this simplification does not change behaviour. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2f1171789af6815094446f107f3c634332a3427e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20kconfig_lint: put $inside_choice together right in the first placeMichael Niewöhner
Instead of substituting the delimiter later, put $inside_choice together right in the first place. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20soc/amd/common/block/cpu: Remove magic number in memlayoutRaul E Rangel
The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20soc/intel/alderlake: Fix wrong FIVR configs assignmentBora Guvendik
For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used by mistake, instead of the expected vnn_sx_enable_bitmap Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/intel/adlrvp_m: Enable touchpadBernardo Perez Priego
These changes include ELAN touchpad to ACPI tables and configure GPIO's. BUG=None Test=Boot board, touchpad should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20mb/intel/adlrvp: Remove EC regionBernardo Perez Priego
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-20psp_verstage: remove psp_ef_table structKangheui Won
psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-20mb/google/brya/anahera: Add two thermal sensor settingWisley Chen
Anahera has 4 thermal sensors, so add the missing sensors settings. BUG=b:203187535 TEST=build and verified by thermal team. Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/brya/anahera: Update HID to MX98360AWisley Chen
Because of a change in the chromium OS kernel machine driver for the MAX98357A, a _HID that matches MAX98360A has to be used. (https://chromium- review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/) BUG=b:200778066 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ic68373920d9135e614ff792149079de451ec6e60 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/taeko: enable DPTF functionality for taekoKevin Chang
Enable DPTF functionality for taeko BRANCH=None BUG=b:203035930 TEST=Built and tested on taeko board Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-10-20mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMCWisley Chen
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6 BUG=b:197850509 TEST=build and boot into eMMC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/google/dedede/var/bugzzy: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20mb/google/dedede/var/sasuke: Generate SPD ID for Samsung K4U6E3S4AB-MGCLSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I91183f33b92569dd49967ef866d58043d79c287b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20soc/intel/{skl,apl}: don't run or even include SGX code if disabledMichael Niewöhner
Do not run or include any code in case the user did not explicitly enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`. Also move the ifdef inside the ASL file. Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-20mb/google/brya/var/taeko: Add fw_config probe for ALC5682-VSJoey Peng
ALC5682-VD/ALC5682-VS load different kernel driver by different _HID. Update the _HID depending on the AUDIO field of fw_config.Define fw config bit 5-7 in coreboot for codec. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20mb/intel/jasperlake_rvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-19soc/intel/skl: Constify `soc_get_cstate_map()`Patrick Georgi
This is a follow-up to commit e9f10ff38b which changed the base signature and all other occurrences. To make gcc11 happy (which is pickier about these things), let skylake follow. Change-Id: I42a629d865baa53640213a03e54e85623a386e35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58458 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-19mb/intel/kblrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each variant. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-19mb/intel/coffeelake_rvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2021-10-19mb/google/brya/var/kano: Correct SSD power sequenceDavid Wu
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:192137970 TEST=FW_NAME=kano emerge-brya coreboot and boot to OS. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/common/block/cse: Use newly added `create-cse-region`Furquan Shaikh
This change uses the newly added `create-cse-region` command for cse_serger tool instead of performing `dd` operations for each partition. BUG=b:189177580 Change-Id: Ia915e3ac423f9461876e9ae186fb8ddce55f3194 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19util/cse_serger: Add command `create-cse-region`Furquan Shaikh
This change adds a new command `create-cse-region` to cse_serger tool which takes as inputs offset:size and file for different CSE partitions and generates the entire CSE region image. BUG=b:189177186 Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19util/cse_serger: Replace cse_layout_regions with array of regionsFurquan Shaikh
This change replaces `struct cse_layout_regions` with an array of `struct region` and introduces enums for DP and BP[1-4]. This makes it easier to loop over the different regions in following changes. BUG=b:189177186 Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_BFurquan Shaikh
CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region in case of firmware update. Ensure that the size of the regions match so that we do not have situations where ME_RW_A/B firmware grows bigger than what CSE_RW can hold. BUG=b:189177538 Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/common/cse: Support RW update when stitching CSE binaryFurquan Shaikh
This change updates the STITCH_ME_BIN path to enable support for including CSE RW update in CBFS. CSE_RW_FILE is set to either CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the selection of STITCH_ME_BIN config. BUG=b:189177580 Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19mb/google/brya: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh
This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: I4da677da2e24b0398d04786e71490611db635ead Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/alderlake: Enable support for CSE stitchingFurquan Shaikh
This change enables support for stitching of BP1 and BP2 partitions for CSE. This currently mimics what Intel FIT tool does w.r.t. adding different components to the different partitions. BP1: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP. * Decomposed components from CSE FPT file: RBEP, MFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC. BP2: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP. * Decomposed components from CSE FPT file: RBEP, FTPR, NFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP. BUG=b:189177580,b:189177538 Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel/common/cse: Add support for stitching CSE componentsFurquan Shaikh
This change adds support for allowing mainboards to stitch CSE components during build time instead of adding a pre-built CSE binary. Several Kconfig options are added to allow mainboard to provide the file names for different CSE region components. This makes use of the newly added cse_serger and cse_fpt tools to create following partitions: 1. BP1 - RO 2. BP2 - RW 3. Layout In addition to this, it accepts CSE data partition as an input using Kconfig CSE_DATA_FILE. All these partitions are then assembled together as per the following mainboard FMAP regions: 1. BP1(RO) : CSE_RO 2. BP2(RW) : CSE_RW 3. Layout : CSE_LAYOUT 4. Data : CSE_DATA Finally, it generates the target $(OBJ_ME_BIN) which is used to put together the binary in final coreboot.rom image. Several helper functions are added to soc/intel/Makefile.inc to allow SoCs to define which components use: 1. Decomposed files: Files decomposed from Intel release CSE binary in FPT format. 2. Input files: Mainboard provided input files using corresponding Kconfigs. 3. Dummy: Components that are required to have dummy entries in BPDT header. These helpers are added to soc/intel/Makefile.inc to ensure that the functions are defined by the time the invocations are encountered in SoC Makefile.inc. BUG=b:189177580 Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19southbridge/intel/common: Add an option to allow stitching of CSE binaryFurquan Shaikh
In the following changes, CSE binary for some platforms will be stitched at build time instead of adding a pre-built binary. This change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to select if it wants to stitch CSE binary instead of adding a pre-built one. In this case, ME_BIN_PATH is not visible to user and instead mainboard and/or SoC code is expected to provide the recipe for stitching the CSE image. BUG=b:189177580 Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19util/cse*: Add cse_helpers.{c,h}Furquan Shaikh
This change moves `read_member` and `write_member` helper functions out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid duplication. BUG=b:189177186,b:189167923 Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19util/cse_serger: Add a new tool for stitching CSE componentsFurquan Shaikh
This change adds a new tool `cse_serger` which can be used to print, dump and stitch together different components for the CSE region. BUG=b:189177186 Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19util/cse_fpt: Add a new tool for managing Intel CSE FPT binariesFurquan Shaikh
This change adds a new tool `cse_fpt` which can be used to print and dump CSE partitions in Flash Partition Table (FPT) format. BUG=b:189167923 Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19cpu/intel/speedstep: Constify `get_cst_entries()`Angel Pons
Make the `get_cst_entries()` function provide a read-only pointer. Also, constify the actual data where applicable. Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19soc/intel: Constify `soc_get_cstate_map()`Angel Pons
Return a read-only pointer from the `soc_get_cstate_map()` function. Also, constify the actual data where applicable. Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19acpi/acpigen: Constify CST functions' pointersAngel Pons
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry` functions don't modify the provided C-state information. So, make the pointer parameters read-only to enforce this. Also constify arguments where possible. Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19soc/intel/*/acpi.c: Don't copy structs with `memcpy()`Angel Pons
A regular assignment works just as well and also allows type-checking. Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19arch/x86: Increase MAX_SMBIOS_SIZETim Wawrzynczak
With the recent addition of SMBIOS table 20, the cbmem area on google/brya0 overflows and ERROR: Increase SMBIOS size SMBIOS tables: 2128 bytes. is seen in the logs. Therefore, double the size of the SMBIOS area from 2 KiB to 4 KiB to accomodate more tables as needed. This happens during ramstage so 2k is not a big deal at this point. Change-Id: I43aa6a88d176e783cc9a4441b35b8d608c4101cd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-19soc/amd/common/block/include/psp_efs: don't typedef structFelix Held
Don't use a typedef for the embedded_firmware struct so that it's clearer that this is a struct. TEST=Timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19util/amdfwtool: rename PSP related embedded_firmware struct elementsFelix Held
The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19soc/amd/common/block/include/psp_efs: rename embedded_firmware elementsFelix Held
The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19mb/google/guybrush/dewatt: update DRAM tableKenneth Chan
Samsung LPDDR4X 4266 2G K4U6E3S4AB-MGCL Hynix LPDDR4X 4266 2G H54G46CYRBX267 Micron LPDDR4X 4266 2G MT53E512M32D1NP-046 WT:B Micron LPDDR4X 4266 4G MT53E1G32D2NP-046 WT:B BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I31ec5b84b5ad2e8d0aedf41ceb56f9e5f7fa538a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58313 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18cbfstool: Add helper function `buffer_from_file_aligned_size`Furquan Shaikh
This change adds a helper function `buffer_from_file_aligned_size` that loads a file into memory buffer by creating a memory buffer of size rounded up to the provided `size_granularity` parameter. BUG=b:189177186,b:189167923 Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18kconfig_lint: Drop overly restrictive rule about choice configsNico Huber
This rule was creating trouble: * A symbol may only be declared inside or outside a choice. The linter treats every occurence of a `config` entry as a symbol declaration, even when it's just setting a default or adding selects. This is not easy to fix as the symbol objects are not created first and then added to the $symbols array when we know what kind of decla- ration we have, but are created incrementally inside this global list. Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18sc7280: Add GSI FW download supportRavi Kumar Bokka
Add GSI Firmware download support for QUP wrappers. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I68c106c942acadc752351f03843d93612cf9c19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-18build system: immediately report what users are supposed to look intoPatrick Georgi
Instead of just logging "Check out that file over there for this type of values", why not emit them directly? Change-Id: I54630afce4011ab9ee3eda415e95d5b7d5812e6b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-18cpu/x86/cpu_info.S: Remove ebx save/restoreRaul E Rangel
The push/pop of %ebx was only added because smm_stub saves the canary value in it. Now that we no longer use cpu_info in smm, we no longer need to save the register. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-18cpu/x86/smm/smm_stub: Remove cpu_infoRaul E Rangel
Now that cpu_info() is no longer used by COOP_MULTITASKING, we no longer need to set up cpu_info in SMM. When using CPU_INFO_V2, if something does manage to call cpu_info() while executing in SMM mode, the %gs segment is disabled, so it will generate an exception. BUG=b:179699789 TEST=Boot guybrush to OS with threads enabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-18arch/x86/assembly_entry: Remove cpu_infoRaul E Rangel
Since cpu_info() is no longer required to use threads, we no longer need to initialize it in romstage or earlier. This code was also incomplete since it didn't initialize the %gs segment. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I615b718e9f035ca68ecca9f57d7f4121db0c83b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-18arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/threadRaul E Rangel
We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in all stages. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18libpayload: Add unit-tests framework and first test caseJakub Czapiga
This commit adds a unit-tests framework ported from coreboot, and test for drivers/speaker. Usage of the unit-tests framework is same as for the coreboot one. Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-18intel/tigerlake: Add missing IRQ for CNViSean Rhodes
Add CNVi (14.3) to IRQ Table to stop dmesg error: iwlwifi 0000:00:14.3: can't derive routing for PCI INT F iwlwifi 0000:00:14.3: PCI INT F: not connected Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18soc/skylake: Make VT-d controllable from CMOS optionSean Rhodes
Make VT-d enable or disable based on CMOS value "vtd" 1 = Enable 0 = Disable Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1aea14968e08ee6af822bd259ca1d462f8926994 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-18mb/intel/adlrvp_m: Enable retimer force power gpioBernardo Perez Priego
Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain to toggle during a switch from DP Alt to TBT Alt modes. Contrary to DS specifying it may be left unconfigured, hence floating, there are instances seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp). Hence configure it to LOW. Branch=none Bug=none Test=Boot to OS, connect TBT dock which enumerates in DP Alt, Login, TBT dock enumerates in TBT Alt Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-10-18cpu/intel/hyperthreading: Use initial LAPIC IDsKyösti Mälkki
For older CPU models where CPUID leaf 0xb is not supported, use initial LAPIC ID from CPUID instead of LAPIC register space to to detect if logical CPU is a hyperthreading sibling. The one in LAPIC space is more complex to read, and might not reflect CPU topology as it can be modified in XAPIC mode. Change-Id: I8c458824db1ea66948126622a3e0d0604e391e4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-10-18cpu/intel/hyperthreading: Use cpuid_get_max_func()Kyösti Mälkki
Change-Id: I4b69b1d20b5a768c269d85f0ea23f79e02391a71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-10-18cpu/intel/hyperthreading: Use CPUID leaf 0xb without X2APICKyösti Mälkki
It is not a requirement to have X2APIC mode enabled to use CPUID leaf 0xb EDX to detect logical CPU is a hyperthreading sibling. Change-Id: I288f2df5a392c396f92bb6d18908df35de55915d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-10-18cpu/x86/lapic: Drop xapic_write_atomic()Kyösti Mälkki
Remove code, which was only needed for B and C2 stepping of P54C. The linux kernel source has commentary on X86_BUG_11AP: * See if we have a good local APIC by checking for buggy Pentia, * i.e. all B steppings and the C2 stepping of P54C when using their * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update") Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-17sb/amd/cimx/sb800: Clear IOAPIC vectors only onceKyösti Mälkki
Change-Id: I640d17cdee2bdaa4fe7049ce66a327b58924bc6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-10-17drivers/generic/ioapic: Drop enable_virtual_wireKyösti Mälkki
All boards with DRIVERS_GENERIC_IOAPIC select it. Presumably the related configuration of routing IRQ0 when IOAPIC is enabled should be always done to provide i8259 legacy compatibility for payloads. Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/skylake: switch to common ACPI codeMichael Niewöhner
Use the common ACPI code to reduce code duplication. After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state table generation (as of commit c2540a9) and the number reduces from 10 to 7 entries. Also, remnants of P_BLK support missed in CB:58096 will vanish. Tested on google/fizz: no errors in dmesg, ACPI tables remain the same (except PSS, as mentioned above). Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-10-17soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM TimerMichael Niewöhner
Apollo Lake and Gemini Lake do not have a hardware PM ACPI timer but only uCode PM Timer emulation. Add a Kconfig `NO_PM_ACPI_TIMER` denoting SoCs without PM Timer and make it mutually exclusive with the Kconfig `USE_PM_ACPI_TIMER`. This is partly redundant to `PM_ACPI_TIMER_OPTIONAL`, which will be dropped in the follow-up change, though. Change-Id: Ic323bbfb7089c53a6f22724910a0ff3df8904ebd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/*: only enable PM Timer emulation if the PM Timer is disabledMichael Niewöhner
uCode PM Timer emulation is only needed when the hardware PM ACPI timer is disabled. Also, since it redirects any register accesses to uCode, it overrides the hardware PM Timer. Thus, only enable emulation when required. Change-Id: I60a775bd6eb4206750f606ce8a8777d2e2dfb579 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-10-17soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosenMichael Niewöhner
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. For SKL and CNL, this temporarly redundantly disables the PM Timer, since FSP does that, too. This redundancy is resolved in the follow-up. Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: implement ACPI timer disabling per SoC and drop common codeMichael Niewöhner
Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: move disabling of PM Timer to SoC PMC codeMichael Niewöhner
Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wakeMichael Niewöhner
Currently, only the PM1_STS mask gets passed to `acpi_fill_soc_wake`. To be able to override the GPE0_STS mask as well, also pass that one. To accomplish that, pointers to the variables are passed now. Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/common/acpi: drop `RTC_EN` from static wake bits maskMichael Niewöhner
`RTC_EN` is in the RTC well* so we can rely on the actual register content instead of statically overriding it. Drop it from the static wake bits mask. * Tested on clevo/l140cu Change-Id: Ia0ae71f0a472513233bc0fd5625faf15bf86beaf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-17soc/intel: deduplicate acpi_fill_soc_wakeMichael Niewöhner
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/skylake: switch to common GNVSMichael Niewöhner
Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 21:29:14 +0000