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2024-11-27drivers/wifi: Support Ultra High Band Country SelectionJeremy Compostella
This feature provides ability to set the Bluetooth Ultra High Band (UHB) settings per country. The bluetooth UHB country selection is defined as follow (default is 0): | Bit | Value | | |-------+-------+---------------------------------------------------| | 0 | 0 | No override; use BT device settings | | | 1 | Force disable BT in all countries that are not | | | | defined in the following bits | | 1 | 0 | USA 6GHz BT disable | | | 1 | 6GHz BT allowed in the USA (enabled only if the | | | | device is certified to the USA) | | 2 | 0 | Rest of the World 6GHz BT disable | | | 1 | 6GHz BT allowed in the Rest of the World (enabled | | | | only if the device is certified to the rest | | | | of the world) | | 3 | 0 | EU countries 6GHz BT disable | | | 1 | 6GHz BT allowed in the EU countries (enabled only | | | | if the device is certified to the EU countries) | | 4 | 0 | South Korea 6GHz BT disable | | | 1 | 6GHz BT allowed in the South Korea (enabled only | | | | if the device is certified to the South Korea) | | 5 | 0 | Brazil 6GHz BT disable | | | 1 | 6GHz BT allowed in the Brazil (enabled only if | | | | the device is certified to the Brazil) | | 6 | 0 | Chile 6GHz BT disable | | | 1 | 6GHz BT allowed in the Chile (enabled only if the | | | | device is certified to the Chile) | | 7 | 0 | Japan 6GHz BT disable | | | 1 | 6GHz BT allowed in Japan (enabled only if the | | | | device is certified to Japan) | | 8 | 0 | Canada 6GHz BT disable | | | 1 | 6GHz BT allowed in Canada (enabled only if the | | | | device is certified to Canada) | | 9 | 0 | Morocco 6GHz BT disable | | | 1 | 6GHz BT allowed in the Morocco (enabled only if | | | | the device is certified to the Morocco) | | 10 | 0 | Mongolia 6GHz BT disable | | | 1 | 6GHz BT allowed in the Mongolia (enabled only if | | | | the device is certified to the Mongolia) | | 11 | 0 | Malaysia 6GHz BT disable | | | 1 | 6GHz BT allowed in the Malaysia (enabled only if | | | | the device is certified to the Malaysia) | | 31:12 | 0 | Reserved Should set to zeros | The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BUCS method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e231 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-27drivers/wifi: Support Bluetooth Bands Selection ModeJeremy Compostella
This feature provides ability to provide Bluetooth Bands Selection Mode. The bluetooth bands selection mode is defined as follow: | Bit | Band GHz | Value | Description | Default | |------+----------+-------+----------------------+---------| | 0 | 2.4GHz | 0 | Controlled by NIC | 0 | | | | 1 | Force disable 2.4GHz | | | 1 | 5.2GHz | 0 | Controlled by NIC | 0 | | | | 1 | Force disable 5.2GHz | | | 2 | 5.8GHz | 0 | Controlled by NIC | 0 | | | | 1 | Force disable 5.8GHz | | | 3 | 6.2GHz | 0 | Controlled by NIC | 0 | | | | 1 | Force disable 6.2GHz | | | 31:4 | Reserved | | NA | 0 | The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BBSM method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e230 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-27drivers/wifi: Support Bluetooth Dual Chain ModeJeremy Compostella
This feature provides ability to provide dual chain setting. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BDCM method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e220 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84943 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-11-27drivers/wifi: Support Bluetooth BiQuad Bypass FilterJeremy Compostella
This feature provides ability to identify non-LTE platform and disable BiQuad Bypass filter logic in hardware for Bluetooth usecases reducing device power consumption. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BBFB method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e213 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-27drivers/wifi: Support Bluetooth Per-Platform Antenna GainJeremy Compostella
The ACPI BPAG method provide information to controls the antenna gain method to be used per country. The antenna gain mode is a bit field (0 - disabled, 1 -enabled) defined as follow: - Bit 0 - Antenna gain in EU - Bit 1 - Antenna gain in China Mainland The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 9.2 specification. BUG=b:346600091 TEST=BPAG method is added to the bluetooth companion device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e210 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-27mb/google/rauru: Add configuration for SD card detect pinYidi Lin
Pass SD card detect GPIO to payloads for SD card detection. BUG=b:317009620 TEST=build pass Change-Id: I1901fd45833f2415c61b61f9e04ebb54440df80a Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85250 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-27mainboard/intel/frost_creek: Add support for Intel CRB Frost CreekYuchi Chen
The Frost Creek CRB is a reference platform for Intel Atom P5300 and P5700 (known as Snow Ridge NS and Snow Ridge NX) SoC. Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83322 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-27soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoCYuchi Chen
This change adds support for Intel Atom Processors P5300, P5700 product families (known as Snow Ridge NS and Snow Ridge NX). Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-27commonlib/bsd/mem_chip_info: Add mem_chip_info_entry_density_bytesYu-Ping Wu
Add a helper function to get the mem_chip_info entry size. Change-Id: Ibf2a2006fb3e7772688b80807589e8f2d64d1147 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-26mb/google/brya/var/trulo: Remove overriding of PL1 value to 20WVidya Gopalakrishnan
The RAPL PL1 limit and MMIO PL1 max values should be set as per silicon TDP as specified in the PDG doc#646929. BUG=b:378623372 TEST=Build and boot on Trulo board. Verified PL1 value is updated in DTT and sysfs interfaces. Output with 15W silicon as below: cd /sys/class/powercap/ cat intel-rapl/intel-rapl\:0/constraint_0_max_power_uw 15000000 cat intel-rapl/intel-rapl\:0/constraint_0_power_limit_uw 15000000 cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_max_power_uw 15000000 cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_power_limit_uw 15000000 Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85184 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-26mb/google/brya/var/trulo: Enable Charger participant in Passive PolicyVidya Gopalakrishnan
Update the TSR1 target's source to CHARGER in Passive Policy. BUG=b:378623372 TEST=Build and boot on Trulo board. Verified the source for TSR1 is updated to Charger in Passive Policy Change-Id: I43db616fd48fc4659dcba359f17854e14adb6039 Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-26mb/google/fatcat/var/felino: Add initial GPIOs configTongtong Pan
Configure GPIOs according to schematics revision 20241120. BUG=b:379797598 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I4e9e81af9c3d8807e65ecd552e73305c1d109a2d Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85234 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-11-26mb/google/brya: Create uldrenite variantJohn Su
Create the uldrenite variant of the brya reference board by copying the template files to a new directory named for the variant. BUG=b:376781355 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ULDRENITE Change-Id: Ife666c6f2fe69643033e2ce3b299e7414e16eef1 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85207 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-25soc/intel/ptl: Change ACPI name for IPUCliff Huang
Change IPU name to 4 characters: IPU0 While the ACPI device name is 'IPU', some part of generated SSDT looks for 'IPU_', since by convention, the names less than 4 characters is padded with underscope ("_"). Please see APCI spec 5.3 ACPI Namespace. BUG=none TEST=Boot fatcat board to OS and check that IPU device name is IPU0 in the SSDT. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I60ce2998cb1d97589c0f7544ce8dc92c12a2b8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85274 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-25Revert "mb/google/nissa/var/telith: Add 6W and 15W power limit parameters"Rui Zhou
This reverts commit c89ccaf2816a781ae0acb997557aed7d8cf10b7c. Reason for revert: b:378775630#comment11 Intel believes that the AC only issue should be addressed head-on and the previous power limit default settings should be maintained. BUG=b:378775630 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9f8344288a1811bddce702c16a244e3d4a59f195 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85276 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-23mb/google/fatcat: Move CSE sync at payloadSubrata Banik
The CSE sync in the payload would allow CrOS devices to render the user notification when updating. Currently, CrOS devices typically take 8-20 seconds to do a CSE sync. BUG=b:380220737 TEST=Able to build and boot google/fatcat. Change-Id: I8f1dd2e153ed0f1e671699002cf34a58d758ce2f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85233 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-22mb/google/brya/var/redrix: Add ACPI fan definitionsStanislaw Kardach
Add entries in overridetree.cb required for exposing fan control via ACPI, which is used then by acpi-fan driver in Linux kernel. This includes: 1. Fan duty-cycle/rpm table. The RPM numbers were adjusted to the values reported by ACPI on different duty cycle levels. 2. Dummy Active DPTF policy. This is required to mark the TFNx devices as active and therefore let the acpi-fan driver probe. BUG=b:358089775 TEST=Build and flash on redrix and check /sys/class/thermal for TFN1 Change-Id: Iaeffe8bc48cd8cd800efa7be29ec81447ecf2935 Signed-off-by: Stanislaw Kardach <skardach@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85175 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-22mb/google/nissa/var/pujjoga: Turn off camera during S0ixRoger Wang
Add a variant specific S0ix hook to fill the SSDT table to disable and enable camera during suspend and resume respectively. For safety concern, our client LENOVO want us to follow the Boten project to create the function. BUG=b:378525209 TEST=Build Pujjoga BIOS image. Ensure that camera is disabled during suspend and enabled during resume. Do the powerd_dbus_suspend and measure the camera power 3.3V which is disable. And resume will recover. Change-Id: I7c7f5d314e8b2a4d5f72c452128f6c4b57c45993 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85133 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-22mb/google/fatcat/var/francka: Add memory DQ mapIan Feng
Follow latest schematics MB_SCH_1102A to add the DQ map. BUG=b:372395010 TEST=emerge-fatcat coreboot Change-Id: I2ea0c5a07d83df108e41fc838e702b793c878096 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-11-22mb/google/fatcat/var/francka: Use RAM ID 1 for MT62F2G32D4DS-020 WT:FAmanda Huang
Change the ram_id to 1 for MT62F2G32D4DS-020 WT:F based on the hardware schematic MB_SCH_1102A. BUG=b:372395010 TEST=Run part_id_gen tool and check the generated files. Change-Id: I8cf0e65036c2da7641f29b2975dece718f7c83e3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85206 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-22mb/google/fatcat/var/fatcat: Enable UFS controllerSubrata Banik
This commit enables the UFS controller on the Google Fatcat mainboard based on FW_CONFIG. This change allows the system to utilize the UFS storage device. TEST=Built google/fatcat with UFS enabled. Change-Id: Ib32523e7865b2ea23d990b2cf9b7406a4d6ecde3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85192 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-22soc/intel/pantherlake: Add option to enable UFS controllerSubrata Banik
This patch adds a Kconfig option to enable the UFS controller for mainboards using the Intel Panther Lake-UH SoC. By default, the UFS controller is disabled as it is not supported by other SoC configurations. This prevents accidental enabling of the UFS controller on unsupported platforms. BUG=b:379828045 TEST=Built google/fatcat with and without UFS enabled. Change-Id: Ica89ae85582367809128fc6cf0cd5fe5d40a2235 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85191 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-22soc/intel/cmn/acpi: Use Kconfig guards for UFS workaroundsSubrata Banik
This change introduces Kconfig guards around the UFS workaround code in the common ACPI ASL file. This ensures that these workarounds are only applied when necessary, allowing future SoCs with UFS controllers to reuse the common ASL file without modification. By using Kconfig, we can enable or disable the workarounds based on the specific SoC configuration, providing greater flexibility and maintainability. BUG=b:379828045 TEST=Able to compile google/fatcat. Change-Id: I968b8811e508378a36648bd8234ff0fd7237b00d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85208 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21vc/google/chromeos/sar: Use size_t instead of int for size functionJeremy Compostella
BUG=b:346600091 TEST=Compilation successful Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e225 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-21soc/mediatek: Rename FREQ_*MHZ to PMIF_TARGET_FREQ_MHZYu-Ping Wu
Enum is useful for improving readability because of the meaningful enum names. Names such as "FREQ_260MHZ = 260", however, don't provide any extra information of the value itself. Therefore, rename those enums to PMIF_TARGET_FREQ_MHZ to better reflect its usage. Change-Id: I420b909a76973a040b96feb2bcb93d3640b086b5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85204 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21soc/mediatek: Rename pmif_ulposc_* function argumentsYu-Ping Wu
Rename the arguments of pmif_ulposc_check() and pmif_ulposc_cali() to make the frequency unit clearer. Change-Id: I7719fd4dc43edd47bf014af13fb57ad38f43778c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-21mb/topton/adl: Add initial support for X2F N100 FW applianceAlicja Michalska
X2F-N100 is an embedded device/firewall with Intel N100 SoC and 4x 2.5Gb Intel I226-V NICs. Currently tested and working: - Payload (EDK2) - Suspend (S3 state) - All USB ports - 4x NICs - M.2 NVME - mPCI-E (WiFi/modem) - 4G USB modem in mPCI-E slot - PCI-E passtrough to VMs (NICs) - HDMI/DP output + HDA audio OS: - Alpine Linux - Windows 11 Pro (from USB) Untested, looks sane: - Internal USB port on M.2 slot marked as "5G_USB" Broken/TODO: - SATA EDK2 reports "Unsupported", drive's not detected. - Suspend in Windows (statements dreamed up by the utterly deranged) Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-11-21superio/ite: Add support for IT8625EAlicja Michalska
Found on tiny firewall appliance from Chinese company named "Topton" with Intel N100 SoC. This system is fanless so all we need is the ability to use serial output (RS232 in RJ45 form-factor, called "Cisco-style" at address 0x3f8), which is working. Change-Id: I9c27f52785d294a6f7c315b8df47d4dd5b389414 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84176 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-11-21mb/google/rauru: Initialize DPM in ramstageJarried Lin
Add initialization of DPM drvier for DRAM low power mode. This DPM flow adds 3ms to the boot time, making the total boot time 860ms. coreboot logs: CBFS: Found 'dpm.dm' @0x19880 size 0x5b7 in mcache @0xfffdd1fc mtk_init_mcu: Loaded (and reset) dpm.dm in 0 msecs (1888 bytes) CBFS: Found 'dpm.pm' @0x19ec0 size 0x7fb5 in mcache @0xfffdd258 mtk_init_mcu: Loaded (and reset) dpm.pm in 3 msecs (43844 bytes) TEST=Build pass. Check with cbmem -1. BUG=b:317009620 Change-Id: Ib855e133a30067fc89c88d5c0fb454cc78504ff3 Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85122 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21soc/mediatek: Rename dpm to dpm_v1Crystal Guo
MT8196 equips new DPM hardware which is different from precedent SoCs. Therefore, we need implement a new DPM loader (said version 2) to run the blob. Considering the version iteration, rename the original dpm to dpm_v1. TEST=Build pass. BUG=b:317009620 Change-Id: I07afb8f5c23e96aad3c6cb0887cb7efd16ebf296 Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-21soc/mediatek/mt8196: Add version two DPM driverJarried Lin
Add version two of the DPM driver for DVFS and DRAM low power feature. MT8196 equips new DPM hardware which is different from precedent SoCs. Therefore, we implement a new DPM loader (said version 2) to run the blob. The new DPM driver includes following features. - Simplify the DPM loading flow without the needs of waking DPM SRAM up and initializing bootargs. - Use the broadcast function to ensure that the DPM load and reset operations performed on channel A will be synchronized to the other three channels. TEST=Full calibration pass. BUG=b:317009620 Change-Id: I77e1ac252b00ab9c4864cc308f20da4a79714e4c Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85121 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-21mb/google/rauru: Fully calibrate DRAMJarried Lin
Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 0) DRAM-K: Fast calibration passed in 1119 msecs TEST=Full calibration pass. BUG=b:317009620 Change-Id: Ibb18675caa11a828d27860eeab48c49acf6b938d Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85120 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-21soc/mediatek/mt8196: Set DRAMC_PARAM_HEADER_VERSION to 3Jarried Lin
Set DRAMC_PARAM_HEADER_VERSION to 3 for aligning with DRAM blob. Test=Bootup pass BUG=b:317009620 Change-Id: I17062bc3b79f60552981d7c604bb5350d8f6199f Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85119 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-21nb/via/cx700/romstage: Include missing static.h headerFelix Singer
Commit 755ecc259c42 ("nb/via/cx700: Implement raminit") is missing an include for static.h and breaks the main branch. Fix it. Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85232 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-21mb/google/nissa/var/glassway: Support HDMI FeatureDaniel Peng
1. Add DB_HDMI_LTE 5 on DB_USB fw_config . 2. Due to refer Nivviks, used GPP_A20/GPP_E20/GPP_E21 as default to set for NF1. Moreover, set to disable HDMI to NC when fw_config not for DB_HDMI_LTE. 3. Set related DB_USB fields to probe correct devices. BUG=b:369509276 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ic5e3b596ff3681f79f31c262e9e59d163e471e3c Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-21nb/via/cx700: Scan PCI bus and probe resourcesNico Huber
Change-Id: I1268a8f886ff395ff822b14a5427a5031260c541 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83389 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21cpu/via/c7: Compress ramstage with LZ4 by defaultNico Huber
It's a slow CPU. Change-Id: I0bf75f410c1d9134f05a2d11b8d011499a7cf794 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82772 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21cpu/via/c7: Use the simple p4-netburst CAR teardownNico Huber
Change-Id: Icba7586145fbfd859d738ecd7a407739a7024ebb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82771 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21nb/via/cx700: Implement raminitNico Huber
This brings the old raminit implementation for CX700 back. It was removed in commit e99f0390b9b8 (Remove VIA CX700 northbridge sup- port). The code is mostly unchanged, three minor issues are fixed: * A shift (>>= 2) was missing when reading tRRD from SPD byte 28. The fixed value matches what the vendor BIOS of a VIA EPIA-EX board programs. The code also suggests that we are looking for a small value (<= 19 for DDR2-533). * We allow the board port to specify which clock outputs should be enabled now. This is necessary for the VIA EPIA-EX, which needs the ALL_MCLKO setting (instead of the previously hard- coded MCLKO2. * When programming the DQS output delays, we considered the 1~2 rank values only for single-rank configurations. Changing the `< 2` to `<= 2` brings us closer to the vendor values on the VIA EPIA-EX. Otherwise a lot of cosmetics changed. Partly because the original code was to be #included into another C file, but also to satisfy checkpatch. Also, all the #if'd code was removed (32-bit width option, ECC, etc.). Change-Id: Ibc36b4f314cdf47f18c8be0fcb98218c50938e94 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-21nb/via/cx700: Implement FSB tuningNico Huber
This northbridge provides a lot of knobs for fine-grained tuning of the FSB drivers. The programming manual calls this "Host AGTL+ I/O Driving Control". We program the known good values for use with a VIA C7 CPU, and warn about use with different CPUs. The numbers were pulled out of raminit of the original CX700 port. Originally, there was a write to 0x83 as well, to set bit 1 which triggers a soft reset of the CPU. It was amidst a table, so it seems unclear if it was put there intentionally. Change-Id: I24ba6cfaab2ca3069952a6c399a065caea7b49f2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-21nb/via/cx700: Perform early bootblock initNico Huber
Disable a timer (GP3) that is always running by default. And enable SMBus, which is useful this early as a console. The SMBus controller is mostly compatible to the Intel one. Change-Id: I77f179433b280d67860fc495605b5764ed081a6c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-21soc/intel/xeon_sp: Fix SRAT debug printsPatrick Rudolph
- Drop duplicated fields - Drop fields filled with constant values - Drop SRAT prefix for sysmemmap entries - Print all zeros when concatenating two hex numbers Change-Id: I379aeb6fcd2e28665c7d592b0639db3c1b4caa9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85189 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21mb/google/nissa/var/telith: Add 6W and 15W power limit parametersRui Zhou
The power limit parameters were defined for 378775630#comment5 by the power team. BUG=b:378775630 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I069869fa01dc157cf2544e72468f43ce1bb64035 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85209 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
2024-11-21mb/google/nissa/var/rull: add RAM ID MT62F1G32D2DS-023 WT:BRui Zhou
Add RAM ID for DDR MICRON MT62F1G32D2DS-023 WT:B BUG=b:378821948 BRANCH=None TEST=boot to kernel success Change-Id: I22e00cffaf6007c64d0c9ffa5f5dde528e3d8952 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-21tree: Remove unused <bootstate.h>Elyes Haouas
Remove "include <bootstate.h>" when it is not used. Change-Id: Ic27acf9f8dfbbccb8f48a139032b1463e7185030 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85216 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-20mb/hp: Add HP Compaq 8300 Elite SFFMichał Zieliński
* Add initial board commit based on HP 8200 SFF and HP Z220 SFF. * Add documentation. Tested on HP 8300 SFF. Change-Id: Ib5322acc0210f000b53954e2925549358f86d5c8 Signed-off-by: Michał Zieliński <michal.zielinski@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67666 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
2024-11-20mb/ocp/tiogapass: Only advertise C-states C1C6Patrick Rudolph
Only advertise C-state C1 and C6. TEST: On ocp/tiogapass Linux no longer complains about advertised but unsupported C-states. Change-Id: I184c337478f97e2d36f6e89b764dbe1da1b91697 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85190 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-20soc/intel/pantherlake/acpi: Update camera_clock_ctl.aslBora Guvendik
Fix ISCLK register definitions Reference: 813032 - Panther Lake H I/O Registers BUG=b:357011633 TEST=check camera functionality on fatcat Change-Id: Ie9f1f639970344eb359dee37914ee26a02dcfb4b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85058 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-11-20soc/intel/ptl: Update ME specification version to 21Pranava Y N
This patch updates Kconfig that selects ME specification version for Pantherlake SoC from version 18 to version 21. BUG=b:362647201 TEST=Able to build fatcat with SOC_INTEL_COMMON_ME_SPEC_21 selected. Change-Id: Ibfebd7c093240aa7f1d6337f3e4dd6e5d34bed1d Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85187 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-20common/block/cse: Add Kconfig to support ME specification version 21Pranava Y N
This patch introduces Kconfig support for Intel's Management Engine (ME), version 21. When 'SOC_INTEL_COMMON_BLOCK_ME_SPEC_21' is selected it sets the ME_SPEC configuration to 18 because ME version 21 is compatible with version 18 in terms of Host Firmware status registers. BUG=b:362647201 TEST=Able to build fatcat after selecting SOC_INTEL_COMMON_ME_SPEC_21 Change-Id: I90c946751ac530dac1af4ff9c3c921b5faf82448 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-20device: Add const qualifier for input of dev_is_active_bridgeShuo Liu
Add const qualifier for input of dev_is_active_bridge so that dev_is_active_bridge could be used for both struct device * input and const struct device * input. TESTED=Build and boot on intel/avenuecity CRB Change-Id: Ia4231534c87cd13d4e6e4d606733f9eb11221ac1 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-11-20soc/intel/pantherlake: Enable CPU feature programming in corebootSubrata Banik
This patch enables coreboot to perform CPU feature programming for both the Boot Strap Processor (BSP) and Application Processors (APs) on Intel Panther Lake platforms. This change eliminates the need for the following FSP modules: - CpuMpPpi - CpuFeature By handling CPU feature programming within coreboot, we reduce reliance on external FSP binaries and improve code maintainability. BUG=b:376092389, b/364822529 TEST=Built and booted google/fatcat successfully. Verified CPU features are correctly programmed. Change-Id: I73321485327f6a02ec8338fcfa1faf1e71008ba6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-11-20mb/google/fatcat: Create felino variantTongtong Pan
Create the felino variant of the fatcat reference board by copying the fatcat files to a new directory named for the variant. BUG=b:379797598 TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a make sure the build includes GOOGLE_FELINO 2. Run part_id_gen tool without any errors Change-Id: Iff7989c19e775d65d5fb04aa4489854150390a35 Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85185 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-19soc/intel/xeon_sp: Walk devicetree to find IOAPICsPatrick Rudolph
Walk the devicetree to collect all PCI IOAPICs. When found read the IOAPIC base address from hardware. TEST: On ocp/tiogapass all IOAPICs are found and advertised. Change-Id: I2835c202e56849655795b96bc83862cb18e83fc0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84851 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-19soc/intel/xeon_sp/cpx: Fix PCU device IDsPatrick Rudolph
CPX uses the same PCU IDs as SKX. Change-Id: I1bc96232e120b9cd9cb4f5b7b5df7d7db62fcbc4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84852 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-19soc/intel/xeon_sp: Fix VTD addressPatrick Rudolph
On 1st and 2nd gen Xeon-SP the VTD PCI device is not at DEVFN 0.0. Fix the DEVFN address and thus fix an assertion in vtd_probe_bar_size(). Change-Id: Ie879e95436af92fca1fee49135938ca2b005d579 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-19soc/intel/xeon_sp: Drop DMAR_X2APIC_OPT_OUTPatrick Rudolph
Drop DMAR_X2APIC_OPT_OUT since coreboot is able to enable X2APIC. TEST: Works fine on OCP/tiogapass, thus drop the opt out. Change-Id: Ia0443a39a9bf392976cfd1a7ccf6a335d5f0bd70 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-19soc/intel/xeon_sp/acpi/gen1: Properly set _PXMPatrick Rudolph
Set _PXM in ACPI to indicate which socket the PCI domain belongs to. TEST: Booted on 2S ocp/tiogapass and checked dmesg that PCI domains are advertised in the correct Proximity Domain. Change-Id: I39cec0307b0dce0a4da5df5be5095b8d90758997 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-19mb/ocp/tiogapass: Enable GBE and 10GBE regionPatrick Rudolph
Enable GBE and 10GBE region since it's used on vendor firmware. TEST: Able to include gbe.bin and 10gbe.bin blobs into ROM. Change-Id: Ia868d6b42e5e557d2abd60be4b2f318a1313b039 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85171 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-19soc/intel/xeon_sp: Read IOAPIC ID from hardwarePatrick Rudolph
Currently coreboot hardcodes the same IOAPIC IDs as used on UEFI native, however FSP does not program the IOAPIC IDs, except for PCH IOAPIC. Drop existing code that hardcodes PCI addresses and IOAPIC IDs and detect the IOAPIC inside the domain automatically, read the IOAPIC base address and let existing code figure out the IOAPIC ID by reading it back from HW. Change-Id: I2543a46dcc4a98ec8629530ca87882a7106c9ed1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84850 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-19soc/intel/xeon_sp: Drop unused codePatrick Rudolph
Drop soc_get_stack_for_port() and move a comment. Change-Id: I9d7615b633b344783150b3e1f3d98634630ed354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84844 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-19soc/intel/common/block/gpmr: Disable GPMR regs if ext-BIOS is disabledYuchi Chen
General Purpose Memory Range registers are only used if extended BIOS region is enabled now, this patch wraps the related code with Kconfig item `CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW`. Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-19soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRYuchi Chen
ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning PIRQ for a given device and INT pin. Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-19drivers/wifi: Remove unnecessary data structure copyJeremy Compostella
The current design has the emit_wifi_sar_acpi_structures() function load and unload the SAR binary. Since DSM and Bluetooth SAR data structures are used outside this function, they are being copied into data structure located in the calling function stack. This overhead is unnecessary as loading and unloading the SAR binary could be done by the calling function. In addition, we are about to add several Bluetooth related data structures which, under the current design, would require to add even more data structure copy operations. BUG=b:346600091 TEST=Wifi/Bluetooth SAR ACPI tables are identical before and after this commit Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e207 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-19mb/google/brya/var/orisa: Update Type C DisplayPort HPD ConfigurationVarun Upadhyay
This change removes the GPIO configuration for Type C DP HPD, as the Type C port does not require HPD setup. BUG=b:366156678 TEST=Build and boot google/orisa. Test Type C port for external usb and DisplayPort functionality. Change-Id: I59ec5c19dbbd053bda25f4260321220524d785b3 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-19mb/google/brya/var/trulo: Update Type C DisplayPort HPD ConfigurationVarun Upadhyay
This change removes the GPIO configuration for Type C DP HPD, as the Type C port does not require HPD setup. BUG=b:366156678 TEST=Build and boot google/trulo. Test Type C port for external usb and DisplayPort functionality. Change-Id: Iad602c9a15c65d37a37d06d486843f45e341b6bc Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85180 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-19mb/google/brox: Reset XHCI controller while preparing for S5Karthikeyan Ramasubramanian
This patch calls `xhci_host_reset()` function to perform XHCI controller reset. This is proactively pulled in to avoid any potential timeouts when PMC sends an IPC command to disconnect the active USB ports. BUG=b:364158487 TEST=Build Brox BIOS image and boot to OS. Perform warm reset, cold reset and suspend/resume cycle. Change-Id: I33fd3aa13e81c7b1ae1ebf6674cc8ac1437ecc03 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com>
2024-11-19tree: Remove unused <assert.h>Elyes Haouas
Remove <assert.h> when it is not used. Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-19soc/qualcomm/sc7280/socinfo: Add missing <console/console.h>Elyes Haouas
This to fix Wimplicit-function-declaration error: src/soc/qualcomm/sc7280/socinfo.c:67:2: error: call to undeclared function 'die'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 67 | die("could not match jtagid\n"); | ^ src/soc/qualcomm/sc7280/socinfo.c:81:2: error: call to undeclared function 'die'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 81 | die("could not match jtagid\n"); | ^ Change-Id: If930e39d0c7231975c1a11179fa7dbd9fcc0d1d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85166 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18vendorcode/intel/fsp/skx_sp: Fix PCI domain scanningPatrick Rudolph
Properly scan all logical stack when creating PCI domains. Fixes PCI bus ranges being used on other stacks, since they look unused, as not all stacks are checked. Change-Id: I13c8b389a585dbccec182d3c98021f1d9d648b2c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-18mb/ocp/tiogapass: Fix GPIOsPatrick Rudolph
Do not enable SMIs on GPIOs since there's no SMI handler. Without an SMI handler this will just slow down the platform once the SMI asserts since it's never cleared. Once the protocol between BMC and x86 has been implemented in an SMI handler, this can be reverted. TEST: Booted on OCP/tiogapass without massive slowdown when SMIs are enabled. Change-Id: If16c2c427f9b160f78a768a01a60128a6ed2c53f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2024-11-18mb/google/nissa/var/rull: add RAM ID H58G56BK8BX068Rui Zhou
Add RAM ID for DDR Hynix H58G56BK8BX068 BUG=b:378821948 BRANCH=None TEST=boot to kernel success Change-Id: I4c4ad191a5e9703ee0f3bed150c816bfb098daf5 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85117 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-18mb/google/rex/var/kanix: Add USB A1 port supportTyler Wang
BUG=b:366291025 TEST=emerge-rex coreboot pass Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-18mb/google/rex/var/kanix: Add audio codec/amp supportTyler Wang
Add support for Realtek audio codec ALC5682I-VS and Realtek audio amp ALC1019. BUG=b:366291025 TEST=emerge-rex coreboot pass Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85100 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18mb/google/rex/var/kanix: Add initial overridetree settingsTyler Wang
Update initial overridetree settings, it's basically copied from karis. This patch includes: 1. USB port related settings 2. Display Port Configuration 3. DPTF settings 4. PCIE settings for NVME 5. Settings of MIPI camera HI556 6. Settings of ELAN9004 touchscreen 7. Settings of ELAN and PIXA touchpad 8. PCIE settings for WLAN card 9. Settings of NUVOTON FPMCU BUG=b:368501705 TEST=emerge-rex coreboot pass Change-Id: I468ca388f495b2e527841145f8162b21074058cc Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-18mb/google/rex/var/kanix: Add initial GPIO configTyler Wang
Initial GPIO config for kanix, it's copied from karis. Will update more GPIO config in future. BUG=b:368501705 TEST=emerge-rex coreboot pass Change-Id: Id23b836b48925a30b212b444c9f51cfd6166b9f8 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85042 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18mb/google/rex/var/kanix: Generate SPD ID for supported memory partTyler Wang
Add kanix supported memory parts in mem_parts_used.txt, generate SPD id. 1. MICRON MT62F1G32D2DS-023 WT:B 2. HYNIX H9JCNNNBK3MLYR-N6E 3. HYNIX H58G56BK8BX068 4. SAMSUNG K3KL8L80CM-MGCT 5. MICRON MT62F512M32D2DR-031 WT:B BUG=b:378390643 TEST=Use part_id_gen to generate related settings Change-Id: I6ce92bac8d8e7ed64135c26387f52b7cc488c391 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85040 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18mb/google/fatcat/var/francka: Add overridetreeIan Feng
Add override devicetree based on schematic_20241104. BUG=b:376245884 TEST=emerge-fatcat coreboot Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-11-18mb/google/fatcat/var/francka: Configure Kconfig for franckaIan Feng
1. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka. 2. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka. 3. Set TPM I2C bus to 0x01 for francka. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I5890a1f02ef88c591973c71a2adb2bba889733e7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85115 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18mb/google/fatcat/var/francka: Update gpio settingsIan Feng
Configure GPIOs according to schematics_20241112. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-11-18mb/google/trulo: Fix invalid GPE route configurationKapil Porwal
GPE route for GPE0_DW0 was not being programmed (i.e. 0) which made it route to GPP_B since a value of 0 means GPP_B. GPE route for GPE0_DW1 is also being programmed to GPP_B which makes the overall configuration invalid. The fix is to program the GPE0_DW0 route to a GPIO group which is not already being used for GPE0_DW1 & GPE0_DW2 i.e. GPP_A. Additionally, the common GPE route configuration is moved to baseboard. BUG=b:378455259 TEST=Verify wake from S0ix when charger is connected Change-Id: I674cf7db160b6bc1ec3d620f9c99ea91041c48bb Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85157 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-18soc/intel: Assert if `pmc_/gpe0_dwX` values are not uniqueSubrata Banik
This commit adds an assertion to ensure that the values of pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the soc_intel_<soc>_config structure are unique. This check helps to catch potential configuration errors early on, preventing unexpected behavior during system initialization. TEST=Built and booted normally. No assertion failure observed. Able to catch the hidden issue due to overlapping Tier 1 GPE configuration. [DEBUG] CPU: Intel(R) Core(TM) 3 N355 [DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a [DEBUG] CPU: AES supported, TXT supported, VT supported ... ... [DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N [DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU [DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1 [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c', line 163 Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-18soc/intel/pantherlake: Reduce memory test sizeSubrata Banik
Enable upd to reduce size of the memory test. TEST=Able to build and boot google/fatcat. w/o this patch: 951:returning from FspMemoryInit 3,452,595 (365,930) w/ this patch: 951:returning from FspMemoryInit 3,442,823 (353,928) Change-Id: I67f10e234019e260923a28a2d71b83786dcb39ee Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-18soc/intel/pantherlake: Bind SoC config to LowerBasicMemTestSize UPDJeremy Compostella
The lower_basic_mem_test_size SoC setting (LowerBasicMemTestSize UPD) request FSP-M to reduce the size of memory tested after memory training. This option reduces the boot time. This is considered a safe option to enable on a well validated board. BUG=b:357011633 TEST=LowerBasicMemTestSize UPD is set when lower_basic_mem_test_size is set Change-Id: I465e9c138ac8f2079bfd506add4667201a8fa533 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85130 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18Documentation/acronyms.md: Add some acronymsMaximilian Brune
These acronyms have been found while looking at the datasheet of the JH7110 RISC-V SOC. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I82104b88e7723b73810f20d5f4dffe6ed8a9ab78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83847 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-17soc/mediatek/common/include/soc/mcu_common: Include <types.h>Elyes Haouas
Include missing <types.h>. Change-Id: I04d18e601e010b64c46f2eb52874d3eb5664b0e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-17mb/ocp/tiogapass: Fix build failurePatrick Rudolph
Add console.c to SMM stage as well. Fixes the build failure: "undefined reference to `get_uart_baudrate'" when CONFIG_DEBUG_SMI is set. Change-Id: I2587287b0074a56c49b7434553c69cae97aaa1b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-17drivers/intel/gma/acpi: Limit OpRegion sizePatrick Rudolph
Limit the ACPI OpRegion to cover only MBOX3. This seems to fix BSOD errors seen on Windows 10/11 as reported at [1]. 1: https://ticket.coreboot.org/issues/327 Change-Id: Ia2affa799e5cd84c0a03330e0f78919755f0e8ac Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81295 Reviewed-by: Joel Linn <jl_coreboot@conductive.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-16tree: Remove unused <console/console.h>Elyes Haouas
Remove unused include <console/console.h>. Change-Id: I2a7cafd7b755a5c3e2bbfa9fc814bf2686c1ccf1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85163 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16device: Add helper to identify PCI IOAPICsPatrick Rudolph
Add a helper function to identify PCI IOAPICs. Will be used in the following commits. Change-Id: Ibe50934260b025575440fd52eace73fe2327a193 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-16soc/intel/xeon_sp/skx: Load microcodePatrick Rudolph
Update microcode on BSP before MPinit and on all APs if necessary. When the APs already have a MCU loaded, MPinit will skip the update. This aligns the code with other platforms that attempt to update the microcode in MPinit even when FIT already has loaded a MCU. Drop the UPD PcdCpuMicrocodePatchBase to prevent FSP-S from updating MCU before MPinit runs. Reduced code differences between SKX and CPX and will allow to merge the codebase into one. Change-Id: I7df6f82055a879a738fd29092e750084557bbd5c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84848 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp/skx: Use Kconfig symbolPatrick Rudolph
Use Kconfig symbol CPU_BCLK_MHZ as done on CPX. Reduced code differences between SKX and CPX and will allow to merge the codebase into one. Change-Id: I8a0a51d4280e4370e0e8695f8b9d8f2ed943d9e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-16soc/intel/xeon_sp/skx: Lock PMC in post_mp_initPatrick Rudolph
Since SKX and CPX are using the PCH, copy the code from CPX and lock the PMC in the same place. Reduced code differences between SKX and CPX and will allow to merge the codebase into one. Change-Id: I9495456fc2650b25ba164b336dc10ea0b88989aa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84846 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp: Reduce code differencesPatrick Rudolph
Use get_platform_thread_count() instead of duplicated get_thread_count(), that is also less precise. Change-Id: I70c095c284aab6898b8351e82243f534963f333b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84845 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp/skx: Lock all PCU registersPatrick Rudolph
Lock all PCU registers on all sockets. The same code can be found on CPX, which is basically the same CPU. Once the differences between CPX and SKX are minimal, the platforms can be merged into one codebase. Change-Id: I73eaa0905e8a418fc9dfe515c42cd257c041cf61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84843 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-15mb/google/nissa/var/telith: Add Fn key scancodeKun Liu
The Fn key on telith emits a scancode of 94 (0x5e). BUG=b:372506691 TEST=Flash telith, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Ib69af9a8448312b275de46f9c835f8a9d592312a Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85045 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-15mb/google/nissa/var/telith: Add 6W and 15W DPTF parametersKun Liu
The DPTF parameters were defined by the thermal team. Based on thermal table in 377955793#comment2 BUG=b:377955793 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-15mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configurationSubrata Banik
This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to accommodate different hardware configurations. Specifically, GPP_E07 is not connected (NC) on google/fatcat boards with the Microchip EC AIC. However, it is required for google/fatcat boards with Nuvoton/ITE AICs. BUG=b:378603337 Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85106 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-15mb/google/brox/var/jubilant: Add fw_config for WWAN Sar SensorRen Kuo
The current WWAN(LTE) does not require any sar setting from RF team's suggestion, and sar sensor will be removed from DVT schematic. To reserve the extendibility, add the fw_config DB_1A_LTE_SAR: field DB_USB 11 12 option DB_1A 0 (None LTE) option DB_1A_LTE 1 (LTE without sar sensor) option DB_1A_LTE_SAR 2 (LTE with sar sensor) end Base on the fw_config to enable/disable related functions: 0)Disable WWAN and Sar if DB_USB = DB_1A 1)Enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE 2)Enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR BUG=b:375341992 TEST=Build and verify on jubilant by DB_USB= 0,1,and 2 of fw_config Check sar sensor and WWAN module from commands: ls -l /sys/bus/i2c/devices i2cdetect -y -r lsusb Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85107 Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-14southbridge/intel/common: Improve ACPI _PRT method generationYuchi Chen
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be reused for multiple domains. Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 14:59:10 +0000