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2023-11-20mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE". Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/skolas: sync slolas overridetree with brya0Nick Vaccaro
Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20sbom/Makefile.inc: Change GOPATHMaximilian Brune
This changes the path where go installs its packages. Now the packages are not installed in the users home directory anymore. This solution is not perfect though, since offline build are still not possible, because go will fetch the packages at build time. -modcacherw will create the go files with rw permissions, otherwise coreboot is not able to delete the files afterwards (make distclean). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2a35369628454057ea4758cd1225e57f07cb71c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-20mb/google/geralt: Remove unnecessary delay for MIPI panelYidi Lin
According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms delay after VDD powering on. The MIPI panel[2] does not need this delay. Move this delay to eDP path. [1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf [2] B5 TV110C9M-LL0 Product Specification Rev.P0 BRANCH=none BUG=none TEST=check FW screen TEST=check timestamp Before: 60:device initialization 696,422 (1) 15:starting LZMA decompress (ignore for x86) 696,587 (165) 16:finished LZMA decompress (ignore for x86) 696,675 (88) 17:starting LZ4 decompress (ignore for x86) 1,340,226 (643,551) After: 60:device initialization 724,259 (1) 15:starting LZMA decompress (ignore for x86) 724,425 (166) 16:finished LZMA decompress (ignore for x86) 724,512 (87) 17:starting LZ4 decompress (ignore for x86) 1,168,176 (443,664) Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-20cross-repo-cherrypick: Update downstream branchJon Murphy
ChromeOS has switched to using the main branch, update accordingly. BUG=b:294218930 TEST=None Change-Id: I31f67ef4fb175a4e4896b5bed81d5ae1cdddb827 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79143 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-19Documentation/releases: Add 24.02 release notes templateMartin Roth
In preparation for the upcoming release, add the template for the 24.02 release and update index.md. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I694142c31ba684e7b94640d55302b2440e25619a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79073 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetreeFelix Held
Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and audio still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetreeFelix Held
Since the PCIe root ports in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are visible and working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18nb/intel/sandybridge: assign gma ops in chipset devicetreeFelix Held
Since the integrated GPU is always function 0 of device 2 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and graphics works in UEFI Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18nb/intel/sandybridge: assign host bridge ops in chipset devicetreeFelix Held
Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18util/lint: Add linter to keep selects out of Kconfig.nameMartin Roth
While having select statements in Kconfig.name files is valid in the syntax of the Kconfig language, having the selections split between the normal Kconfig file and Kconfig.name files makes it harder to see what's going on. Kconfig.name files will now be limited to their original purpose of selecting a particular board or board variant, not actually configuring that board. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2aab78e296f2958e77a938b1afa40a25a6aa82b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-18mb/google/brox: Use Ti50 configShelley Chen
Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18mb/google/brox: Fix GPIO assignments in gpio.hShelley Chen
Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE configurations so that they are mapped to the proper wake sources (GPP_B, D, E groups). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18qualcomm/sc7180: Move QCSDI and increase romstage size by 4KBJulius Werner
We need to increase romstage size a little to make a compiler upgrade fit (CB:70771). Unfortunately the end of the romstage directly touches the QCSDI region in the current memlayout, and there is no other way to reshuffle things to make more space... so we need to move QCSDI out of the way. This means that anyone who is actually building this platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob that's not publicly available) will need to recompile their QCSDI binary to match the new start address. Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-18Docs/releases: Update 4.22 release notesMartin Roth
These should be the final release notes prior to tagging coreboot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id723f8e1fc92ef1a36e877f48e594eef59b0ba8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79077 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17docker/coreboot-sdk: Add perl modules for gcovMartin Roth
These perl modules are needed to run the coverage-report target for gcov. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If32a42ce17edcbae94394f770c26d3300abebcbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/79072 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17Docs/security/vboot: Update list of boards with vbootMartin Roth
Update the vboot board list for the 4.22 release. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I77c5ca2c2c36d8b1ddadad4f15d2d4148ff0b325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-11-17mb/google/herobrine: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17mb/google/trogdor: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-17soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17nb/amd/pi/00730F01: add CPU and domain ops in devicetreeFelix Held
Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-17nb/amd/pi/00730F01: restructure chip opsFelix Held
Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17nb/amd/pi/00730F01: introduce and use chipset devicetreeFelix Held
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17include/device/device: drop HAVE_ACPI_TABLES guardsFelix Held
There's no need to remove the corresponding fields from the device_operations struct when HAVE_ACPI_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17include/device/device: drop GENERATE_SMBIOS_TABLES guardsFelix Held
There's no need to remove the corresponding fields from the device_operations struct when GENERATE_SMBIOS_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17mb/google/corsola: Configure I2C and I2S interface for ALC5650wuyang5
Configure I2S1 and I2C5 for ALC5650 to support beep sound in depthcharge. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-17MAINTAINERS: Add Dinesh Gehlot as MTL SOC and GOOGLE REX MB maintainerDinesh Gehlot
Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-17mb/google/zork/morphius: Drop touchscreen detectionMatt DeVillier
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO for touchscreen power/enable, and so fail with runtime detection enabled. Since it only has one touchscreen option, and no SKUs lack a touchscreen, we can safely assume it is present in all cases. TEST=build/boot morphius w/4k screen, verify touchscreen enabled in cbmem and functional in Linux and Windows. Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16util/docker: Switch back to root user in jenkins-nodeMartin Roth
Leaving the user as coreboot caused the entrypoint to run as coreboot, which means we couldn't mount directories or run sshd correctly. Switching to root at the end of the file fixes this. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79067 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16util/ifdtool/ifdtool.c: Add NULL check for fmapnameMaximilian Brune
Some boards (e.g. prodrive/hermes) that do not provide their own FMAP and therefore have been generated by the build system (+ ifdtool) experience a failure when trying to build with an IFD that contains regions which do not have equivalent fmap names (set to NULL). Therefore add a NULL check for the fmapname and ignore the region if we do not have an fmapname. Test: compile prodrive/hermes Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-11-16ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hSimon Glass
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16acpi/device: Only return dev->ops->acpi_name if non-NULLCoolStar
Returning a NULL device name can cause issues if something else does handle it. E.g. UART and GNA devices on Intel Alder Lake-N cause INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid packages being created from a NULL name Test: build/boot google/nissa (craaskvin) to Win11 Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-16mb/google/skyrim/frostflow: Drop GPIO override for camera shutterMatt DeVillier
Appears to not be used under Windows, Linux, or ChromeOS, and causes high CPU usage at idle under Windows. BUG=none TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter function unchanged, CPU usage under Windows idles where expected. Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16Revert "tests: Allow specifying vboot source directory"Felix Singer
This reverts commit 7713a2f295d9ed9a7023a78e085ce190ee1203fe. Reason for revert: breaks main branch Change-Id: I2749bea9369c222e510b838e278c7797d5dce56e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78852 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-11-16Update amd_blobs submodule to upstream main branchMatt DeVillier
Updating from commit id edd465837e26 (2023-10-20): cezanne: Update PSP binaries to release 0.11.11.75 to commit id e4519efca746 (2023-11-15): Revert "picasso: Update PSP binaries to release 0.8.13.7B" This brings in 1 new commit: e4519efca7 Revert "picasso: Update PSP binaries to release 0.8.13.7B" Change-Id: I860aa04324128199cbc91a5f310fcdf92a2cd65d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16mb/system76/rpl: Allow 5600 MT/s memory for RPL-HXMatt Parnell
System76 only sells units with memory speeds up to 5200 MT/s, but the i9-13900HX supports up to 5600 MT/s memory. Tested by running memtest and checking dmidecode reports 5600 MT/s when using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3, bonw15, serw13. Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Signed-off-by: Matt Parnell <mparnell@gmail.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16mb/supermicro/x11: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16tests: Allow specifying vboot source directoryroccochen@chromium.com
Respect VBOOT_SOURCE while including generic headers. BUG=none TEST=make clean-unit-tests && VBOOT_SOURCE=/path/to/vboot_reference/ make unit-tests -j TEST=make clean-unit-tests && make unit-tests -j BRANCH=none Change-Id: Id3bb3726c91167d2dd648d748763a3948787f28d Signed-off-by: roccochen@chromium.com <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78849 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16mb/google/geralt: Disable SD card support for CiriRuihai Zhou
According to proto schematics, the SD card is removed. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-16mb/google/geralt: Move backlight-related functions to common panel.cRuihai Zhou
These backlight related functions can be reused in other variants, move them out to the panel.c. Also the panel_geralt.c should be used for Geralt, enable it on Geralt board only. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-11-16lib/device_tree.c: Fix print_propertyMaximilian Brune
This uses the size attribute to traverse the possible string. This patch traverses the entire property for non printable characters and not just until the first 0 is hit. Now numbers that start with a zero (memory wise) are not falsely recognized as strings: before the patch: clock-frequency = ""; after the patch: clock-frequency = < 0x1c2000 >; Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I229c07b76468fe54f90fa9df12f103d7c7c2859d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16drivers: spi_flash: Add space before colon to fix coding styleTyler Wang
BUG=none TEST=build karis firmware pass Change-Id: I67b4ca4c8fde795d4206eaa0b9ea9d9bfc768ac6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-16mb/google/geralt: Create variant CiriRuihai Zhou
Create the variant Ciri and enable MAX98390 AMP for it. The panel related support will be added in the follow up CLs. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78954 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-16mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variantUsha P
This patch creates a new variant mtlrvp4es_p_ext_ec. The new variant will support ESx samples. The existing mtlrvp_p_ext_ec variant will support the QS samples. BUG=b:310775573 TEST= Build and boot mtlrvp4es_p_ext_ec. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Iad72c0f6343af149d16d8b1f8639ba496f6aab0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-16lib: Update locales for non-VBOOT platformsSubrata Banik
This patch sets the default locales to English for platforms that do not have support for VBOOT configuration. This ensures that the system will use English locales if the platform does not provide its own locale settings. TEST=Built and booted the google/rex platform successfully. Change-Id: I7554c8bfd58411f460deeb22cf7218059ca8ba9f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79054 Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16tests/lib: Enforce ux_locales-test with CONFIG_VBOOTSubrata Banik
The ux_locales-test relies on the ability to determine supported locales for the platform. However, this information is unavailable without VBOOT config being enabled. Therefore, enforce this test for platforms with VBOOT config alone to avoid unnecessary failures. Change-Id: I2828eb062e2b601e073e7dab9aef7316fc6ba2cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16mb/google/brya/var/osiris: Update power limit values for RPL CPUDavid Wu
Update power limit values based on the suggestion of the thermal team for RPL CPU. The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W). BUG=b:310834985 TEST=built and booted into OS. Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-15acpi/acpigen: drop len assert in acpigen_pop_lenFelix Held
This is already handled as a separate case in the code below, so there's no need for this assert any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTESFelix Held
Use a define instead of magic numbers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15acpi/acpigen: rework acpigen_pop_len for different size PkgLengthFelix Held
Previously acpigen_pop_len always wrote a 3 byte PkgLength to the 3 bytes reserved by acpigen_write_len_f. After this patch acpigen_pop_len encodes PkgLength in 1-3 bytes depending on the PkgLength. When less than the 3 bytes that were previously reserved in the corresponding acpigen_write_len_f call are needed for PkgLength, the payload data will be moved back by the number of reserved bytes that aren't needed for the PkgLength. This fixes the problem that the Windows AML parser doesn't like a 3 byte PkgLength being used for the size of the buffer containing UTF-16 strings when the length could be encoded in a single PkgLength byte. In that case, Windows previously ignored the whole SSDT containing this larger than necessary PkgLength encoding. It should however be noted that the ACPI 6.4 spec doesn't specify if it's required to always use the most compact possible encoding of the PkgLength or not. Since iasl generates the shortest possible PkgLength encoding, it's also a good idea to make coreboot's acpigen do the same although it's not required by the specification. With this patch applied, Windows still boots on Mandolin and the time it takes to write the tables doesn't change. To measure the times, the log level in bs_sample_time was increased to BIOS_CRIT and the console log level was increased to BIOS_CRIT too to only get those times as output. BS: BS_WRITE_TABLES run times (exec / console): 8 / 0 ms Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib897b08a05a7cdc52902d51364246c260ea1f206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-15soc/amd/genoa: Add mmio.aslVarshit Pandya
This patch adds asl code for MMIO device like I2C, UART, GPIO etc. Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>t show Reviewed-on: https://review.coreboot.org/c/coreboot/+/78895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-15mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-ADaniel_Peng
Add support for the new memory CXMT CXDB4CBAM-ML-A. BUG=b:304932936 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" And confirm the mainboard boot normally with CXMT CXDB4CBAM-ML-A memory. Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-15soc/qualcomm/{sc7180,sc7280}: Use correct return types for functionsZebreus
Some functions in the headers for sc7180 and sc7280 specified the int as their return type when they should have used enum cb_err. Found while testing GCC 13.2.0 Change-Id: I41331fe708a396f7f2f40359e8ba03c8a46a4d4b Signed-off-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-15arch/arm64: Avoid GCC warning about out of bounds array accessZebreus
With the update to GCC 13 a new warning about subtracting numbers from arrays appears. src/arch/arm64/armv8/mmu.c:296:9: error: array subscript -1 is outside array bounds of 'u8[]' {aka 'unsigned char[]'} [-Werror=array-bounds=] Change-Id: I4757ca2e7ad3f969d7416041ea40c3e9866cdf49 Signed-off-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79014 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-14soc/intel/cannonlake: Drop entries from soc_acpi_name()Matt DeVillier
The THRM and SATA PCI devices do not currently have any ACPI devices defined, so drop them from soc_acpi_name() so they do not end up in the LPI constraint list. This eliminates the following errors under Linux: AE_NOT_FOUND: _SB_.PCI0.THRM AE_NOT_FOUND: _SB_.PCI0.SATA TEST= build/boot google/hatch (jinlon) and verify no ACPI errors. Change-Id: I3827b152644e2eaecc1ad288d441d2dad4d76ccb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79013 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-14nb/intel/sandybridge: Drop raminit_native.hKeith Hui
After commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), no boards use this header anymore and it no longer offers original content. Adjust northbridge code #includes as needed and drop it. Change-Id: I2785e920bd6188dbfc1a6157351083ec4a2526d0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-14mb/apple/macbookair4_2: Drop obsolete spd.bin fileKeith Hui
After commit 940fe080bf1e (mb/apple/macbookair4_2: Correctly implement SPD mapping the Haswell way), this file is obsolete and can be removed. Change-Id: I5afe6809c7097ab8529a3c1ec7befbd0d6f01c5f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-14mb/lenovo/t530/early_init.c: Drop unused and revise used includesKeith Hui
With commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), raminit_native.h now only includes 4 other headers and offers no original content. Based on the idea that all source files should include what they use directly, drop it in favor of sandybridge.h (which it already includes anyway) and types.h (replacing stdint.h because it also uses boolean constructs). Board appears to not use anything sb/intel/bd82x6x/pch.h provides. And the board still builds after dropping it. Change-Id: I1b201fe4dd29bac5feb08f372d1e36353eac161d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78783 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-14mb/google/brox: Set unstuffed straps to NCShelley Chen
All of these signals have net names, but are actually unstuffed, so we have to set them to NC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-14cpu/intel/model_2065x: Read CPU voltage for SMBIOSPatrick Rudolph
Report smbios_cpu_get_voltage() on Sandy Bridge as well. Change-Id: I13ea930a58eaedc24d69fa3790f1f2a151558a80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78432 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-14soc/intel/cmn/block/cse: Support sending EOP from payloadKapil Porwal
Skip sending EOP from coreboot when payload is sending it. BUG=b:279184514 TEST=Verify sending EOP from depthcharge on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fbb9fd0f8522eefad39960ca3167c2ba764f523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74765 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-14mb/google/eve: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I866250602701e7e83a695d346f4b404b1bbae6d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-14mb/google/glados: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I4f2c4f4a576ea2fd2ccb7a7e6b52cf258bac5f84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79043 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/protectli/vault_kbl: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ie25c56f48648733095ab9d2a565c842b2f90efb2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79041 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/kontron/bsl6: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic25d112a95903e77b58bda70bbcc3f08df383395 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13mb/purism/librem_skl: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: If4f89fb81664474e03ab0ade76cfbd617127127e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79040 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/intel/kunimitsu: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I413a3630bda841ae9ed6c4a584d2250a81c28308 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/intel/saddlebrook: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic4043828baf43d14f7f2060fa3946e3a9e2008fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79038 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/acer/aspire_vn7_572g: Make use of the chipset devicetreeFelix Singer
The comments related to the PCI devices are superfluous since the reference names from the chipset devicetree are used. So remove the comments and also the devices which are turned off, or in general have an equal state compared to the configuration in chipset devicetree. Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic45446b03a3c571837fc1c41f55d60bdf2a25a7e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/facebook/monolith: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib1adeaf4745804dfc91f99fb4e4491b68631202c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/lenovo/x220: Update devicetreePatrick Rudolph
- Disable unconnected PCH PCIe ports 1 + 3. - Add smbios_slot_desc to WLAN PCIe port - Add comment for PCIe port 7 that might have a XHCI controller connected (some variants only). Test: Lenovo X220 still boots and all devices are still working fine. The WLAN slot is shown in dmidecode -t 9. Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-11-13mb/libretrend/lt1000: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I6ba850c783999d06c73137ed77d32fc108a20347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/starlabs/starbook/kbl: Use chipset dt reference name for LPCFelix Singer
Change-Id: I41b3ed4926fe77c5729672fd7a7bcb8ca0c5c216 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79033 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/hp/280_g2: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib6edae61fb904143c3b3994df812524a258fa9f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13mb/asrock/h110m: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I9f92246da4a500e85c878d865d621033f6b35f1b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13nb/intel/sandybridge: Clean up post Haswell SPD mapping API migrationKeith Hui
With migration to Haswell SPD mapping interface complete: 1. Remove weak stubs meant to ensure smooth transition and internalizes mainboard_get_spd() within raminit.c. 2. Remove post-mainboard SPD data sanitization code in raminit_mrc.c, now that it fills its own SPD data. 3. Remove old prototypes from raminit_native.h 4a. Drops raminit_native.h from raminit.c, as individual headers therein are already included. 4b. Drop another header from raminit.c IWYU identified as unneeded. asus/p8z77-m still builds afterwards. (sandybridge to receive a full IWYU cleanup later.) Change-Id: Ie073c1386cd0a645069f0e1416263b4fa359b74b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76991 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/*: Update SPD mapping for sandybridge boardsKeith Hui
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-13mb/apple/macbookair4_2: Correctly implement SPD mapping the Haswell wayKeith Hui
While converting this board to provide SPD info using the Haswell API, it was discovered that its SPD setup was not correct to begin with. For a board that only has soldered down memory with SPD data in CBFS, it didn't enable HAVE_SPD_IN_CBFS in Kconfig. It also duplicated one set of SPD data with deliberate gaps in between. It worked its dark magic within mainboard_get_spd(), which is going away as a callback. Add HAVE_SPD_IN_CBFS to mainboard Kconfig, recreate the one set of SPD data as a hex dump same as other boards, and hook everything back up with Haswell-style mb_get_spd_map(). Recreated SPD data was extracted from abuild-built binary and manually verified for correctness against existing spd.bin (which will be removed in a follow-up). Change-Id: I906c49f6d1949f830828530edc0298b1b22ec04d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76995 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13nb/intel/sandybridge: Standardize MRC vs. native SPD mapping APIKeith Hui
Changes both MRC and native raminit code path to get SPD mapping from one place. Boards with all memory socketed specify their mappings in a devicetree setting introduced in commit 5709e03613b3 ("nb/intel/sandybridge: Migrate MRC settings to devicetree") back in May 2019 but remains unused as of this patch. This setting will now hold raw SMBus addresses, and MRC raminit gets code to translate them into a representation MRC expects. Boards with soldered down memory (specifically with HAVE_SPD_IN_CBFS in their board Kconfig), with or without socketed memory, specify their layouts in mb_get_spd_map() as used by Haswell boards, where they access hardware GPIO straps to select which SPD data to use. This harmonizes the way boards specify their SPD layouts across Haswell/SNB/IVB boards whether using MRC or native raminit. Going forward they only need to specify the layout in one place. (Going forward the devicetree setting should be backported to Haswell, once we get native raminit working there.) With this, northbridge code is now fully responsible for loading all SPD data, be it from CBFS or SMBus. To avoid breakage, transition will happen in stages: 1. This patch gets all the code in, and implements weak stubs that maintain existing code and data flow (i.e. mainboards still populate final SPD layout data). At this point devicetree already uses new representation, but is still unused meaning no breakage. 2. Follow-up patch(es) remove mainboard_get_spd() from mainboards, and replace it with mb_get_spd_map() or devicetree values (as appropriate) with converted SPD info. The "weak" mainboard_get_spd() with new logic takes over. Boards go Haswell Style at this point. Boards with MRC raminit also lose code to fill in SPD data, allowing new data to take hold. 3. Clean-up patch removes the weak functions and public prototypes re mainboard_get_spd(), making it internal to northbridge. Changeover is complete. Change-Id: I1a75279d981e46505930a9ce1aae894ccc4e1f24 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76965 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/51nb/x210: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I0f069f02e4f0957cbff05d1bc9aa499fb51b6a02 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13soc/amd/genoa: Hook up MCA codeArthur Heymans
This patch uses AMD SoC common code for MCA and adds MCA bank information as per Genoa Processor Programming Reference (PPR) version 0.25 (#55901) and uses AMD SoC common code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If728d803d600f7e86507cd1b35b40022bf4d379e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76524 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13soc/amd/genoa: Hook SMP and SMM initArthur Heymans
All CPUs properly come out of reset and relocate SMM. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13soc/amd/genoa: Double HEAP_SIZE to 0x200000Varshit Pandya
Default value of HEAP_SIZE is 0x100000, since genoa has a lot of CPU increase the HEAP_SIZE to 0x200000 Change-Id: Idd707200fe72730849267cd3cafc40e44f1f8c5d Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13security/vboot: Die if vb2api_reinit() failedYu-Ping Wu
In vboot_get_context(), vb2api_reinit() is called to restore the vboot context from the previous stage. We use assert() for the return value of vb2api_reinit() because there shouldn't be runtime errors, except for one edge case: vb2_shared_data struct version mismatch. More precisely, when RW firmware's VB2_SHARED_DATA_VERSION_MINOR is greater than RO's, vb2api_reinit() will return VB2_ERROR_SHARED_DATA_VERSION. To avoid using an invalid vb2_context pointer (when FATAL_ASSERTS is disabled), change assert() to die() on vb2api_reinit() failure. For the vb2api_init() case the assertion is unchanged because there shouldn't be any runtime error for that. Also move the vb2api_init() call outside the assert() argument, as assert() may be a no-op macro depending on the implementation. Change-Id: I4ff5ef1202bba2384c71634ec5ba12db1b784607 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-13mb/google: Remove obsolete Kconfig symbol VBT_DATA_SIZE_KBMartin Roth
The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 - "drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886, however that patch only removed the Kconfig option from the Intel chipsets, leaving it unused in the mainboards. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13fmap: Map less space in fallback path without CBFS verificationJulius Werner
This is a fixup to CB:78914 which inadvertently broke the RK3288 SoC. Unfortunately we can only accommodate very little PRERAM_CBFS_CACHE in the tiny SRAM for that chip, so we would not be able to map an entire FMAP. Solve this problem for now by mapping less space when CBFS verification is disabled, and disallowing CBFS verification on that SoC. Change-Id: I2e419d157dc26bb70a6dd62e44dc6607e51cf791 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-13drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksumBill XIE
Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-11-13security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk
init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76954 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13arch/x86/riscv: Use 'all' target to include files in all stagesArthur Heymans
This adds a few new files to romstage, that will be needed in follow-up patches. Change-Id: I2ba84e0becee883b5becf12e51f40734cad83d7d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68839 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-11-13Update genoa_poc/opensil submodule to upstream mainMartin Roth
Updating from commit id d81517e: 2023-09-28 14:13:56 -0600 - (Improper bit field offset calculation) to commit id 0411c75: 2023-11-10 23:59:34 +0000 - (Minor changes to fix issues compiling with clang) This brings in 1 new commits: 0411c75 Minor changes to fix issues compiling with clang Change-Id: Ib3adfd7bccd45dfd76ede462677dcfb294baa15d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13util/lint/kconfig_lint: Ignore C preprocessor macros in codeMartin Roth
To see which Kconfig symbols are actually used, and to verify that they're used correctly, kconfig_lint scans the C code. It gives an error if it sees a CONFIG(symbol) where the symbol doesn't exist. This creates a problem when a C preprocessor macro is created to match multiple Kconfig symbols. The simple solution here is to just ignore those C preprocessor macro definitions as beyond the scope of this linter. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5a20e8bb5a3e19e380802cba712d6dd3ff2f4dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78681 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-13acpi/acpigen: point out what acpigen_write_len_f doesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf2f54f2f428f4438ef22b7f9d205db10e144db Reviewed-on: https://review.coreboot.org/c/coreboot/+/79001 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13MAINTAINERS: Add Felix, Martin, Varshit for soc/amd/genoaVarshit Pandya
Change-Id: Ia368f390901424ef427eaefaa57acf2b6ae5d703 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-13MAINTAINERS: sort AMD SoC alphabeticallyVarshit Pandya
Change-Id: I0eaf94f7fb91a4b11dab2731a0b5d08aa85fd41e Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78988 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13MAINTAINERS: Add Felix, Martin, Varshit for mb/amd/onyxVarshit Pandya
1. Split AMD mainboard between AMD server and AMD non-server SoC 2. Add maintainers for onyx mainboard Change-Id: I94814da1c06d57cc63c9b968866570a812346fde Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78987 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13tests/acpigen: Patch to allow moving buffersNico Huber
When a package length needs to be written, we used to always write three bytes for it, even when the length would fit into one or two bytes. To allow such compact package lengths, we have to move the written buffer data in case the length is smaller. This makes tracking the start of nested buffers harder, as they may be moved entirely later when a package length is written. So instead of tracking start addresses in test_acpigen_nested_ifs(), let's work with the generated AML alone. In this lucky case, we can simply search for the `if` operations. Change-Id: Id8557dd5d1be3878713ee0b6106c3e0975665e97 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-13arch/riscv/ramstage.S: Add comments for passed argumentsMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib1af1359249008d9eba351271637748a7edcec26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78966 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/google/nissa/var/gothrax: Add GPIO configurationYunlong Jia
Add variant of LTE and WFC support on gothrax board. We base decisions on the values within the firmware configuration CBI field. In fw_config settings, if the board move LTE and WFC modules, the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7 pins need to be deasserted. BUG=b:303526071 TEST=emerge-nissa coreboot & \ Check against schematic. Whether it works as expected under different SKUs. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ia8041bdc599509911bde95d6294314036e75b227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13spd/lp4x: Add SPD for CXDB4CBAM-ML-A in parts_spd_manifest.generated.txtDaniel Peng
Generate initial SPD matched for CXMT CXDB4CBAM-ML-A. BUG=b:304932936 TEST=make -C util/spd_tools util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: Ia33a94a1784f865b4776ad9107e25e87420f944f Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78891 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-12util/docker/jenkins-node: Install pip modules into virtual envMartin Roth
Instead of installing the pip modules system-wide, and possibly causing conflicts, install them into a virtual environment for the coreboot user. If we wanted to, in the future, we could install different versions of the modules into different virtual environment directories to allow for testing or anything else we needed. Change-Id: I49c749a13a698bfb7af29bf07e42ac14b67b2ae7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>