| Age | Commit message (Collapse) | Author |
|---|
|
Allow the use of 64bit MMCONF base in MCFG table.
Previously only 32 bits were utilized for MMCONF base, while the
remaining 32bits were reserved & held value of zero as evident from MCFG
table disassembly. This commit entails updating the 'base_address' field
in the 'mmconfig' structure to 64 bits and removing the 'base_reserved'
field.
TEST=Confirmed the functionality of the 64bit MMCONF base in the MCFG
table disassembly below
Signature : "MCFG"
Table Length : 0000003C
Revision : 01
Checksum : BD
Oem ID : "COREv4"
Oem Table ID : "COREBOOT"
Oem Revision : 00000000
Asl Compiler ID : "CORE"
Asl Compiler Revision : 20230628
Reserved : 0000000000000000
Base Address : 0000001010000000
Segment Group Number : 0000
Start Bus Number : 00
End Bus Number : FF
Reserved : 00000000
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77539
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I25807e116869d1bd7b8324525bc5ae1691e072e4
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77601
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with
amd linker script hooked up.
Default to 64bit code as that will be a sensible default for this
platform (high memory access required for RAS setup).
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I69253466084d17c4359d7e824d69f12490b076e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
This board will use custom MP2 FW to dump the contents of the STB when
the SOC fails to enter/exit S0i3. Enable `PSP_LOAD_MP2_FW` by default.
BUG=b:259554520
TEST=Built and ran on skyrim device, verified that MP2 FW loads.
Change-Id: I4222521d01e2c98708f0e5b6693a8aee9e59edf2
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72118
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id 6a1e1457afdd:
2023-08-18 16:32:27 -0600 - (Add GenoaPI 1.0.0.4 blobs)
to commit id 591d5fb62cbb:
2023-08-21 13:57:09 -0600 - (mendocino: Update MP2 FW to 0A.0D.00.06)
This brings in 1 new commit:
591d5fb mendocino: Update MP2 FW to 0A.0D.00.06
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77541
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Older FSP releases don't have an option to do MP init via PPI, so it
should not be visible.
Change-Id: I74b4bd5dd72980b859763e89ead7d7f619321e66
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63759
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch creates rex ES variant with EC ISH enabled.
BUG=b:296886409
TEST=Able to build and boot rex4es_ec_ish variant.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I2b1cdb8cffd66badd90a7bf9825d9decb07941a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This update 'input-event-codes.h' file to master branch.
Change-Id: I09839886824868cfaff6127fe44ff02d7e21ba42
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
With the Tc-cold handshake, there's a fast flicker when connecting
external displays. With it disabled, it's just one "flick", so use
this as it's lesser of two evils.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie42b935d3e69beff6a1e503a8dee69554123b4f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The rule being added to the refactoring section is already present
in the "coding style" section of the guide, but is currently easy
to miss. Adding it to its own section makes it a little more plain
and makes it more strongly worded.
Update a couple of other areas:
- Make kernel specific phrasing better aligned with coreboot.
- Remove duplicate "try to match" phrase in coding style section.
- Remove section on Data structures - it doesn't apply to coreboot.
- Update text to make it clearer and more coreboot-centric.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic3508529f639ea0609d2ea2032cc52407e9543e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71067
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add support for FSP ASPM and Clock PM configuration based on Kconfig
options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some
use cases it may be desirable to disable ASPM and Clock PM to achieve
more deterministic and higher performance of PCIe devices.
TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all
PCIe devices are still working and ASPM and Clock PM capabilities
are not present on the PCIe Root Ports.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The amdfw.rom is mostly in region COREBOOT. Calculate the relative
address as the CBFS module address. That is for future 32M flash size
support.
TEST=binary identical test on amd/birman amd/majolica amd/gardenia
amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon
pcengines/apu2
google/skyrim google/guybrush google/zork google/kahlee google/myst
This commit is part of a series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72961
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It is based on work by Arthur Heymans, 69852.
Get rid of the confusing "position index" and use the relative flash
offset as the Kconfig setting instead.
TEST=binary identical on amd/birman amd/majolica amd/gardenia
amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon
pcengines/apu2
google/skyrim google/guybrush google/zork google/kahlee google/myst
(The test should be done with INCLUDE_CONFIG_FILE=n)
Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Update header files for FSP for Meteor Lake platform from 3292.83
to 3323.84.
The patch changess only a few spacing alignment for FSP-M header and
added few PPR (Post Package Repair) related variable for MemInfoHob
header.
BUG=b:297965979
TEST=Able to build and boot google/rex.
Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add FW_CONFIG probe for absent FIVR bypass mode on peezer.
BUG=b:296982082
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I0b2053b2d732fd9462686ed7b0c9225539b28fb2
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77396
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I1fb3630bf5e8a56ddcf6102faffde568134accc9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77375
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I6c985974e2eeea1329b2dbb232711c72b0bd99bc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: I67d443cb15d89482b20b01f4068502b16ac8fc8e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: I56e0501b511866b8ccc200b55620f87883e12067
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
According to the schematic, set below GPIO to NC:
1. GPP_C18
2. GPP_C19
3. GPP_S04
4. GPP_S05
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: If1f847d2db83b63a351203f0449cc1368bef27f4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77558
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The Genoa SoC supports MMIO addresses larger than 48 bits. Since the
MMIO base and limit registers in the data fabric only contain bits 16 to
47 of the MMIO address, the MMIO address extension register is
introduced on some SoCs like Genoa. This additional register contains
the upper bits of the MMIO base and limit. Since it's not available on
all SoCs, introduce the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
Kconfig option to select the correct data_fabric_get_mmio_base_size
implementation to be added to the build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic304f5797bc5661c1d511c95e457c6dde169d329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77514
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
Add HDMI GPIO configuration to early GPIO list to support
VGA text o/p in Pre-RAM stage on HDMI.
BUG=b:279173035
TEST=If CONFIG_UGOP_EARLY_GRAPHICS is set to y, check SOL
text on HDMI during Pre-RAM boot stage.
Change-Id: I13691850d09a442d5d5493a2b1dcf1145cf9797a
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch sets the Fast V-Mode (FVM) configuration parameter as
suggested in Intel doc 640982. As per the doc, Intel MTL-U 15W CPU
supports FVM on IA and SA.
Fast V-Mode (FVM): Intel Meteor Lake introduces the ability to manage
the peak power events it calls "reactive peak power management".
The Fast V-Mode is one such technique to perform the reactive peak power
management. It relies on the detector integrated inside the processor
which senses when the processor load current exceeds a present threshold
by monitoring the processor power domain IMVP (Intel Mobile Voltage
Positioning) VR sense point.
The baseline ITRIP for IA is 66A and 21A for SA.
BUG=b:286809233
TEST=Able to build and boot google/rex without seeing any performance
regression.
Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75763
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Collect SPD data from DIMMs and memory-down, and find the common
supported settings.
Original-Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a
Original-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I7948554eb02113bdca380222a11cfb322f9615f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Add unit tests for ux_locales_get_text() in lib/ux_locales.c.
BUG=b:264666392, b:289995591
BRANCH=brya
TEST=make tests/lib/ux_locales-test
TEST=Make sure ux_locales.c has 100% test coverage
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I4d73419c02478870942828d324c258ef0eaa983c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
|
KBL_STATE was originally intended to provide more granular control
of the keyboard backlight. However, KBL_BRIGHTNESS has a valid value
of "off" which achieves the same thing.
Therefore, unconditionally set the KBL_STATE to enabled, and rely on
KBL_BRIGHTNESS.
Change-Id: Ic7ee6b96b1dcaa6633b111e92097bce87908885e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77201
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I08187c339ebbe84b183f3c6e53f0eea540620fbf
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This patch adds option to override Fast Vmode on Meteor Lake SoC.
This requires CepEnable, EnableFastVmode, IccLimit FSPM UPDs in FSP
header. If the hardware supports Fast Vmode, the FSPM will set the
ICC limit value to the value passed from coreboot.
With CepEnable and EnableFastVmode enabled, if IccLimit is not
specified by coreboot, FSPM sets IccLimit as default value. If no
values assigned to all the three CepEnable, EnableFastVmode and
IccLimit, coreboot sets their values to 0 and Fast Vmode is disabled.
BUG=b:286809233
TEST=In debug MTL FSP logs, the value of FSP parameters is as passed
from coreboot including enable_fast_vmode, cep_enable, and
fast_vmode_i_trip. Also, fast_vmode_i_trip value is passed to pcode
using mailbox command without any error. This test done on google/rex
board.
Signed-off-by: Jay Patel <jay2.patel@intel.com>
Change-Id: Id05dccac56c504523f9327babe0c6fbeff488ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75566
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
|
Karis use MIPI camera only, remove related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I96316d63c068c48b5bec75d3b4c5444d15fd985f
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77510
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
According to the schematic, karis does not have a SAR sensor. Update
GPIO settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ib3b66b9594f2d0fddbbfc56e99f06b6587487f2a
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Follow schematic, set GPP_D04 to NC.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ie222a2773ff7d2b87641f55b4d37ff3bdf761cd2
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
enable GL9750 invert WP function
BRANCH=none
BUG=b:297244291
TEST=emerge-rex coreboot
Change-Id: I7fdc94b5ca6b316ee0291c38e39c5f8b08cbc127
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77414
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add an option to invert write protect polarity for GL9750.
Change-Id: I5761f3066291a2400caecbecc79ae893f0a0c146
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77403
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE comment was likely a
copy-paste leftover, so remove it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45b12d1dc5af84be99d54fea0c9ccf610cf5dae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
This reverts commit 5013c60a871af8fbce8c38a1c342c454e5b8452f.
Reason for revert: consecutive reboots are causing kernel panic.
BUG=b:297153853
TEST=Able to perform 50 cycles of consecutive reboot after reverting
this CL and it boots to the OS every single time(w/o any kernel panic).
Change-Id: If6c96dcc62c706a522b98a1cf1dd1920ad6473a1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77467
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds logic for logging the FW splash screen event to
the event log.
There could be three possible scenarios as below:
1. Platform w/o FW splash screen (i.e., either HAVE_FSP_LOGO_SUPPORT
or BMP_LOGO configs not enabled)
Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) not
present in the event log.
39 | 2023-08-27 12:42:54-0700 | System boot | 12
40 | 2023-08-27 12:42:54-0700 | ACPI Wake | S5
41 | 2023-08-27 12:42:54-0700 | Wake Source | Power Button | 0
2. Platform w/ FW splash screen (i.e., both HAVE_FSP_LOGO_SUPPORT
and BMP_LOGO configs are enabled)
Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is
enabled in the event log.
34 | 2023-08-27 12:07:29-0700 | System boot | 11
35 | 2023-08-27 12:07:29-0700 | Firmware Splash Screen | Enabled
36 | 2023-08-27 12:07:31-0700 | ACPI Wake | S5
37 | 2023-08-27 12:07:31-0700 | Wake Source | Power Button | 0
3. Failed to render FW splash screen (due to any reason if FSP failed
to render the splash screen)
Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is
disabled in the event log.
43 | 2023-08-27 13:06:10-0700 | System boot | 13
44 | 2023-08-27 13:06:10-0700 | Firmware Splash Screen | Disabled
45 | 2023-08-27 13:06:11-0700 | ACPI Wake | S5
46 | 2023-08-27 13:06:11-0700 | Wake Source | Power Button | 0
BUG=b:284799726
TEST=Verify that the event shows up in the event log when the user
selects the HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs to display
the firmware splash screen.
Change-Id: Ie9e09acff5443c31b881c300134bc0bb06c490c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch adds support for logging the firmware splash screen event
to the event log. There could be two possible scenarios for this
event: enabled and disabled.
BUG=b:284799726
TEST=Verify that the event shows up in the event log when the user
selects the HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs to display
the firmware splash screen.
Change-Id: I1e224903df21159d6eef2849a7d6fb05de09f543
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch adds a new eventLog type ELOG_TYPE_FW_SPLASH_SCREEN to
support logging when we show firmware splash screen to the user.
BUG=b:284799726
TEST=Event shows in eventlog when user selects BMP_LOGO and
HAVE_FSP_LOGO_SUPPORT configs.
Change-Id: Id1572ecb83ca025ff65608e7ae4f3a065024f6d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77507
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A trivial follow-up on CB:67060. This makes contents of the file look a
bit less regular, but more like the rest Makefile.inc in the code base.
Change-Id: I772d37825e4b59cf927637dc39bfb3ee06115860
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77533
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use "int foo(void)" instead of old-style "int foo()".
Change-Id: Ic698dbbba74d579a21ff57005a7aa9bb8ce80253
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use "int foo(void)" instead of old-style "int foo()".
Change-Id: Ieb151c2db1c0ee9222dbacccae78ca725bdcde08
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77498
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use "int foo(void)" instead of old-style "int foo()".
Change-Id: I19869ce2f47b543af4552ea23ce1fd1beea2f892
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77497
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use "int foo(void)" instead of old-style "int foo()".
Change-Id: I609c0332132389c07b03db40dc48dc94ca836a56
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This change causes a freeze during boot on an RPL-UR that does not have
the memory part string in the CBI.
BUG=b:296353047
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot
problematic DUT to kernel.
This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365.
Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the required GPIO and FW_CONFIG support to configure BT offload
audio in discrete mode for Intel Mysty Peak module on google/rex
Proto2 HW.
BUG=b:297125514
Test=Verified BT audio playback on google/rex Proto2.
Change-Id: I560f1700f78f8b653dfcc2f26764f0ebf2652689
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77357
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
|
'useable' -> 'usable'.
Change-Id: Iad2e1ef97a5c98ffa6f33806bce5b77722e687e8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: I157a3a700ed998b1012c85857c5fad78f60d62dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77525
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: I9804fcd9076b5a4813f099db0852a5af5ac36609
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77523
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: Idc38c759489976cbdf51d9c4bb950ef6d470b93a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Change-Id: Id7634099e40c0bf97944be124b494c41d6335ad7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Clang does not recognize comments to indicate falltrough is intended
behavior.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Idcf7a24fc763b80863902702172b4ea950e132b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77431
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
x86 assembly code uses a lot of nested macros so increase the default
value from 20 to 1000.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic23c452514de7dc1aa420541b756c443180b8b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77430
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to the schematic, karis does not have a UWB, remove
related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I8a442518c2007cde883183871cef96db416850c0
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77437
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The tool 'toada' which converts the Kconfig output to ada syntax keeps
running even when it can't parse something. Change that behavior to
halt, and update the error message to show where the error is coming
from.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I29807a054581060d04b9ecbe02f2ba666c46bcf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Any builds using ADA were getting a message saying:
`couldn't parse value '-1' for 'SEABIOS_DEBUG_LEVEL'`
This change allows toada to parse negative integers.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6507c54976b67f1ad70846b6bd6c54c861130d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77421
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
- Change all links to wikipedia to https.
- Update some links to wikipedia that were incomplete.
- Update a few links that are now broken.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If780e15997c499d1df975b436fd9af530f324eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77488
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Both mainboards have the same documentation. Instead of having two list
items referring to the same document, just merge the two items.
This fixes the following Sphinx warning:
WARNING: duplicated entry found in toctree: mainboard/lenovo/w530
Change-Id: I4140b34db01b1d5f47a39b9c1e33405e7789de63
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77503
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The document for northbridge/intel/i440bx doesn't exist and it didn't
exist at the time of introduction of these two mainboard documents. So
replace the reference with just the northbridge name.
This fixes the following Sphinx warning:
WARNING: unknown document: '../../northbridge/intel/i440bx/index'
Change-Id: Iaa67399f9d0e62d5d54ae08f5ebb8c70073c601f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
|
|
Add new documentation generated by util/util_readme/util_readme.sh.
This also fixes the following Sphinx warning:
util/abuild/index.md: WARNING: document isn't included in any toctree
Change-Id: I26c33af3c5a5853f6bcce23e982a6b192b01f1d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
|
|
Sections may not start with transitions. Remove them.
This fixes the following Sphinx error:
ERROR: Document or section may not begin with a transition.
Change-Id: I519af83df14e44b0709dee7e338dba1ee6413f0a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77440
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iabbb637c797a361a2cbc55505002774ff4f774e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77526
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clevo started using OZ711LV2 for the SD card reader around the time of
making its TGL boards. Without the driver, CPUs don't go to power states
lower than C2 due to LTR not being programmed. After enabling the driver
the CPU will go to C8 while the system is idle, giving significant power
savings if the system is left on battery power.
There is another issue with RPL where it only goes to C6 instead of C8.
This may be due to the intel_idle driver in Linux (as of 6.5-rc6
mainline and 6.4.6 stable) not supporting RPL C-states.
- tgl: Started being used with the Gazelle 3060 variant
- adl: Used on all models
- rpl: bonw15 does not have an SD card reader
Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The psp_transfer.h file was the same under all SoCs, and is really
tied to the file common/vboot/transfer.c, not the SOC.
This patch makes an include directory under vboot to put the header into
and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes
the header file available to all platforms, so that new chips that don't
use the psp_verstage don't have to make a psp_transfer.h file just to
satisfy the compiler.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
License classifiers are much better about classifying files with SPDX
headers than they are at classifying the general text licenses due to
minor variations in the text. To help with classification, add the
SPDX headers to the files.
To see the current state of coreboot's licensing, see:
https://coreboot.org/fossology/
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If490f6705e7862d9ad02c925104113b355434101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add new block for handling overclocking watchdog. The watchdog is
present since Skylake or maybe even earlier so it is safe to use with
most of the microarchitectures utilizing intelblocks.
The patch adds the common block for initializing and feeding the
watchdog. Timeout is defined statically in Kconfig and should be set
high enough by the board or SoC Kconfig to let the board boot with
full memory training and avoid reset loops. Full training of 128GB
DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs
with newer memory technologies and higher RAM capacity may take more.
The default has been set to 10 minutes.
The patch also adds support for feeding watchdog in driverless mode,
i.e. it utilizies periodic SMI to reload the timeout value and restart
the watchdog timer. This is optional and selectable by Kconfig option
as well. If the option is not enabled, payload and/or software must
ensure to keep feeding the watchdog, otherwise the platform will
reset.
TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add new memory part in the mem_parts_used.txt and generate the
SPD ID.
1. MICRON MT62F512M32D2DR-031 WT:B
BUG=b:291018417
TEST=emerge-rex coreboot
Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:297276380
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot
chromeos-bootimage
Cq-Depend: chrome-internal:6373154
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
|
|
According to the schematic, karis does not have a WWAN module, remove
related settings.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
This patch changes the SAR table selection logic to use FW_CONFIG which
will eventually help to support different WiFi SAR tables.
TEST=Able to build and boot google/rex.
Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de
Signed-off-by: YH Lin <yueherngl@google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These Kconfig options were being used basically as #define statements,
which is unnecessary. This isn't a good use of Kconfig options and would
be better just as #defines if actually needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
This patch moves the line adding hwlib to the include path to the inner
makefile so that it doesn't get added to every build, but only when
CONFIG_USE_SIEMENS_HWILIB=y
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id668b76366a554efff560cec746e637487ebdbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled
into the build when they aren't needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
This change tells the build to only pull vc/eltan/security/Makefile.inc
into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.
BUG=b:296511904, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified by EE
Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Scaleway Tagada was removed with commit c013fa6234 and Intel Galileo was
removed with commit 037c25d4dd. So remove their configs.
Change-Id: I1c491f437b8a1104bdf31a34e3c7d2c4e5794301
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77415
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add two missing mapping for GPIO GPE routes
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This compiler argument only exists on gcc.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I10902517c86daedc9853e6f6cac8fcf513211bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77436
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This fixes compilation with clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I675056c8a15fe446bba81a144bfea64d106df293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77435
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is necessary with clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icc197fbd48b49bfa8770caf01727669b0ac59090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Tweak a few sentences noticed when reading this.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0a072c83402bc551a6bbdb7cd7c55fc3505784b2
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
|
|
This is a useful feature, so add a note about it.
Change-Id: If29f6480f878bdaf877dc208cc4861b884e10840
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77465
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Update the U-Boot version to the latest release. Also switch to github
since it is typically much faster to download than the existing URL.
Drop the 'experimental' tag since this payload is pretty stable. It is
also tested regularly in U-Boot's CI.
Change-Id: I082130539c3474593a82e4b21cb995380f4db168
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77463
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
We only checked that the resource fits below the given `limit` in
memranges_find_entry(), but then accidentally placed it at the top
of the found memrange. As most resources have only a coarse limit,
e.g. the 4G barrier of 32-bit space, this became only visible when
artificially setting an unusual, lower limit on a resource.
So, for the final placement, use `MIN(limit, range end)` instead
of the range's end alone.
Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Set customized_leds value for RTL8111K to fix led can't work.
BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.
Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS
Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
In order to support logging of events for PSR data backup command
status during CSE firmware downgrade, add support for
ELOG_TYPE_PSR_DATA_BACKUP and ELOG_TYPE_PSR_DATA_LOST types.
BRANCH=None
BUG=b:273207144
TEST=Verify event shows in eventlog after CSE firmware downgrade
Change-Id: Ibb78ac8d420bb7a64328ce009ddcb99030519ec6
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77005
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
|
|
Add new eventlog types to support logging of Platform Service Record
(PSR) backup related messages. Eventlog entries are added on PSR data
backup success/failure and also when PSR data is lost.
BRANCH=None
BUG=b:273207144
TEST=Verify elog event added after PSR data backup command is sent
cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent
...
ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC
Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:271491845
TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08
Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The `use_8254` should be flipped, the same as the other Intel
SOCs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.
BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Idd3acd204c0809753b6f5534790e1dc81c10b761
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command
00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0
00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1
Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286
"payloads/external/LinuxBoot: Clean up".
Include the initrd into the payload. Allows to actually use LinuxBoot.
Change-Id: I5ab6b1a43a4100e83f4c188b9ea3451ab7b4ffe5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77412
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile
SoCs have, so add the additional 3 SMN base address definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When LZMA compression is selected, then it's not needed to check if LZ4
compression is selected in addition. So instead of handling both cases
separately, check for LZ4 only if LZMA is not selected.
This applies to the cases of both, FSP-M and FSP-S.
Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage
gpio table.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of
GPP_F14, GPP_F15 and GPP_F16 GPIOs.
BUG=none
TEST=none
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I124e7d68198050616795a67df23b6481f6fe1276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77407
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To avoid redundancy about how to call into `Makefile.sphinx`,
only do that from the `Documentation/Makefile` and call into
that from the top level.
Change-Id: I99c462cdaf83d711e4b7c07b713d304274db8cb4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
