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2023-06-07mb/google/rex/variants/ovis: Add GPIO configurationJakub Czapiga
Based on Platform Mapping Document for Ovis (go/ovis_mapping_doc) state for June 6, 2023 (Rev 0.3) BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Iae3ca243a245928e8ec3d48877cf578843922fc7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75502 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/nissa/var/joxer: disable PCIE RP7Mark Hsieh
joxer removed SD card from all SKUs, thus disable pcie_rp7. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3486d665ddb1de521ab4e656addb2209055174c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75658 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID configReka Norman
Board IDs are now filled in as part of the signing process, so we don't need to set them in coreboot. BUG=b:240620735 TEST=Build and check VBOOT_GSC_BOARD_ID is set to ZZCR. Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75641 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07security/intel/cbnt: Remove unneeded go stepsArthur Heymans
This updates the go modules in the intel-sec-tools git submodule. This is not needed. Change-Id: I2012d519b07321317fef415df892bbb966512ee2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55845 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.aslFelix Held
This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Stoneyridge ACPI code a bit more in line with the ACPI code of the other SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75597 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macroFelix Held
Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/picasso/acpi: rename sb_fch.asl to mmio.aslFelix Held
This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Picasso ACPI code a bit more in line with the ACPI code of the newer SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75591 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.aslFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785abfc90c99b58c11d57847573f550fcea1f774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/picasso/acpi: use ROOT_BRIDGE macroFelix Held
Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. TEST=Both Ubuntu 2022.4 and Windows 10 still boot successfully and don't show any new ACPI-related error. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2587d8bb270dc3edce9dfa570a5018116fc9187f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macroFelix Held
When instantiated in the DSDT, this macro will expand to the static part of the PCIe root bridge device. This macro allows both to deduplicate parts of the DSDT code as well as adding more than one PCIe root bridge device in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75568 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/acpi: move acpi_fill_root_complex_tom to StoneyridgeFelix Held
Now that Stoneyridge is the only AMD SoC that still needs the part of the SSDT that contains the TOM1 and TOM2, move it from the common code to the Stoneyridge northbridge code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9091360d6a82183092ef75417ad652523babe075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75564 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/glinda/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I948d882b2e2c6d19f73c0be094e4ff6e42ec81d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75560 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/phoenix/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. BUG=b:283495475 TEST=Myst still boots and both the coreboot console and the kernel show the expected PCI MMIO ranges being used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I425876c4ef470574e00e123d36101641240c98cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/mendocino/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad34d74d9f6cbed1d8a71a561a505f563e31db18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/cezanne/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/common/data_fabric/domain: write _BBN method in SSDTFelix Held
Instead of having PCI0's _BBN method in the DSDT that always returns 0, use acpigen_write_BBN to generate the _BBN method that returns the first PCI bus number in the PCI domain/host bridge. TEST=On mandolin the _BBN method in the _SB/PCI0 scope is now in the SSDT instead of the DSDT, but still returns 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8badeb0064b498d3f18217ea24bff73676913b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74992 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/picasso/chip: use common data fabric domain resource codeFelix Held
Use amd_pci_domain_read_resources function that gets the configured MMIO regions for the PCI root domain from the data fabric's MMIO decode registers instead of using pci_domain_read_resources. This results in the same IO port range being used by the allocator, but makes sure that the allocator will only allocate non-fixed MMIO resources in the address ranges that get decoded to the PCI root complex. In order for the PCI0 _CRS ACPI resource template to match the decoded PCI root domain MMIO windows, use amd_pci_domain_fill_ssdt to generate the _CRS ACPI code instead of having a mostly hard-coded _CRS method in the DSDT. This makes sure that the OS will know about the MMIO regions it is allowed to used. Before this patch, only the region from TOM1 to right below CONFIG_ECAM_MMCONF_BASE_ADDRESS was advertised as usable PCI MMIO in the PCI0 _CRS method. Also the resource allocator didn't get any constraint on which address ranges it can use to put the non-fixed MMIO resources. This approach worked until now, since all address range from 0 up to right below TOM1 was filled with either usable or reserved memory and the allocator was allocating beginning right from TOM1, since it was using the bottom-up allocation approach and everything below TOM1 was already in use. The MMIO region from TOM1 to right below CONFIG_ECAM_MMCONF_BASE_ADDRESS also matched the MMIO decode window configured in the data fabric's MMIO decode registers, so everything seemed to work fine. However, when either selecting RESOURCE_ALLOCATION_TOP_DOWN or enabling above 4GB MMIO, things broke badly. This was partially due to the allocator putting non-fixed MMIO resources in regions that weren't decoded to the PCI root, since AMD family 17h and 19h silicon doesn't subtractively decode PCI MMIO and the wrong ranges the allocator used also weren't advertised in ACPI. TEST=Even when selecting RESOURCE_ALLOCATION_TOP_DOWN that usually ends up with a non-working system when the MMIO ranges aren't reported correctly to the resource allocator due to the reasons descried above, Ubuntu 22.04 LTS still boots on Mandolin both with SeaBIOS and EDK2 payload and Windows 10 boots with EDK payload. There's however an EDK2 bug that results the MMCONFIG region not being advertised in the e820 table, which causes Linux to not use the MMCONFIG and fall back to the legacy PCI config access method. This only happens with EDK2 payload and everything works fine when using SeaBIOS as payload. That e820 issue is unaffected by this patch. At the end of the data_fabric_set_mmio_np call, this is the data fabric MMIO register configuration: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 The limit of the data fabric MMIO decode register 1 is configured as 0xffffffffffff although this is way beyond the addressable memory space. add_data_fabric_mmio_regions fixes this up, so the range that gets passed to the allocator in that case is 0x7fcffffffff which takes both the reserved most significant address bits used for the memory encryption and the 12GB reserved data fabric MMIO at the top of the usable address space into account. This results in the following domain ranges passed to the resource allocator: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: fc000000 size: 0 align: 0 gran: 0 limit: febfffff DOMAIN: 0000 mem: base: 10000000000 size: 0 align: 0 gran: 0 limit: 7fcffffffff DOMAIN: 0000 mem: base: d0000000 size: 0 align: 0 gran: 0 limit: f7ffffff The IO resource producer region is split into two parts to not cover the PCI config IO region resource consumer. This results in these resources being added to the PCI0 _CRS resource template: amd_pci_domain_fill_ssdt ACPI scope: '\_SB.PCI0' PCI0 _CRS: adding busses [0-3f] PCI0 _CRS: adding IO range [0-cf7] PCI0 _CRS: adding IO range [d00-ffff] PCI0 _CRS: adding MMIO range [fc000000-febfffff] PCI0 _CRS: adding MMIO range [10000000000-7fcffffffff] PCI0 _CRS: adding MMIO range [d0000000-f7ffffff] PCI0 _CRS: adding VGA resource Kernel version 5.15.0-43 from Ubuntu 2022.4 LTS prints this in dmesg: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-3f] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff window] pci_bus 0000:00: root bus resource [mem 0xfc000000-0xfebfffff window] pci_bus 0000:00: root bus resource [mem 0x10000000000-0x7fcffffffff window] Another noteworthy thing I wasn't aware of at first when testing ACPI changes on Windows 10 is that a normal Windows shutdown and boot cycle won't result in it processing the changed ACPI tables; you have to tell it to reboot to do a proper full boot where it will process the updated ACPI tables (and fail if it dislikes something about the ACPI tables and bytecode). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia24930ec2a9962dd15e874e9defea441cffae9f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74712 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdtFelix Held
Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI bus numbers and IO and MMIO regions can be used for PCI devices below _SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and amd_pci_domain_read_resources provided to the resource allocator. This makes sure that the PCI0 _CRS ACPI resource template matches the constraints the resource allocator used when allocating resources. TEST=With also the rest of the current patch train applied, the generated _CRS resource template contains the expected PCI bus numbers and IO and MMIO resources and both Linux and Windows boot on Mandolin. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-07acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_ioFelix Held
When an IO resource producer is generated that covers the whole IO space from 0 to 0xffff, the length field in the word resource ACPI type would overflow and be truncated which results in Linux not finding any usable IO space to use for the PCI IO BARs. Instead generate a double word IO resource producer to have all cases supported. Beware that covering all IO ports with the IO resource producer while covering the PCI config IO ports with a resource consumer in the same PCI root device will make Linux a bit unhappy and it will complain due to the overlap, but still end up doing the right thing: acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored The SoC code should make sure to carve out the PCI config IO ports from the IO resource producer. TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord resource producer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/data_fabric/domain: provide scan_bus and read_resourcesFelix Held
Provide amd_pci_domain_scan_bus to enumerate the PCI buses in the one PCI root domain and amd_pci_domain_read_resources to read the MMIO regions that the resource allocator can use to allocate the PCI MMIO BARs in the one PCI root domain from the corresponding data fabric MMIO decode registers. This makes sure that the allocator will only put PCI MMIO resources in areas that are decoded to the PCIe root complex. The current code only covers the case of a system with one PCI root where all PCI bus numbers belong to the only PCI root, all IO ports get decoded to the only PCI root and the MMIO regions from the data fabric MMIO decode registers get decoded to the only PCI root. In future patches, this will be extended to also support the multi PCI root case. TEST=With also the rest of the current patch train applied, the resource allocator uses the constraints on the MMIO regions and both Linux and Windows boot on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4aada7c8a2a43145ad08d11d0a38d9cdc182b98e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74717 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits()Felix Held
In case the secure memory encryption is enabled, some of the upper usable address bits of the host can't be used any more. Bits 11..6 in CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken away from the usable address bits in the case the secure memory encryption is enabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/block/cpu/noncar/cpu: add missing types.h includeFelix Held
types.h provides uint32_t via a chain include. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I875e3bb096b56bbea862c9ad0e3e14e025e3298b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75622 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06drivers/spi/winbond.c: Add W25Q256JW_DTR partFred Reitberger
BUG=b:285110121 TEST=boot Myst and verify the flash is recognized Change-Id: I30aed5299f87f7cf02fe9a5569edd2b8dcf7b452 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-06drivers/spi/spi_flash.c: Print the flash ID when find_match failsFred Reitberger
Print the flash ID codes when find_match fails to match the flash. BUG=b:285110121 Change-Id: I2106abfcfbd44c7d56d48ffbb43d8c76089af076 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-06libpayload/drivers/usb/xhci.c: Check for NULL in xhci_initFred Reitberger
Ensure the physical_bar parameter passed to xhci_init is not NULL, else return NULL. This may occur when an XHCI controller is disabled and no resources are allocated for it. BUG=b:284213001 Change-Id: I05c32612606793adcba3f4a5724092387a215d41 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75645 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/intel/common/crashlog: Add support for IOE diePratikkumar Prajapati
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/amd/stoneyridge/northbridge: reserve PCI config IO portsFelix Held
This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75619 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-06soc/amd/*/root_complex: reserve PCI config IO portsFelix Held
This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-06arch/x86/include/arch/vga: add defines for VGA MMIO addressesFelix Held
To avoid magic constants in the code, add defines for the VGA MMIO address range from 0xa0000-0xbffff. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Reviewed-on: https://review.coreboot.org/c/coreboot/+/75618 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/rex/var/rex0: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06soc/intel/xeon_sp/spr: Add RMT configNaresh Solanki
This commit adds a configuration option to enable RMT in the coreboot build for the Intel Xeon SP SPR platform. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-06mb/google/kukui: Change Juniper/Willow RAM table offset to 0x30Sheng-Liang Pan
All the DRAM module for Juniper/Willow can reuse the RAM ID in offset 0x30 table, so change Juniper/Willow RAM table offset to 0x30 for introducing more DRAM modules. BUG=b:284423187 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-06mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7Dtrain Hsu
Uldren does not have PCIE device and should disable PCIE RP7 and GPP_D7 for preventing PCIe controller not power gate in S0ix. BUG=b:283735051 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage 1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6' [SPEW ] PCI: 00:1c.6: enabled 0 [SPEW ] PCI: 00:1c.6: enabled 0 2. GPP_D7: iotools mmio_read32 0xfd6d0ab0 0x44000300 Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-06mb/google/rex/variants/ovis: Add RAM IDsJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06mb/google/rex: Create ovis variantJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/corsola/var/starmie: Add K&D-ILI9882T panel supportRuihai Zhou
The K&D-ILI9882T panel and STA-ILI9882T share all DCS commands and EDID information except for the manufacturer_name which has no effect to the function of panel. Let's reuse the STA_ILI9882T struct in this case. BUG=None TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I510462a49d273f3d25158b25906d4c514f855cdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-06mb/google/geralt: Fix MIPI panel power on/off sequenceRuihai Zhou
Based on the power sequence of the panel [1], the power on T2 sequence VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP to VSN should be larger than 0ms. We modify the power sequence to meet the datasheet requirement. [1] B5 TV110C9M-LL0 Product Specification Rev.P0 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-06soc/intel/meteorlake: Fill PCI SSID parametersKapil Porwal
Set SSID UPD to program DID as SSID for all the on board PCIe devices if SSID is not being overridden by CONFIG option or device tree. BUG=b:263846223 TEST=Verify that SSID for all PCI devices is same as their respective DIDs. Output of lspci in the OS: 00:00.0 0600: 8086:7d02 (rev 01) Subsystem: 8086:7d02 00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller]) Subsystem: 8086:7d45 00:04.0 1180: 8086:7d03 (rev 01) Subsystem: 8086:7d03 00:05.0 0480: 8086:7d19 (rev 01) Subsystem: 8086:7d19 00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e4d Capabilities: [98] Subsystem: 8086:7e4d 00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec4 Capabilities: [90] Subsystem: 8086:7ec4 00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec6 Capabilities: [90] Subsystem: 8086:7ec6 00:0a.0 1180: 8086:7d0d (rev 01) Subsystem: 8086:7d0d 00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI]) Subsystem: 8086:7ec0 00:0d.2 0c03: 8086:7ec2 (prog-if 40) Subsystem: 8086:7ec2 00:0d.3 0c03: 8086:7ec3 (prog-if 40) Subsystem: 8086:7ec3 00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI]) Subsystem: 8086:7e7d 00:14.2 0500: 8086:7e7f (rev 01) Subsystem: 8086:7e7f 00:14.3 0280: 8086:7e40 (rev 01) Subsystem: 8086:0094 00:15.0 0c80: 8086:7e78 (rev 01) Subsystem: 8086:7e78 00:15.1 0c80: 8086:7e79 (rev 01) Subsystem: 8086:7e79 00:15.3 0c80: 8086:7e7b (rev 01) Subsystem: 8086:7e7b 00:16.0 0780: 8086:7e70 (rev 01) Subsystem: 8086:7e70 00:19.0 0c80: 8086:7e50 (rev 01) Subsystem: 8086:7e50 00:19.1 0c80: 8086:7e51 (rev 01) Subsystem: 8086:7e51 00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e3e Capabilities: [98] Subsystem: 8086:7e3e 00:1e.0 0780: 8086:7e25 (rev 01) Subsystem: 8086:7e25 00:1e.3 0c80: 8086:7e30 (rev 01) Subsystem: 8086:7e30 00:1f.0 0601: 8086:7e04 (rev 01) Subsystem: 8086:7e04 00:1f.3 0401: 8086:7e28 (rev 01) 00:1f.5 0c80: 8086:7e23 (rev 01) Subsystem: 8086:7e23 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06mb/google/rex/var/rex0: probe for i2c1 touchscreenEran Mitrani
Touchscreen may either use I2C1 or SPI0. FW_CONFIG.TOUCHSCREEN is set to determine which is used. This CL adds a probe to enable I2C1. BUG=b:278783755 TEST=Tested on rex, confimed i2c1 is disabled when TOUCHSCREEN != TOUCHSCREEN_I2C Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06soc/amd/phoenix: Update USB device aliasEric Lai
Follow 57263_FP8_MBDG_rev_0_92 Table.57 to update the alias. We can match the schematic for now. BUG=b:285793461 TEST=USB still works. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-06vboot: Drop argument to select slot from `vb2ex_ec_protect()`Subrata Banik
vboot code changes have eliminated the redundant call to WP the EC-RO region as protecting RW flash implies protecting both RO and RW flash, so the call to protect RO is redundant. google/rex currently takes about 17 ms to lock down the EC. Along with vboot changes, this patch drops argument to choose between RO and RW slot to protect while calling into `vb2ex_ec_protect()`. It ensures vb2ex_ec_protect() is explicitly meant for protecting RW regions. w/o this patch: 517:waiting for EC to allow higher power draw 846,196 (17,297) w/ this patch: 517:waiting for EC to allow higher power draw 838,258 (9,719) Additionally, update vboot submodule to upstream main to avoid the compilation error. Updating from commit id 35f50c3154e5: Fix build error when compiling without -DNDEBUG to commit id 034907b279c9db: vboot_reference: eliminate redundant call to write protect EC-RO Change-Id: I2974f0cb43ba800c2aaeac4876ebaa052b5ee793 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-06mb/google/nissa/var/joxer: add lp5x SPDs for JoxerMark Hsieh
Add Makefile.inc to include four LPDDR5x SPDs for the following parts for Joxer: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) H58G56BK7BX068 4 (0100) MT62F1G32D2DS-026 WT:B 4 (0100) K3KL8L80CM-MGCT 4 (0100) BUG=b:236576115 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibdc89c882581cfe4e5978faf4c6f70d653e0813d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75610 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06Docs: Update the 4.19 release notes to match the server versionMartin Roth
The version of the 4.19 release notes on the server was updated with signatures and a note explaining the new tarballs vs the original, corrupted tarballs. That data didn't make it back to the version of the release notes in the documentation. Likewise, the updates in the documentation didn't get pushed to the release directory on the website. The website now has this version of the release notes that combines the two. This patch does the same for the documentation folder. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib2563e7fa4b8d82ad4fbb3fd3880ee62a24a8aca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-05soc/amd/mendocino: Print content of manifest fileGrzegorz Bernacki
This adds printing content of 'manifest' file at ramstage. It allows to learn about blobs version used to build the coreboot binary, which is useful when investigating bugs. Version data are stored in CBFS file, which was generated during coreboot build. If AMD FW blobs will be manually replaced in coreboot image, versions from CBFS file are no longer valid. Log: AMDFW blobs version: type: 0x01 ver:00.3c.01.18 type: 0x08 ver:00.5a.28.00 type: 0x30 ver:2b.25.b0.10 type: 0x73 ver:00.3c.01.18 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74269 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04Documentation: Move 4.20 release notes to 4.20.1Martin Roth
This moves the release notes to 4.20.1, as was done with the 4.8 release when it went to 4.8.1. The index.md file is updated for both the 4.20.1 and 4.8.1 releases, and extra spacing was added. This doesn't get shown in the output, but makes the text version look better. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic2fb35f1bf9fa7dc16d324882cd6057a1a4b05ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/75637 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-04Documentation: Finalize 4.20 release notesMartin Roth
Update the 4.20 release notes to the final post-release version. This fixes a few typos, updates the statistics to include the final few patches, and adds a note about the licensing issues which required a version bump to 4.20.1. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I350535b8aa531642e161f1cad4752452f9171647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-04mb/google/rex: add macro for touchscreen IRQEran Mitrani
BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04soc/sifive: Comment out set but unused variablesArthur Heymans
The code is supposed to output debug messages but is commented out, so do the same for variables. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ief1f9d2175fe1375fe6ac4bb0765b00513321fa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-04cpu/x86/smm: Drop fxsave/fxrstor logicArthur Heymans
Since we now explicitly compile both ramstage and smihandler code without floating point operations and associated registers we don't need to save/restore floating point registers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I180b9781bf5849111501ae8e9806554a7851c0da Reviewed-on: https://review.coreboot.org/c/coreboot/+/75317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-04util/qemu: Revise q35 configsNico Huber
Add an NVMe drive and be more conservative with hotplug-capable PCIe ports. QEMU treats everything as hotpluggable by default, so devices can be added at runtime. However, this leads to unrealistic resource allocations with PCIEXP_HOTPLUG enabled. Tested recent allocator changes with QEMU/Q35 config and: $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg Change-Id: I23746b642329356c6767b04ec177cd9411e3adb9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67026 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-04mb/google/brya/var/taeko: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/brya/var/marasov: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/brya/var/constitution: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/brya/var/kuldax: use RPL FSP headersDavid Wu
Select SOC_INTEL_RAPTORLAKE for kuldax so that it will use the RPL FSP headers for kuldax. BUG=b:285406822 BRANCH=firmware-brya-14505.B TEST="FW_NAME=kuldax emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage" Cq-Depend: chromium:4583807, chrome-internal:6003096 Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75599 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-04mb/google/brya/var/kuldax: Enable Fast VMode for kuldaxDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:285406822 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I9ae58d704cba8124c6cb9865431aff84c9d154f7 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75600 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-04mb/google/myst: Add USB configJon Murphy
Add the phoenix usb config struct for Myst since the FSP has been updated to accept the config from coreboot and the default values do not work. BUG=None TEST=Boot to OS on Myst, verify devices are seen with lsusb Change-Id: I329aba80f3003a3a5f343b8dcc3efa8502b98e24 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-04mb/google/rex: Enable ISH supportBernardo Perez Priego
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in case device is a tablet and motion sensors are handled by ISH instead of EC. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled and loaded Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex,screebo: Update GPIO PAD IO Standby StateBora Guvendik
Fix for the "Onboard Keyboard and Type-C ports are not working after resuming from powerd_dbus_suspend" issue. This issue was caused since FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState programming when GpioOverride UPD is enabled. This patch moves the IO Standby State programming that FSP was doing to coreboot. BUG=b:284264580 TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex/var/screebo: Add devicetree for support audioRui Zhou
Add devicetree config for ALC1019_ALC5682I_I2S BUG=b:278169268 TEST=emerge-rex coreboot and verified on screebo Change-Id: I2814cc76aff43daf0353cfef41592591bbe3d213 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-04lib: Support localized text of memory_training_desc in ux_locales.cHsuan Ting Chen
To support the localized text, we need to get the locale id by vboot APIs and read raw string content file: preram_locales located at either RO or RW. The preram_locales file follows the format: [string_name_1] [\x00] [locale_id_1] [\x00] [localized_string_1] [\x00] [locale_id_2] [\x00] [localized_string_2] ... [string_name_2] [\x00] ... This code will search for the correct localized string that its string name is `memory_training_desc` and its locale ID matches the ID vb2api returns. If no valid string found, we will try to display in English (locale ID 0). BUG=b:264666392 BRANCH=brya TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04mb/google/myst: Add PCIe shutdown workaroundJon Murphy
On Myst, the FSP is shutting down the PCIe lanes that the SSD is on. Enable hotplug to force the FSP to keep the lanes active. BUG=b:284213391 TEST=Boot to OS Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Reviewed-on: https://review.coreboot.org/c/coreboot/+/75583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-04mb/google/myst: Enable S0ixJon Murphy
Enable s0ix on Myst. BUG=b:277215113 TEST=builds Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04libpayload/uhci: Return expected length for control/bulk transfersNico Huber
Libpayload's USB API was changed in commit e9738dbe2b (libpayload: Make USB transfer functions return amount of bytes). However, the UHCI driver was never adapted. Instead of returning 0 for success, we can return the expected data length as a best effort. We won't be able to catch short transfers this way, but previously working cases will work again. Change-Id: I31d7de495a46af401e2cbe5a3b8f6349facad8ff Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04vc/intel/fsp2: Drop Intel Quark FSP headersFelix Singer
Intel Quark was dropped in commit 531023285e. Thus, drop the remaining FSP headers. Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-04crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5Elyes Haouas
Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75635 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4Elyes Haouas
Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-04soc/intel/meteorlake: Apply PCIe RP mask based on SoC typeSubrata Banik
This patch ensures to update the FSP-M UPDs related to PCIe RP mask properly as per the SoC type. For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse PCIe RPs are from PCH die in case of MTL-S. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: Ice81553274682476bb4c927061b1196dc142836d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-04mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_PSubrata Banik
Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot intel/mtlrvp. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75607 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/rex: Select SOC_INTEL_METEORLAKE_U_PSubrata Banik
Google/Rex is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04soc/intel/meteorlake: Introduce different SoC flavors of Meteor LakeSubrata Banik
This patch introduces the different SoC flavors of Intel Meteor Lake as: * MTL-U * MTL-P * MTL-S MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die. The task for mainboard is to specify the correct SoC type rather than selecting the MTL SoC by default. This change is necessary to support the different SoC flavors of Intel Meteor Lake. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04soc/intel/meteorlake: Hook up UPD PchHdaSdiEnableRonak Kanabar
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:273962021 TEST=Verified the settings on google/rex using debug FSP logs. Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3194_81, previous version being 3165_81. FSPM: 1. Add 'PchPcieRpEnableMask' UPD 2. Address offset changes Add "FspProducerDataHeader.h" file to support MRC version Info BUG=b:284803304 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-03Docs: Update sphinx targets with the build directoryMartin Roth
Because Makefile.sphinx looks like a standard makefile from the sphinx project, it probably shouldn't be updated without good reason. This change lets us update the output directory and tell the Makefile.sphinx where we want the output. Also fix the spacing on PDFLATEX to match the new SPHINXDIR variable. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iab111e8feea8ec02260f39636e7c17fd1cae7c30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-03Docs: Add a test target for the documentationMartin Roth
The test target will run, but won't fail the build if there are issues. This is so it can be added to the jenkins build and run until it passes. At that point, it can be made to fail if there's an error. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5810643ee143f9db4f1cd388531161d4398d596c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-03mb/google/rex: Create karis variantTyler Wang
Create the karis variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:285195072 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KARIS Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-03mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281950933 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-03mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-03spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCLWisley Chen
Generate initial SPD for Samsung K4UCE3Q4AB-MGCL BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-03mb/starlabs/starbook: Fix the ramtop CMOS entrySean Rhodes
The ramtop entry has to be 10 bytes long, and it was incorrectly set to 10 bits, instead of 10 bytes. Change this to 80. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-03lib/dimm_info_util.c: Add newlines to log messagesFred Reitberger
Add newlines to log messages to prevent them from running into each other. Change-Id: I4f61c80385f384a3734a5122ccb4161c1ed7c6c5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75589 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02Docs: Add help target and .phony identifiersMartin Roth
This change adds a help target so we can see what the valid targets are and what they do, and also identifies the phony targets. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie61d44d87e8628e12d01f3355360e2a679b5ce85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02payloads/edk2: Set max variable size to 0x8000 for SMMSTORESean Rhodes
SMMSTORE requires 0x8000, compared to the default value of 0x10000. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I10d2a5a0c1d729d83e0b62bb9430863317b883cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-06-02util/amdfwtool: Add ability to split hash tableKarthikeyan Ramasubramanian
Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-02Docs: Add sphinx to the documentation's "all" targetMartin Roth
The all target really should build the expected output. At this point, that means sphinx as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ibbceddd013605f5f7e11707480ae2a1e5d012a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02util/docker: Split coreboot-sdk test into its own docker imageMartin Roth
This allows the coreboot-sdk docker image to build properly even if the testing fails, and keeps the added overhead out of the coreboot-sdk image. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6488799256f57ad64e14c93e7317b7ad2a71781c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02soc/amd/common/block/graphics: Add missing pci_rom_free()Grzegorz Bernacki
pci_rom_probe() can allocate memory when mapping a CBFS file, so pci_rom_free() should be called before leaving the function. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: Ie6fbbfd36f0974551befef4d08423a8148e151e7 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74779 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-06-02device/pci_rom: Add simple pci_rom_free()Grzegorz Bernacki
It adds simple function, which frees the memory which could be allocated by pci_rom_probe(). In the next step it will be modified to free only memory, which was mapped from CBFS. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: Ibc9aad34b6bf101a3a0c06b92ed2dc6f2d7b9b33 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74778 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/amd/common/block/cpu: Refactor ucode allocationGrzegorz Bernacki
Move microcode load/unload to pre_mp_init and post_mp_init callbacks. It allows to make sure that ucode is freed only if all APs updated microcode. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: I200d24df6157cc6d06bade34809faefea9f0090a Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-02amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenixFred Reitberger
BUG=285390041 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEXFred Reitberger
The phoenix SoC does not support multiple EFS locations. Set the default to the only valid value and prevent mainboard overrides by making the option non-user-configurable. TEST=build birman-phoenix Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-02soc/amd/mendocino: Add manifest generation to MakefileGrzegorz Bernacki
This adds manifest generated by amdfwtool to CBFS. BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: I13c9d322735e0979484b120c665fb100cf187eab Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74267 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-02amdfwtool: Add --output-manifest optionGrzegorz Bernacki
Passing this option tells amdfwtool to create a text file, containing the versions of the blobs below: - PSP bootloader (type 0x01), - SMU firmware (type 0x08), - AGESA bootloader 0 (type 0x30), - PSP bootloader AB (type 0x73). Created file can be embedded into CBFS which allows to read the version of blobs at runtime. This way version of blobs used to build the coreboot image can be verified at runtime and also from the binary file. Format of manifest file is following: $ cat build/amdfw_manifest type: 0x01 ver:00.35.00.13 type: 0x08 ver:00.5a.23.a6 type: 0x30 ver:2a.14.b0.10 type: 0x73 ver:00.35.00.13 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-02mb/google/rex/variants/screebo: add FW_CONFIG for audio/DBSimon Zhou
This patch adds FW_CONFIG to accommodate different Screebo BOM components across various SKUs. 1. DB_CONFIG for DB_TPEC/DB_TBT/DB_UNKOWN 2. AUDIO for ALC1019_ALC5682I_I2S/AUDIO_UNKNOWN BUG=b:278169268 TEST=build pass Change-Id: I928aae61d4936509a7b68f4041c0cd72f298e83d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-02include/cpu/x86: Simplify en/dis cache functionsHimanshu Sahdev
Implementation of enable/disable cache functions aren't complex, simply drop cr0 variable usage, still maintains good readablity. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: I81688e8bbb073e1d09ecf63f3f33e1651dbd778e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75552 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01soc/intel/jasperlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-01mb/google/myst: Add ELAN touch screenEric Lai
Follow the eKTH7B18U_Product_Spec_V1.1 to add the device. BUG=b:284381267 TEST=Check touch screen can detect in coreboot. [INFO ] \_SB.I2C1.H010: ELAN Touchscreen at I2C: 02:10 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4bd521410953892a477020a872de0d882001b178 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-06-01mb/google/myst: Add ELAN touch padEric Lai
Follow the data sheet SA577C-12C0, Rev. 1.1 to add the device. BUG=b:284381266 TEST=check touch pad can detect in coreboot. [INFO ] \_SB.I2C0.D015: ELAN Touchpad at I2C: 01:15 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0eb0ee1e6cb9c15bfe3964af6ce2ed02eee370a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-06-01mb/google/myst: Add codec RTL5682 and amp RTL1019Eric Lai
Follow the schematic_0502 to add the audio codec and amp. BUG=b:270109435 TEST=Check device can detect in coreboot. [INFO ] \_SB.I2C3.RT58: Realtek RT5682 at I2C: 04:1a [INFO ] \_SB.I2C3.D029: Realtek SPK AMP R at I2C: 04:29 [INFO ] \_SB.I2C3.D02A: Realtek SPK AMP L at I2C: 04:2a Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icfec8d99be8fde986c5516e0c4cd50dae1edfa98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75477 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA portsMario Scheithauer
There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-24 05:17:30 +0000