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This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Update the QUP DFSR cmd to clear the SW control and also update the perf
registers when M is set. While at it also update the d_2 values.
Tested: validated DFSR clock configuration and M/N/D values.
Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Developer/Reviewer, be aware of this patch from Mistral:
https://review.coreboot.org/c/coreboot/+/33425/18
Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add golang and libelf-dev so LinuxBoot can be built from the
coreboot-sdk docker container.
BUG=N/A
TEST=build
Change-Id: I7a156fc24a6040d73467e06c16139bf298a29740
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38751
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enabling an assertion in vb2_member_of() results in coreboot
linking vb2ex_abort() and vb2ex_printf() in ramstage.
Move these two functions from vboot_logic.c to vboot_lib.c,
which is should be enabled in all stages if CONFIG_VBOOT_LIB
is enabled. Note that CONFIG_VBOOT_LIB is implied by
CONFIG_VBOOT.
Relevant vboot_reference commit: CL:2037263.
BUG=b:124141368, chromium:1005700
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ica0103c5684b3d50ba7dc1b4c39559cb192efa81
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Wait for HPD DP unless HDMI is plugged.
Some Type-C monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Similar to that of b:72387533 however our DP&HDMI are beind a MST.
See commit d182b63347c744c on how this was done for mainboard/fizz.
BUG=b:147992492
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I19d40056e58f1737f87fd07d62b07a723a63d610
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using
PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board
to enable the dGPU.
Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The STM support aligns the smm_save_state_size. However, this creates
issue for some platforms because of this value being hard coded to
0x400
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: Ia584f7e9b86405a12eb6cbedc3a2615a8727f69e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38734
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA
1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly
utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which
is compatible with AGESA 1.0.0.4 version.
Cut out the changes introduced in CB:11225 exclusively for apu2 board.
TEST=boot PC Engines apu2 and launch Debian Linux
Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8
and disable Fast PKG C State Ramp (IA, GT, SA).
BRANCH=hatch
BUG=b:143501884
TEST=build and verify that noise reduce.
Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I5f053c1270bab71aeab3bb785c60417419736b44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This update is a combination of all four of the patches so that the
commit can be done without breaking parts of coreboot. This possible
breakage is because of the cross-dependencies between the original
separate patches would cause failure because of data structure changes.
security/intel/stm
This directory contains the functions that check and move the STM to the
MSEG, create its page tables, and create the BIOS resource list.
The STM page tables is a six page region located in the MSEG and are
pointed to by the CR3 Offset field in the MSEG header. The initial
page tables will identity map all memory between 0-4G. The STM starts
in IA32e mode, which requires page tables to exist at startup.
The BIOS resource list defines the resources that the SMI Handler is
allowed to access. This includes the SMM memory area where the SMI
handler resides and other resources such as I/O devices. The STM uses
the BIOS resource list to restrict the SMI handler's accesses.
The BIOS resource list is currently located in the same area as the
SMI handler. This location is shown in the comment section before
smm_load_module in smm_module_loader.c
Note: The files within security/intel/stm come directly from their
Tianocore counterparts. Unnecessary code has been removed and the
remaining code has been converted to meet coreboot coding requirements.
For more information see:
SMI Transfer Monitor (STM) User Guide, Intel Corp.,
August 2015, Rev 1.0, can be found at firmware.intel.com
include/cpu/x86:
Addtions to include/cpu/x86 for STM support.
cpu/x86:
STM Set up - The STM needs to be loaded into the MSEG during BIOS
initialization and the SMM Monitor Control MSR be set to indicate
that an STM is in the system.
cpu/x86/smm:
SMI module loader modifications needed to set up the
SMM descriptors used by the STM during its initialization
Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Add detailed instructions on how to unlock protected SPI ranges and
flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by
exploiting stock BIOS security issues.
Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst
to deep in order to met power off timing.
BUG=b:143733039
TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We set MPS to speed_to_default_mps(speed) initially
but later compare maxpacketsize with 8 to change mps.
So compare with speed_to_default_mps(speed) to determine
if we need to change settings here.
BUG=b:147783572
BRANCH=none
TEST=works with 12Mbps/8MPS USB device
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38556
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Enable PCIe port for dGPU
2. Change WLAN PCIe port from port 14 to port 7
BUG=b:147249494
TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.
Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1
BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting.
They should be NF1.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This change adds support for allocating resources for PCI express hotplug
bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI
subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of
non-prefetchable memory, and 8 KiB of I/O space to any device with the
PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which
indicates hot-plugging capability. The resource allocation is configurable,
please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig.
In order to support the allocation of hotplugged PCI buses, a new field
is added to struct device called hotplug_buses. This is defaulted to
zero, but when set, it adds the hotplug_buses value to the subordinate
value of the PCI bridge. This allows devices to be plugged in and
unplugged after boot.
This code was tested on the System76 Darter Pro (darp6). Before this
change, there are not enough resources allocated to the Thunderbolt
PCI bridge to allow plugging in new devices after boot. This can be
worked around in the Linux kernel by passing a boot param such as:
pci=assign-busses,hpbussize=32,realloc
This change makes it possible to use Thunderbolt hotplugging without
kernel parameters, and attempts to match closely what our motherboard
manufacturer's firmware does by default.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The eltan verified_boot is using the vboot 2.1 data structures and code,
as well as the fwlib21 build target, they are all deprecated. Refer to
CB:37654 for more information.
The verified_boot code is updated to use the vb2 structures and code and
make sure only public functions are used.
BUG=N/A
TEST=build
Change-Id: I1e1a7bce6110fe35221a4d7a47c1eb7c7074c318
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This define is used to set up the STM SMM Descriptor table tr entry.
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: Iddb1f45444d03465a66a4ebb9fde5f206dc5b300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ClearControl Function which is needed for a follow-up patch.
Change-Id: Ia19185528fd821e420b0bdb424760c93b79523a4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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BUG=b:139481313
Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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With Audio DSP OSC qualification disabled from S0ix criteria.
S0ix is achieved before the DSP is suspended. When driver tries
to suspend DSP its already turned off.
BUG=b:139481313
Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate CPUID entry between KBL and CFL.
CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL
CPUID (0x806EA) for CFL-D0.
TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with
CPUID 0x806EA.
Change-Id: I078dd7860891896b512967dc8dec5dd94d069193
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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The current MP init timeout is hardcoded as 1s. To support
platform with many cpus, the timeout needs to be adjusted.
The number of cpus is calculated as:
number of sockets * number of cores per socket *
number of threads per core
How long the timeout should be set to, is heuristic.
It needs to be set long enough to ensure reboot stability,
but not unreasonable so that real failures can be detected
soon enough, especially for smaller systems.
This patch sets timeout to be minimum as 1 second, while each
cpu adds 0.1 second.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The SMBus support is identical between stoneyridge and picasso.
Unify on common support code.
Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Set HeciEnabled = 1 on puff device tree to turn on
Intel ME communication interface.
BUG=b:143232330
BRANCH=None
TEST=Build puff and boot up OS.
ran lspci and confirmed there is a HECI device.
00:16.0 Communication controller: Intel Corporation Device 02e0
Change-Id: I2debb885022ae31e395869d014a91824b5dd980c
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iac3ae21a381119bd0f24f68d4dd991817f2ff51f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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libpayload passes argc and argv to main(), and ignoring these arguments
causes a compile time error when using LTO.
Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 6ef33b99:
2019-11-22 Hung-Te Lin futility: updater: refactor: unify
getting temp files for firmware images
to commit id 0e97e25e:
2020-01-23 Julius Werner 2lib: Fix struct vb2_hash the way it was
meant to be
Change-Id: I539aba2f283804f67ff3ff4f98324b3d10b2bb54
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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According to the C standard, accessing the NULL pointer (memory at
address zero) is undefined behaviour, and so GCC is allowed to optimize
it out. Of course, accessing this memory location is sometimes
necessary, so this optimization can be disabled using
-fno-delete-null-pointer-checks. This is already done in coreboot, but
adding it to xcompile will also disable it for all the payloads. For
example, coreinfo compiled with LTO libpayload crashes when this flag
isn't set, presumably because the compiler is optimizing something out
that it shouldn't.
Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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acpi_device_scope() will return NULL if it is unable to find the path
of the parent device. Return early if this is the case to prevent a null
pointer dereference.
Change-Id: I3eff1c1e3477c75c7130b52898de7d59692ba412
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1409672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38669
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is found that keyboard backlight in T440p is enabled by clearing
bit 3 of EC RAM 0x01. This patch sets has_keyboard_backlight in
devicetree.cb and also corrects the CMOS configuration.
Change-Id: Ib4c2b1591d26e2bb33f9549e3933efe9a6e0b043
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Dennis Witzig <dennis@wtzg.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Configure xHCI, xDCI according to board design
BUG=none
BRANCH=none
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Asserting reset in RO instead of in RW has no impact on security or
performance, but it does limit improvements to this process later.
This fix removes reset line control from RO and makes these variants
consistent with other hatch variants.
This fix reinforces the concept from commit fcd8c9e99e
(hatch: Fix FPMCU pwr/rst gpio handling).
BUG=b:148457345
TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Configure GPP_H22 as output pin for BOMACO mode enabled.
BOMACO stands for "Bus Off Memory Alive Core Off".
BUG=b:146081272
TEST=emerge-mushu coreboot
Change-Id: Ic35e55771d76b7254bcb457fcb38f37433b9ad67
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38210
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set CPU ID and cores to EC then EC will adapt power table
according to the CPU ID and number of cores.
BUG=b:148126144
BRANCH=None
TEST=check EC can get correct CPU id and cores.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37944
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For the up-to-date list of Windows versions follow this link:
https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi
Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This GPIO dumping was implemented using the
Document Number: 341080-001
Intel® 495 Series Chipset Family On-Package Platform Controller Hub
Volume 1 of 2
datasheet. The GPIO community ports can be found in table 36-1, while
the community and pin descriptions are taken from
linux/pinctrl/intel/pinctrl-icelake.c .
This commit was tested on the late 2019 Razer Blade Stealth with 1065G7
and Chipset 495 PCH and the output manually compared against
linux/pinctrl-intel.
Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Newest clang compilers warn about "misleading indentation", and because
warnings-are-errors in our builds, that breaks the build.
The lzma code base is vendored in, so we might just have to update it,
but that's a bigger effort than just removing a couple of spaces (the
coding style of the file is horrible, but I will only change it as much
as the compilers ask for).
BUG=chromium:1039526
Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove EC_HOST_EVENT_MKBP from kohaku's EC_SCI_EVENTS mask, so that
MKBP events don't generate an SCI. The EC is also being changed to use
host events to wake up the system, and use the EC_INT_L line for MKBP
IRQ signalling. Otherwise, there would be two IRQs generated for MKBP
events.
BUG=b:144122000
BRANCH=firmware-hatch-12672.B
TEST=System shows ACPI interrupt as the wakeup IRQ, and the
MKBP host event is properly processed as well.
Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new functions to get (from the EC):
1) The number of USB-PD ports
2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS)
BUG=b:146506369
BRANCH=none
TEST=Instrumented calls to these and verified the data
Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The new host command provides these static capabilities of each USB-PD port:
1) Port number
2) Power role: source, sink, dual
3) Try-power role: none, sink, source
4) Data role: dfp, ufp, dual
5) Port location: these come from power_manager
BUG=b:146506369
BRANCH=none
TEST=compiles
Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The help output suggests clean-docker should be used to remove the
docker coreboot containers and images. The Makefile actually supports
the docker-clean target.
Corrected the help output to reflect the actual Makefile target.
BUG=N/A
TEST=build
Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
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Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37295
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the multiplications with corresponding shifts, so that it's
easier to see at which bit offsets the values get assigned.
Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch overrides CPU flex ratio on hatch in order to get
better boot time numbers in vboot_reference.
BUG=b:142264107
TEST=Able to save ~100ms of platform boot time while running with
lower cpu flex ratio (i.e. freq ~1500MHz)
Without this CL
1100:finished vboot kernel verification 802,443 (148,108)
With this CL
1100:finished vboot kernel verification 685,382 (46,496)
Change-Id: Idd1d1c0c04b1f742f17227a1335f27a956ee940d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36865
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Explicitly state that the assignment is missing in the devicetree. In
the case of the warnings, the missing assignments might not be an issue.
Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In glibc feature control macros, _DEFAULT_SOURCE is the shorthand to
tell glibc to enable "all the default stuff", meaning POSIX, BSD and
System V interfaces. However, this macro is somewhat recent and older
glibc versions (e.g. 2.12) are still occasionally in use that don't
recognize it yet. For the benefits of users with these versions, let's
also enable the deprecated _BSD_SOURCE and _SVID_SOURCE macros which
essentially achieve the same thing. We must continue to define
_DEFAULT_SOURCE so that newer glibc versions don't throw a deprecation
warning.
This patch should make BSD-style byteswap macros like le32toh()
available on these older glibc versions.
Change-Id: I019bbcf738a1bcdccd7b299bdde29cd4d4ded134
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The SMBus function declarations were duplicated. Use the common
ones provided by smbus_host.h.
Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The timeout is fixed and only used in one place. Put the assumption
in the compliation unit utilizing the defintion.
Change-Id: I93c061e74df6b4265fd1c61fc4669410ebc9554f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The fixed bus speed of 400 kHz doesn't need to reside in a header file.
Just move the assumption into the code itself.
Change-Id: I8bb68607070d0daeae2ad3bcd79f49d5c20048fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The SMBus function declarations were duplicated. Use the common
ones provided by smbus_host.h.
Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The timeout is fixed and only used in one place. Put the assumption
in the compliation unit utilizing the defintion.
Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The fixed bus speed of 400 kHz doesn't need to reside in a header file.
Just move the assumption into the code itself.
Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to
some value which can't be overriden outside of soc/intel/common. So
adding a non-SoC platform thats uses code from soc/intel/common is not
possible.
TEST=build test on wip platform
Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
|
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Change-Id: Iae8d4f0470f75b47e53c50790f06902acb9a24cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f $(find util -name '*.[ch]')
Change-Id: I059071fd3a2edb41c72fc57fccbb520bd2ebb757
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f $(find src/superio -name '*.[ch]')
Change-Id: I36fd8cfeffdaf81d7ac646bab7ffac3e36c77879
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Update the security document to reflect the current state of the
coreboot implementation.
Add more detail and document the change to the public vboot API.
BUG=N/A
TEST=build
Change-Id: I228d0faae0efde70039680a981fea9a436d2384f
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Intel docs also call it "Scalable Bus Speed", so the typo is on us.
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/msrtool/*.c
Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/cbfstool/*.c
Change-Id: I13a27407bf2bad4b9fadcec8cdbd5889068f13cf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38633
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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commit 1191c09201b43aab55333a70d056d0c355abe329 at
https://salsa.debian.org/agx/lintian/tree/master/data/spelling provides
a much more comprehensive collection of misspellings, so merge it in.
While at it, also sort the file for future easier merging which is the
main reason that some lines appear to be removed: they're merely moved.
For sorting, I adapted their make rule:
make -f - sort-spelling.txt <<'EOF'
.RECIPEPREFIX=%
sort-%: %
%csplit --prefix $<- $< '/^$$/'
%LC_ALL=en_US sort -u $<-01 | cat $<-00 - > $<
%rm -f $<-0[01]
EOF
Change-Id: I939e3a8820c88d0e639bd29b46a86b72bce1a098
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38632
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The authors from the header of the files are added in a previous commit.
Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6d56380beef7023c60d6fbb47c520ec6f6a7c9db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4821c48ccac92f412126cea0f22cca5fd8bf8647
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
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Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for
the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH.
Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become
lively again.
BUG=b:147026979
BRANCH=none
TEST=Boot puff and do 1500 cycles of S0ix.
Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38523
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for
the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH.
Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become
lively again.
V.2: Ensure reset_gpio && enable_gpio are optional.
BUG=b:147026979
BRANCH=none
TEST=Boot puff and do 100 cycles of S0ix.
Change-Id: I3ae8dc30f45f55eec23f45e7b5fbc67a4542f87d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Allow for making both reset_gpio && enable_gpio as optional in
the params by fixing a potential NULL deref and defaulting to
zero values.
BUG=b:147026979
BRANCH=none
TEST=builds
Change-Id: I8053d7a080dfed898400c0994bcea492c826fe3d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add Word/DWord/QWord Address Space Descriptor helper functions.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I707f8a443090b6f30e2940b721f9555ccdf49d32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Update to reflect the beta status of the code.
BUG=N/A
TEST=build
Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch adds CMP-H LPC IDs.
TEST=Build an image and boot with discrete TPM chip.
Enable measured boot and kernel could get the measured
data from TPM chip.
Change-Id: I7eac8b0514f79b47a05973210e2472dd1dc3d0ed
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38251
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's symmetric to the code found in 00730F01 northbridge.
Change-Id: I1ee439213ff128b534f5bf130661d0ae2b9558ab
Signed-off-by: Jorge Fernandez <jorgefm@cirsa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37547
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The fwts method test reports errors on the methods implementing
processor throttling control. The T states are not supported in coreboot
at this moment.
Remove the methods required by processor throttling control. They can be
restored when the required support has been added to the SoC
implementation.
BUG=https://ticket.coreboot.org/issues/252
TEST=tested using fwts on facebook monolith.
Found-by: fwts 19.12.00
Change-Id: Ib50607f60cdb2ad03e613d18b40f56a4c4a4c714
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Remove two blank lines and reorder functions by read/write sizes.
Change-Id: I7bd6ed44546d49b65135a98e424a5669d90f2867
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38146
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add description of the procedure to create the flash components for this
system.
BUG=N/A
TEST=N/A
Change-Id: I2690dfbe715fa120f840d98c57fdc3fd7e8b45b1
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I66e2cfd041f9a93668e41d79c40cec9cb1bd917e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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TGL FSP does just pin mux for image clock pins by UPD and image clocks
are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder.
Disable image clocks by UPD for bypassing FSP pin mux and do pin mux
in gpio.c according to board design.
BUG=none
BRANCH=none
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pin mux for IMGCLKOUT_0 and IMGCLKOUT_1
BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux for
Image clocks pins(GPP_D4, GPP_H20)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ifb0c2b17dd481ef6c19bdf9ee84f47ef08d7b9a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Change-Id: I932bd0cb97507fa159d1fe3cf2335beb31ca1caf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibd6f6bf7983382901a5327121d277606f609eca4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ie6c94c0627743f9e965347ecfd28f1b0441178ad
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38516
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This makes diff between boards even smaller in some cases.
Change-Id: I42ecaf5de657275708ddaf2c926fe31fe16a7220
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux
from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux
from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With UART3 and 4 enabled, the serial console in LinuxBoot crashes. This
is a short-term solution until we found and fixed the original bug.
Change-Id: I75cb387ef12944232b51f6d8d41810bb27754b05
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Add helper functions to get board's sku_id and fw_config. Enable
EC_GOOGLE_CHROMEEC_BOARDID to get board_id. Add board's SKU ID and
OEM name into SMBIOS table.
BUG=b:144768001
TEST=Build Test.
Change-Id: Id1729e245accf5acc29307a22721362fb1ce0878
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38551
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:148221635
TEST=build;install;lspci
Change-Id: I1732f7fe64ace41a721a2d6a964988efc97b2579
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38550
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The names of each spi flash cause quite a bit of bloat in the text
size of each stage/program. Remove the name entirely from spi flash
in order to reduce overhead. In order to pack space as closely as
possible the previous 32-bit id and mask were split into 2 16-bit
ids and masks.
On Chrome OS build of Aleena there's a savings of >2.21KiB in each
of verstage, romstage, and ramstage.
Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.
Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).
Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.
Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Fix a non-standard larger picture not handled in time before merging.
Change-Id: Ia494484cd0eff6b19408b065264911d0093ceeb0
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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Types from stdint.h are used in that header file without stdint.h being
included.
Change-Id: I71449dd26162dc8420c206285896ac9a8e4e04d4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The two defines are identical, so deduplicate this.
Timeless build for lenovo/x230 results in identical binary.
Change-Id: I32e0eee88d72eb6f8dc71b0324d62f46079120a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The GLK bootblock seems(?) to be hard limited to 32KB and some Octopus
variants are so close to that that they only have 0.5KB left. This is
blocking development of new core features, so let's disable the
bootblock console to gain a couple of KB back (like we already did on
RK3288).
There are probably other opporunities for code size reduction here (e.g.
it seems that almost half(!) of that whole bootblock size is taken up by
devicetree.cb structures), but I'm not familiar enough with the platform
to dig into them.
Change-Id: I05b4ecf5abef7307e3d0a81db04a745ff3da0c42
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38521
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie1d0a2ed9aa5c0645fa8400ec9af17be592d3dea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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