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Use common SoC drivers for DRAM calibration support.
TEST=build pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Remove emi.h because emi.h is defined in common/include/soc.
Add dramc_param.h and dramc_soc.h to prepare for implementation of
DRAM full calibration.
TEST=build pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie03f7049b013648372b002ce9b731589b1fffabd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2416456bd447a6296ca3fac6cf90aa2e78f6de57
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I36a02f8d509ef39983b4162188abc0cbc3d570cf
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I445dbe5d1f744c6512d618efdc927509d5ba291f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I1c438e53adc835df0a3f9436f94e0f5341cf79dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: If4ba4b2a7a358ad86b547b16a12593b912f9bd8f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I2287ae1357e0f02a42ebd770ee799613fd29c033
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I7691cf37da03e6a689efcb84527ba519fe661258
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ifc6708c2e864e5dcba12d53af24993dc173fca7f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I019ba38015b245f69c9663fd93775409c7d9cb1b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I7e99a44dcb512f0eb4355663cdc8dac690211dab
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Icd58cd466c8e85625170bb14e66fc068758883f5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I22e189dfa9b8944341aafcafe4e97dca65558937
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I545a1111e24f45f732f1c325c808737dfb6bcae6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Previously (before CB:56965 [1]) mtk_dsi_send_init_command() would
ignore NULL initialization commands passed to it. However, in the
current code mipi_panel_parse_init_commands() doesn't check that (see
CB:57150 [2]), so we should check it on the caller side from
mtk_dsi_init().
[1] b2a1480191 device: Move MIPI panel library from
mainboard/google/kukui into common
[2] 4757a7ea33 mipi: Make panel init callback work directly on DSI
transaction types
BUG=b:202871018, b:209930699
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
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PS8640 is a low power MIPI-to-eDP video format converter.
VRF12 does not provide power to PS8640 on krabby.
In original patch, VRF12 is not used, and is set to hardware control
for low power. We change the setting to remove hardware control.
Therefore, if we want to control VRF12 by software, we can control
it directly.
BUG=b:210806060
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add basic devapc (device access permission control) drivers.
DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.
1. Initialize devapc.
2. Set master domain and secure side band.
3. Set default permission.
BUG=b:202871018
TEST=build pass
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Move some definations of devapc for sharing between MT8195 and MT8186.
BUG=b:202871018
TEST=emerge-cherry coreboot; emerge-corsola coreboot;
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before
DRAM calibration. When we check cbmem, we found the content of this
memory is unreadable.
The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.
BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Current mainboard code supports different baseboard binding
example: brya uses BOARD_GOOGLE_BASEBOARD_BRYA and brask uses
BOARD_GOOGLE_BASEBOARD_BRASK Kconfig.
This patch makes the `BOARD_GOOGLE_BRYA_COMMON` Kconfig default
`n` and specific baseboard binding Kconfig can select this Kconfig.
It would also avoid adding if clause for specific baseboard binding
Kconfig everytime with introduction of newer mainboard in future.
TEST=Verified CONFIG_BOARD_GOOGLE_BRYA_COMMON=y while building brya
and brya coreboot.rom remains the same.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I754159447e68b8ac2ea21009cc801fc5ba5df56e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This patch ensures ADL-P PCH can get selected by mainboard
variants to accommodate mainboards with ADL-N PCH in future.
TEST=Able to build and boot brya without any Kconfig change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifbcd1cd7f8ecafee22d50c3f3f20decc4cc62797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60378
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1416d8f783518eca0606efef4314a3d86837b016
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The intel-spi driver maps the BIOS region of the flash as an mtd device
at /dev/mtdX. Since this system is intended for development purposes,
disable its write protection.
Change-Id: Ib73d14eb4e7df6e29433b8dfbeb77dbab4a85f08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Config options and package names might change from channel to channel.
Thus, don't let nix-build depend on the locally configured NixOS
channel, but instead let `nixpkgs` point to a specific channel to ensure
that always a compatible channel is used.
For now, let `nixpkgs` point to NixOS 21.11, which is currently the
latest stable release. This needs to be updated after a new release.
Change-Id: Ia77c34f93f0e2c3d351ae229830adfce75a56ae4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Merge build scripts to `build.sh`. The new one takes the desired NixOS
config as an argument.
Example:
$ build.sh console.nix
Change-Id: I49360a5c57954a205c697a4ae07361779db2aa83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60372
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is a design issue of bit shift which will drop a bit for
USB3 phy on MT8195. Therefore, we add this patch to set USB phy
registers from value of efuse.
BUG=b:211528577
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copied from commit df72b18d (mb/google/brya/var/taeko: Set vGPIO reset
type).Due to the vGPIO is not reset when we power on through S5, we
would met MCA when PCIE send L1 request without following Ack.
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add parentheses around the parameter of the `USB_PORT_WAKE_ENABLE`
macro to prevent unintentional operator precedence problems.
Change-Id: I61fbacc129cbfb42ade7e64ee40cd07c98d87683
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I0e296b3efbff0260f32badc699f1062f9885fa53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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v2471_02""
This reverts commit a4dddfc3a3a48727ebcec727a0b1fd87eb4c14ad.
Reason for revert: Ready to land FSP 2471.02
Change-Id: I2d858edee2eb24506c3e55a1cb808a1ccbd58da2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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AMD SDLE testing had been done and apply the following telemetry settings for dewatt:
vdd scale: 95359
vdd offset: 449
soc scale: 31481
soc offset: 193
BUG=b:211566312
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE test
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I597a51ca599eff2abc9640aba5f3c804a686f057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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It makes sense to provide limits.h via the types.h header.
Change-Id: I3ba189b998644c68068b85f25b11cff4d70c037d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55320
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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futility actually depends on flashrom. Previously it
was of the form of subprocess and now uses the libflashrom
API directly. Due to the previous subprocess decoupling it
was not obvious that the dependency existed however not
the runtime requirement is also a strict buildtime requirement.
Therefore update the Makefile accordingly.
BUG=b:203715651,b:209702505
TEST=builds
Change-Id: Id9744424f75299eb8335c1c0c2aca2808bde829d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
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Lists of changes:
1. Create choice config to let ADL mb variants to pick the desire CAR
setup configuration between NEM and eNEM, where NEM and eNEM Kconfig
have selected its required IA SoC common CAR Kconfig to able to perform
the early boot configuration using CAR.
2. Lists of variants (kano, redrix, and felwinter) to drop
INTEL_CAR_NEM Kconfig select and choose eNEM.
3. Default CAR configuration for ADL mb is still NEM due to still using
older SoC skus without eNEM support enabled.
BUG=b:168820083
TEST=Able to build and boot P2 boards using eNEM mode.
Change-Id: Ibe94e6b82739ec65829859271622d904d75e978d
Signed-off-by: subratabanik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I4de9bc426b92d57d6aabe17cceddf6b6aa444327
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I31df9c339821074493329f6ed8fb1559b9e1a793
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Idb7fcaaa175eb5b6e953ad0d5e2c5757d18838e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6698c3882a3019e7e8f86fcb4e1c456e362d74b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Align with other mainboards and put the baseboard option before the
variants ones.
Change-Id: I314239b6d5abd531ccdcbe4426b2c7956dc9ae45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I52c79f8958c5c40a258bcc292702154765afc476
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ia9c59917196df8226391765f7dd7b7c5cdad1aee
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I013a6250727040c289244c31fbfbffef5ed0730b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since all variants select the option `BASEBOARD_REEF_LAPTOP`, drop it
and let the common baseboard option select it.
Change-Id: I7f2ffd1e7b9ad2fab500b83c4cc56c9fc2d161ab
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/
conn: Change usb{23}_port_number fields to device pointers) changed the
way the pmc_mux/conn driver gets the corresponding USB ports from the
devicetree. This change didn't include the corresponding change for the
Taniks and Vell variants of the Google Brya project and the Intel
adlrvp_n_ext_ec board which probably weren't in the tree at the time the
patch referenced above was created. This patch ports the needed change
forward to those boards to fix the build of the upstream tree.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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List of changes:
1. Add separate file for ADL-N GPIOs
2. Configure GPIOs as per the schematics of ADL-N RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram).
BUG=b:210755120
TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Run the command below to fix all occurrences.
$ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,'
Change-Id: I84669341e2c8976953284dbaf113da3397857de3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Run the command below to fix all occurrences.
$ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,'
Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.
Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Support GL9763E as a eMMC boot disk
BUG=b:210089379
TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taniks.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add Kconfig item RT8168_SET_LED_MODE to enable LED customization.
Update the LED settings in devicetree.
BUG=b:193750191
TEST=Try different register values to verify LED feature.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Realtek RTL8125 has four registers for four leds
and a feature config register.
We use led0 and led2 in brask, so modify ethernet driver.
Those registers' IO address are based on RTL8125 datasheet.
BUG=b:193750191
TEST=Modify overridetree.cb to verify LEDs' settings.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell:
DRAM Part Name ID to assign
H9JCNNNCP3MLYR-N6E 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The board ID check for audio codec is no longer required, therefore
remove it.
BUG=b:210705216
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Enable Acoustic noise mitigation
- Copied from gimble set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch add timestamp around cse_fw_sync().
TEST=Verified on Brya, cbmem -t:
948:starting CSE firmware sync 1,381,577 (45,227)
949:finished CSE firmware sync 1,459,513 (77,936)
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add the stylus field in fw_config.
Update devicetree and gpio to handle stylus pen detection.
BUG=b:167983049
TEST=Build firmware and check behavior as following:
1) Set the fw_config "bit4=1" for pen present:
Wake up from suspend when pen is removed from the garage.
Present the stylus menu when pen is removed from the garage.
2) Set the fw_config "bit4=0" for pen absent:
Wake up and present menu will not work when pen is removed
form the garage.
Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.
Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10
Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O
Untested:
- VBT (it is included, though)
- Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Writing a coreboot image without a payload to a board's flash chip will
result in a non-bootable system, so warn the user if this is the case.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL
2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants)
BUG=b:203014978
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
vdd scale: 73457 -> 73331
vdd offset: 291 -> 1893
soc scale: 30761 -> 31955
soc offset: 834 -> 852
BUG=b:207299255
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE/Stardust test
Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Add support for Alder lake N LP5 RVP with board ID 0x7.
Since SPD index 7 is unused earlier, ADL-N will use it.
Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This patch introduces new FlashMap API, the fmap_locate_area().
It works on cached FlashMap provided in lib_sysinfo.fmap_cache.
Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload
build directory as a base, instead of installing it first. This caused
include errors, because commonlib/bsd is not present there. This patch
introduces comonlib/bsd include path to lpgcc CFLAGS if it is being
built using libpayload build directory as a base.
Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Remove SD controller configurations based on the beadrix's schematic.
BUG=b:204882915
BRANCH=None
TEST=Built test coreboot image
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds internal USB camera into devicetree for beadrix.
BUG=b:204882915, b:210772511
BRANCH=None
TEST=Built and checked camera device existence with lsusb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix.
BUG=b:204882915, b:210756131
BRANCH=None
TEST=Built and heared speaker sound on OS
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds PIXA touchpad into devicetree for beadrix.
BUG=b:204882915, b:203113111
TEST=Built and verified touchpad function
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Using Vbt.bin version 244, with the following changes:
* Add 200ms delay to sink (T3) to avoid no response to AUX Channel
transaction, which manifests as a repeating, colourful flicker.
* Increase maximum supported refresh rate to 120Hz
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
BUG=b:203837656
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable SaGv support for anahera/anahera4es.
BUG=b:211362081
TEST=FW_NAME=anahera emerge-brya coreboot
Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI
table), PLD is added to ACPI table. It causes the DUT to not boot into
the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2
to solve this issue.
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
BUG=b:209723556
BRANCH=none
TEST=build coreboot and boot into OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below.
CC ramstage/southbridge/intel/common/rcba_pirq.o
src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq':
src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n",
| ~~^
| |
| long int
| %d
87 | dev_path(dev), int_pin - PCI_INT_A,
88 | pirq_idx(pin_irq_map[map_count].pic_pirq));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka unsigned int}
The return value of `pirq_idx()` is of type `size_t`, so use the
appropriate length modifier `z`.
Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476
Found-by: gcc (Debian 11.2.0-13) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Currently, the pmc_mux/conn driver uses integer fields to store the
USB-2 and USB-3 port numbers from the SoC's point of view. Specifying
these as integers in the devicetree is error-prone, and this
information can instead be represented using pointers to the USB-2 and
USB-3 devices. The port numbers can then be obtained from the paths of
the linked devices, i.e. dev->path.usb.port_id.
Modify the driver to store device pointers instead of integer port
numbers, and update all devicetrees using the driver. These are the
mainboards affected (all are Intel TGL or ADL based):
google/brya
google/volteer
intel/adlrvp
intel/shadowmountain
intel/tglrvp
system76/darp7
system76/galp5
system76/lemp10
Command used to update the devicetrees:
git grep -l "usb._port_number" src/mainboard/ | \
xargs sed -i \
-e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \
-e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g'
BUG=b:208502191
TEST=Build test all affected boards. On brya0, boot device and check
that the ACPI tables generated with and without the change are the same.
Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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USB ports
Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4).
BUG=b:199468920
TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics
BUG=b:208756696
TEST=emerge-brya coreboot
Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37
Signed-off-by: = <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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update override devicetree for touchpad based on schematics
BUG=b:209554950
TEST=emerge-brya coreboot
Change-Id: I835958349537ed490191db7c8e35847630de64ed
Signed-off-by: = <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Because of a typo, `bootblcok-y += rtc.c` does nothing. Drop it.
Change-Id: Ife2ee152ab32ef23df5986c47bec490db592ab60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56216
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes unused header inclusion as <commonlib/helpers.h>
from several mainboard gpio definition files.
Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae
Signed-off-by: subratabanik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Some SKUs of google/taeko have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:204343849
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The Bayhub LV2 has a known errata wherein PCI config registers at
offsets 0x234, 0x238, and 0x24C will only correctly accept writes
when they are addressed via a DWORD (32-bit) wide write operation
on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop
latency register, therefore add a finalize callback to this driver
which will program the LTR max-snoop/no-snoop register with a 32-bit
write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849
TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Some device drivers may need to get access to the LTR values for their
respective devices, therefore export this function instead of marking it
static.
BUG=b:204343849
Change-Id: Id372600e8adec0d55d3483726bb9353139685774
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change in power sequencing appears to fix issues with power
consumption of the SD card controller. Possibly this change
ensures the device has enough time to properly initialize itself
after reset is deasserted but before it is accessed.
BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This causes the I2C touchpad device to stop working after warm reboot.
BUG=b:210701402
BRANCH=none
TEST=after warm reboot, the touchpad still works.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60126
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on schematic G570_MB_CHROME_1207_1630_ADC and gpio table of
taniks, generate overridetree.cb settings for taniks.
BUG=b:209926534
TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This reverts commit ae0ea32c52905d6bcb527b04727463bc2d1b9e09.
This change should not have merged until the 2471_02 FSP change is ready
for merge.
BUG=b:211481222
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0
to kernel.
Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Id71c63556da73a09c5a6d3e844686ddc3e113ea7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I9578dd7cd4766b4b2ce8fb14992b1ef4701d9878
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I5bda94b20da4c9184cef2a39598e25a214c044b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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These variant-specific options are only selected by their board options
and are not used for anything else. Thus, merge their selects into the
board options and drop them.
Change-Id: I0eb3fdc4fd7306e76d5479494e3ab80bbdb984fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I462426f2ef4a0ff62c0a7c1eb2a4946fba68c4a9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will
cause verstage to run during s0i3 resume. The TPM will be reinitialized
in verstage during s0i3 resume. This is necessary on guybrush boards
because the TPM_RST_L pin is asserted by the SOC in S0i3.
BUG=b:200578885
BRANCH=None
TEST=TPM initialized after s0i3
Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.
BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.
Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Build-test the configuration Prodrive uses to build coreboot for their
Hermes mainboard.
Change-Id: I62e79d3143851bf14dfdbe70e60c60f13dd06c3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
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The patch defines new TS for CSE firmware synchronization.
Also, removes unused TS_FIT_UCODE_LOADED TS.
TEST=Build the code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59668
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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