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Convert multiline Redhat package list to one-line code markup.
Change-Id: I1ba38bf2fc767a3f1694c55cf50e137ce10bfd75
Signed-off-by: Juan José García-Castro Crespo <jjgcc@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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IOEX was replaced with GPIOs, this CL makes the required changes
BUG=b:325533052
TEST=Built FW image correctly.
Change-Id: I09ebba336b179cb36c6801b47ee0be5ade08c257
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80570
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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GPP_F19 and GPP_F20 sre set incorrectly previously. Change them to not
connected according to schematics.
BUG=b:305793886
TEST=Built FW image correctly.
Change-Id: Ifb6da1f8696f44cb47be3d1de83c55e62b12a9e9
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80569
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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In preparation for the upcoming release, add the template for the
24.05 release and update index.md.
Change-Id: Ic8fdf82519ffa4001bcc06bdd808eaebdde18a1e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This is needed to build opensil. With meson and ninja added to the
coreboot-sdk image there is no need have them in the jenkins node image.
Change-Id: I36188ae895f2a770f1dc4528f332c09bf386db73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Missing pkg-config and libcrypto when building coreboot (Step 6) on
Debian 12 (bookworm). Add required packages to Step 1, libssl-dev and
pkg-config.
Change-Id: I5df06611a934d1ef85c8335764f4f6e0f241c9a9
Signed-off-by: Juan José García-Castro Crespo <jjgcc@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80722
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When we're building non-AMD processors, don't bother building amdfwtool
unless we're specifically building all of the tools like for abuild.
Change-Id: I9021674a06d65a79e24020790d317ab947c505fe
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation to merging all the other HP sandy/ivy desktops in here
as variants.
Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into
variant directories.
Kconfig:
Move options not common to the others under the variants instead.
devicetree:
Move XHCI to variant overridetrees (8200 gen has no USB 3)
board_info.txt:
Make it more generic. It seems to be copied from 8200 SFF and
inaccurate to Z220 anyway.
TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and
SFF ROMs are (SHA1) same as before.
Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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The GNU BFD linker makes a good guess that this section should not be
loaded, however other linkers like LLVM LD need this to be made explicit
in order for the section to have the NOBITS, rather than PROGBITS
attribute set.
Change-Id: I3ca7221d10f144f608823e0b9624533780fbf335
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80735
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Starting from MT8195, MediaTek platform supports "dram adaptive" to
automatically detect dram information, including channel, rank, die
size..., and can automatically configure EMI settings. So we can just
pass a placeholder param blob to `mt_mem_init_run` by enabling this
option.
Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive"
need to implement `get_sdram_config` to get onboard DRAM configuration
info.
TEST=emerge-geralt coreboot && emerge-asurada coreboot
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada
Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboards using Intel Twin Lake (TWL) SoC shall select
SOC_INTEL_TWINLAKE.
BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie4c5d137ee54512313344f853e7ca66d1fd25003
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80688
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No rmodule was using heap.
Change-Id: I0bc049a5231dabbec1c962a99ef875eddcc4ac6e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
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v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/deku using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
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v
romstage (A20/1)
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v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Karis has RO locked, any change in the bootblock won't be
applicable for FSI'ed karis devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is
TEST=Able to build and boot google/karis using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
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v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/ovis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
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v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/rex0 using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
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v
romstage (A20/1)
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v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Screebo has RO locked, any change in the bootblock won't be
applicable for FSI'ed screebo devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is.
TEST=Able to build and boot google/screebo using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80640
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I17758e23da25d610a0b462dfd388c53b89315242
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was
not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor
Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping".
Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is needed in order to move device_tree.c into commonlib in a
subsequent commit.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch passes the correct flag to vboot to enable SIMD crypto
acceleration on arm64 devices. This uses a core part of the ISA and
should thus be supported on all arm64 SoCs -- so we normally always
want it enabled, but there should still be a Kconfig in case a SoC wants
to use the hwcrypto interface for its own (off-CPU) crypto acceleration
engine instead. (You could also disable it to save a small amount of
code size at the cost of speed, if necessary.)
Change-Id: I3820bd6b7505202b7edb6768385ce5deb18777a4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Updating from commit id 3d37d2aa:
2024-01-15 Makefile: Support FIRMWARE_ARCH=mock for firmware unit tests
to commit id 09fcd218:
2024-02-22 Makefile: Test compiler for -Wincompatible-function-pointer-types
This brings in 26 new commits:
09fcd218 Makefile: Test compiler for -Wincompatible-function-pointer-types
00e8c2d8 tests: Run hwcrypto RSA tests for arm64
d3387824 firmware: Add vectorized modexp() implementation for arm64 (NEON)
8856e04b tests: Stop exporting ENABLE_HWCRYPTO_RSA_TESTS to test scripts
6abd9cc0 Makefile: Separate ${ARCH_DIR}, split arm/arm64, remove symlinks
e7f567d1 test_update: Skip ifdtool-dependent tests when not available
1a0f8df8 libvboot_host: Check for undefined symbols
c0806280 vboot_host: Expose dynamic library
2ff5784d vboot: Remove 2kernel.c from vboot_host library
6e472468 Add crdyshim keygen script and devkeys
8a711468 scripts/keygeneration: Move generate_ed25519_key to common.sh
57e2092d scripts/image_signing: Call futility instead of its symlinks
0fa2ea47 scripts/image_signing/make_dev_ssh.sh: Improve parameter removal
1d32db3b Makefile: Remove genfuzztestcases from runtestscripts prerequisites
f6ff822b README: Add 'futility sign' and 'futility verify' to useful utilities
a717c83d tests: Replace vbutil_{firmware,kernel} with 'futility sign'
94c82417 *.sh: Unify indentation with 2 spaces
23d25957 utility/dev_debug_vboot: Replace vbutil_firmware with 'futility verify'
fd20901f cgpt/futility: bundle as a subtool
dccc5a31 image_signing: Add support for signing Flexor kernel image
660b6675 futility/cmd_show: Add "::verified" summary to vblock parseable output
2fcff1e4 tests/*.sh: Replace vbutil_firmware with 'futility verify'
c6b13823 make_dev_firmware.sh: Replace vbutil_firmware with 'futility show'
d260d094 firmware: 2modpow_sse2: Clean up calculation of `mu`
2596679a Add -Wint-conversion and -Wincompatible-function-pointer-types
39fb6201 futility: update: Use ifdtool to unlock ME
f8016c2b make_keyblock: change to parsing key prefix
Change-Id: Ibc6daef30092b1b31f3dd08f3aed02ba31fd12d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Use clrsetbits32p instead of clrsetbits32 to not need to cast the
uintptr_t address to void * in the function call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic29bf04866a7e1d5c831422f31803a724a41069b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In follow up to commit 0452d0939e7d ("soc/amd: Factor out gpp_clk_setup function") use gpp_clk_setup_common for glinda as well.
Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80699
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings glinda in line with cezanne, mendocino,
phoenix and picasso. This also prepares glinda to use the common
function gpp_clk_setup_common.
Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
BUG=b:301854636
TEST=/sys/devices/system/cpu/cpuidle/
low_power_idle_system_residency_us" will show system idle residency time
Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add FSP header files for Twin Lake. Currently these are just a copy of
ADL-N headers.
BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I37579335c784866ebbf978e28936abf046a85b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Since the ACPI code is looking for VtdBars, that only appear on
Vtd devices, search for the Vtd device in devicetree.
With the previous commit the VtdBar is now exposed as a resource
on the Vtd device and thus can easily be accessed and used.
Drop the FSP HOB parsing and just use coreboot native functions.
Allows the code to work with multiple PCI segment groups.
Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Provide a helper function to locate PCI devices on a given socket
by their PCI vendor and device IDs and functions to return
information about the current device, like the corresponding stack
and socket.
In addition add functions to return "location" information, like stack
and socket affiliation.
This becomes handy when locating devices and generating ACPI code.
Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Read the VtdBar and add it to the resources of the host bridge PCI
device. The BAR is already marked as PciResourceMem32 in the parent
PCI domain.
This allows easy probing for VTD devices with enabled VtdBars in the
next commit, without the need to look up the stack HOB.
Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I773fb39801f180fead584942dfb385fcde9d2680
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: ron minnich <rminnich@gmail.com>
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If a downstream LPC device (eg, SIO function) is disabled, we shouldn't
attempt to open PMIO windows for it, as those functions often have
unset IO bases (which default to 0), resulting in false errors like:
[ERROR] LPC IO decode base 0!
TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors
in cbmem log for disabled SIO functions.
Change-Id: I92c79fc01be21466976f3056242f6d1824878eab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The get_gpio function in this file is both unused and it shouldn't use
a signed int to pass in the MMIO base address and offset.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b08bad040ad175b37175ef21d0a0a29525c4478
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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It's been several years already since we announced the deprecation of
the legacy CBFS API for payloads. It's time to remove it completely.
Change-Id: I0ed157ac2d1376b8dff4537af9a63731064b45f6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80650
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Early EC Sync does not need to be enabled in coreboot as EFS2 is being
enabled in the EC.
BUG=b:326152804
BRANCH=None
TEST=emerge-brox coreboot
To be tested with EC sync enabled
Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As there are multiple Vtd devices, print the path of each when reporting
resource registers.
Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80549
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.
Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.
The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR 1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR 1 MiB
- VTD_BAR_CSR 4 KiB
Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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IOAT logics are optimized out for non-IOAT platforms where
CONFIG(HAVE_IOAT_DOMAINS) as false.
This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead
of is_ioat_iio_stack_res() check in the corresponding if
statement to fulfill the optimization outs.
TEST=intel/archercity CRB
Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ADL-M is not commercially available, so it can be removed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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These boards are not commerically available so can be removed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
If it's mismatched, the TBT port will time out.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot built FW image correctly.
Change-Id: I8db065e25e21406f1966d8020a3b926b3a62ae12
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
H58G56AK6BX069 2 (0010)
H9JCNNNBK3MLYR-N6E 3 (0011)
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
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The cmocka problem of sanitizing XML strings has been fixed in CB:80382.
Therefore the helper macros UX_LOCALES_GET_TEXT_FOUND_TEST() and
UX_LOCALES_GET_TEXT_NOT_FOUND_TEST() can be merged into one.
TEST=make unit-tests JUNIT_OUTPUT=y -j
Change-Id: Ic3199e2a061550282fb08122943994c835845543
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
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The Rotation Matrix allows the specification of a 3x3 matrix
representing the orientation of devices, such as accelerometers.
Each value in the matrix can be one of -1, 0, or 1, indicating the
transformation applied to the device's axes.
It is expected by Linux and required for the OS to interpret
the data from the device correctly. It is used by various drivers,
mainly in `iio/accel`.
It was tested on Ubuntu, by rotating the device and verifying the
orientation was correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80179
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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1) Initial commit for upstreaming Birmanplus mainboard changes.
2) Add the DXIO descriptors for Birmanplus mainboard.
Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Updating from commit id 507ef01:
2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP)
to commit id dd98487:
2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path)
This brings in 6 new commits:
dd98487 Fix EagleStreamFspBinPkg Path
fcf623b Fix MAX_VMD_STACKS_PER_SOCKET
e07f875 Fix EagleStream BSF File
85f37ab Idaville FSP - New UPDs for SSC
98e497f IoT RPL-P MR1 (4445_03) FSP
fc5e3c9 IoT RPL-P MR1 (4445_03) FSP
Change-Id: If7d852e1a92d8409a5161797c0aa3a55a71c8b49
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This adds an optimization to lzma decode to also read from the boot
medium in chunks of 8 bytes if that is the general purpose register
length instead of always 4 bytes. It depends on the cache / memory / spi
controller whether this is faster, but it's likely to be either the same
or faster.
TESTED
- google/vilboz: cached boot medium
64bit before - 32bit - 64bit after
load FSP-M: 35,674 - 35,595 - 34,690
load ramstage: 42,134 - 43,378 - 40,882
load FSP-S: 24,954 - 25,496 - 24,368
- foxconn/g41m: uncached boot medium for testing
64bit before - 32bit - 64bit after
load ramstage: 51,164 - 51,872 - 51,894
Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The base for this region is a magic number and none for the fields are
used, which likely means this was simply copied from a different
firmware.
Change-Id: I217bbd0b098cd15ef296854cc6262d651f11d10e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73183
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support memory parts for Xol.
- Samsung K3KL6L60GM-MGCT
- Samsung K3KL8L80CM-MGCT
BUG=b:319506033
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Proto board can boot to ChromeOS.
Change-Id: Ic6a36e40f0f93109f296c5cc67a368ace81bd217
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Update memory configuration following proto schematics.
BUG=b:319506033
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Proto board can boot to ChromeOS.
Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update initial DTT policy and TCC setting for Xol. The setting values
are from internal power team.
- Critical CPU temparature: 105 -> 99
- TCC offset: 90 -> 94
BUG=b:323989520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80410
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Set tdp_pl1_override to 15 for performance required by the thermal team.
Fix policies.critical index from 2 to 0.
BUG=b:313833488
TEST=emerge-nissa coreboot
Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e90580 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
This mirrors an identical commit for google/brya: 1ce0f3aab72d
("mb/google/brya: Fix S0i3 regression")
TEST=Boot Linux on google/drobit, verify S0i3 counter incrementing after
exiting S0ix suspend states.
Change-Id: I644e42388c0f6127512bf52e774b79721601ecc9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80612
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the glassway variant of the nivviks reference board by copying
the template files to a new directory named for the variant.
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=None
Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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New patches:
8be3737 cmocka: Fix assert_memory_equal() display
fb38de9 cmake: disable `-Wdeclaration-after-statement`
a74d9cd Sanitize XML strings.
4e92198 Improve c_strreplace implementation
ea6ab8b cmake: Set CMOCKA_LIBRARIES in package config for backwards compatibility
53de473 cmocka: Add overflow check for test_calloc()
e738d6e tests: Add test for test_calloc()
a01cc69 Bump version to 1.1.7
123f00e cpack: Update ignore files for source package generation
f1e1615 Bump version 1.1.6
35dd06e tests: The exception handler doesn't work on Windows
9d72cf9 tests: Raise segmantation fault
2b20a4d tests: Rename exceptions tests array
4cd1fda tests: Better match for test_exception_handler
8ad2c4e cmake: Fix path relocation in pkgconfig file for mingw
3137fa5 cmake: Do not use CMAKE_(BINARY|SOURCE)_DIR for compile_commands.json
6e9d32f Improve INSTALL.md
c4da7e1 doc: Link to the examples for mocking
b13f29b include: Update copyright year info
98c451d include: Define strtok_r with Visual Studio
4aae816 gitlab-ci: Move memory and ub sanitizer to analysis stage
559381b gitlab-ci: Move freebsd to test stage
ce43813 examples: Add missing compile and link options
5ead982 gitlab-ci: Introduce stages
5f366b6 gitlab-ci: Fix typo in fedora/mingw32 build
77476f7 gitlab-ci: Use gitlab windows runners
200393b gitlab-ci: Reformat yaml
406591a tests: Initialize 'struct stat' in test_assert_macros.c
b201da5 cmake: Fix path where to find cmocka.dll
a47b3da include: Improved call ordering documentation
61b1fb9 doc: Remove redundant words
2cc8cba Fix issue with fail_msg
TEST=make unit-tests
TEST=make unit-tests JUNIT_OUTPUT=y
TEST=(cd payloads/libpayload; make unit-tests)
TEST=(cd payloads/libpayload; make unit-tests JUNIT_OUTPUT=y)
Change-Id: I60b37021e2587cc32c755719ef40a650a1c14b59
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80382
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5967cebad3ad52b5cbc7babc0c808039d7da5227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80635
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable DPTF functionality for brox board
BRANCH=None
BUG=b:324360936
TEST=Built and tested on brox board
Change-Id: I0315f7f45688ccc36d321d6be4fa4fac7559a16b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
This patch moves their definition from FSP header to Xeon-SP layer
ACPI header.
TEST=intel/archercity CRB
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED
and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common
codes.
TEST=intel/archercity CRB
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
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IOAT is the term for the on-chip accelerator technology of
Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack.
Different SoC has different check criteria for IOAT stacks,
this patch introduces an util function to abstract these differences
as well as cleaning up the usage of names.
TEST=intel/archercity CRB
Change-Id: I376928ad89b68b294734000678dad6f070d3c97d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80578
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No devicetree uses these anymore.
Change-Id: Ia65a0a56a6668a13761bad35f6a44ed8f6a35a78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72600
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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These will be updated and finalized after the release to capture any
final changes, remove "upcoming release", and finalize all stats.
Change-Id: Idc224c43f2459faabf91a9ef282bb9eaeba42240
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80617
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.
Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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It's not needed other than for booting w/SeaBIOS, where it is already
selected by default, and enabling it with edk2 payload prevents Linux/
Windows from fully entering S0ix.
TEST=build/boot purism/librem_cnl (Mini v2), verify Win11/Linux able
to enter and exit S0ix properly.
Change-Id: I974a82bedc4e06f48ce801f2bc0c29afbd80ffcf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80602
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The tcss.asl doesn't just relate to tcss, it is required for core
scheduling, so include it for all platforms.
Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This patch adds ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Probe usb ports by FW_CONFIG setting to disable C1 port on
beadrix poin2 new daughterboard without C1 port.
BUG=b:316365055
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot
Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add beadrix supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. CXMT CXDB4CBAM-ML-A
BUG=b:321830738
TEST=Use part_id_gen to generate related settings
Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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SELF has the fields wired up for 64bit, but adding flat images cuts the
upper half.
Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. romstage.S should only be included if we have a separate romstage
2. FW_JUMP and FW_DYNAMIC are opposing options and we only support
FW_DYNAMIC
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79952
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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currently the HiFive Unmatched mainboard produces the following error:
```
util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a
(_clzsi2.o): in function `__clzdi2':
util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation
truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in
.rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/
rv64imafdc/lp64d/libgcc.a(_clz.o)
```
This is due to the fact that the libgcc.a library is compiled with the
medlow code model but the mainboards are compiled with the medany code
model.
Changing the code model of the GCC libraries to the medany code model
fixes the issue.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only call fill_pds() once to prevent leaking memory. Previously it was
called for every active stack on every socket.
Only call dump_pds() once to prevent spamming the console with the same
information.
Drop the return value since it's always returning success.
Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The struct map_entry has two zero'd entries due to the ifdef
being used. Do not read those entries and do not print those
entries.
Fixes a NULL string being printed along as the vendor and device
ID of the PCI device.
Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866
"[PATCH] Increase number of e820 entries hard limit from 32 to 128"
made in 2005 the number of e820 entries passed from the bootloader
is 128. Use the boot protocol version to check for support of
128 entries and use them if necessary.
Tested on IBM/SBP1:
Fixes booting a Linux payload when more than 32 entries are present
in the memory table, which can easily happen on a 4 socket platform.
Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Now that the baseboard uses chipset devicetree references, remove
all references whose value is identical to the chipset devicetree
default or the baseboard default, since they are pointless clutter.
TEST=build/boot purism/librem_cnl (Mini v2), verify output of lspci
and lsusb unchanged before and after patch.
Change-Id: I12498e7261dafd7ee59fe79926532399392d1b09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80600
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the board uses chipset devicetree references, remove all
references whose value is identical to the chipset devicetree default,
since they are pointless clutter.
TEST=build/boot purism/librem_cnl (Mini v2), run lspci and verify output
unchanged before and after patch.
Change-Id: I6c656d227962548cebde61f1d82333837adbbf56
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80599
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.
This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).
1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates.
ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.
BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.
Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.
Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's already selected at the SoC level, so selecting at the board
level is redundant.
Change-Id: Ifbe7f88858b9e5e8e5185dbff5853186fd3c66cb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80557
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add an ACPI stub containing the TCPU device in proper scope, along with
the device status, on boards not using the DPTF driver, so that there
exists an ACPI device to be referenced from the PEPD LPI constraint
list.
Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for
_SB.PCI0.TCPU on boards with the SA thermal device enabled but which do
not use the Intel DPTF driver.
TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2).
Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is now generated by acpigen in the common/block/sata module.
Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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acpi_device_path() includes the device name, so we end up with:
Scope (\_SB.PCI0.SATA) {
Device (SATA) {
...
Fix this by using acpi_device_scope() instead.
TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify
SATA device scope correct.
Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: Ib100a677935cf3309a380952c35e9060e64433cb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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