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* Intel HD Graphics 510
* Intel HD Graphics 515
* Intel HD Graphics 520
* Intel HD Graphics 530 (2x)
* Intel UHD Graphics 615 (2x)
* Intel UHD Graphics 617
* Intel UHD Graphics 620 (3x)
* Intel UHD Graphics 630 (7x)
* Intel UHD Graphics 640
* Intel Iris Graphics 540
* Intel Iris Graphics 550
* Intel Iris Pro Graphics 580
* Intel Iris Plus Graphics 650
* Intel Iris Plus Graphics 655
Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30610
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on not publicly available IT8613E Preliminary Specification V0.3.
Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change adds support for the SuperIO chip IT8613E. This chip uses
FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so
it relies on support in common ITE code. LDNs were taken from IT8613E
Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This is a great check, but unfortunately it's currently not effective
because most uses of IS_ENABLED() do not have whitespace in front of
them (they're mostly used as part of an if (IS_ENABLED(...)) condition).
This patch makes the linter a little more generous in what it considers
in scope to avoid these false negatives in the future.
Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX).
This patch can fix that. However, I don't have (and don't plan to
acquire) an affected system to test, so approve at your own risk (or
let me know if I should just remove that check instead).
Change-Id: I79a0fca65853798ee45c3779b437864ba3cf2b1e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX).
This patch fixes the issue. Not tested on a real board, but looking at
the affected code paths suggests that this will result in no effective
change anywhere (since CAR should already be torn down by the time this
is called on FSP1.0 boards, so do_car_migrate_variables() would have
immediately exited anyway).
Change-Id: I74e0ed4d04471ee521ff5c69a74a6f4c949e5847
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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When updating firmware, it is very often that we may want to preserve
few sections, for example vital product data (VPD) including serial
number, calibration data and cache. A firmware updater has to hard-code
the section names that need to be preserved and is hard to maintain.
A better approach is to specify that in FMAP area flags (the `area_flag`
field) using FMAP_AREA_PRESERVE. With this patchset, a FMD parser flag
"PRESERVE" is introduced and will be converted to FMAP_AREA_PRESERVE
when generating FMAP data (by fmap_from_fmd.c).
For example, The FMD statement:
RO_VPD(PRESERVE)@0x0 16k
will generate an FMAP firmware section that:
area_name = "RO_VPD"
area_offset = 0
area_size = 16384
area_flags = FMAP_AREA_PRESERVE
BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
Manually added 'PRESERVE' to some FMD files, and verify (by running
fmap.py) the output coreboot.rom has FMAP_AREA_PRESERVE set
Change-Id: I51e7d31029b98868a1cab0d26bf04a14db01b1c0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The recent toolchain update also updated binutils, which has a new
relocation type, introduced with commit bd7ab16b
(x86-64: Generate branch with PLT32 relocation).
Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32.
Add comment explaining the situation.
Fixes build error on x86_64.
Change-Id: I81350d2728c20ac72cc865e7ba92319858352632
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Qemu does not have a real CAR but postcar stage is still useful
for testing the stage.
The postcar stage is also mandatory for x86_64 to setup
pagetables for x86_64 ramstage.
Do not set up MTRRs, as qemu ignores them anyways.
Tested on qemu-i440fx and qemu-q35.
Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The idea of "annotation" for firmware sections was pretty flexible, but
in future we will want multiple attributes applied to same area. For
example, indicate the section must be preserved when updating firmware
so serial number or MAC address can be preserved.
The solution here is to extend annotation so it can take multiple
identifiers (flags) in a row. For example, to declare a 64KB COREBOOT
section as CBFS using annotation:
COREBOOT(CBFS)@0x0 64k
If there's a new flag "PRESERVE" indicating the section must be
preserved before update, we can declare it following CBFS flag:
COREBOOT(CBFS PRESERVE)@0x0 64k
The flags are directly parsed in fmd_parser, and stored in an union
flashmap_flags. Output modules can choose to ignore or process the
flags.
Currently the only supported flag is "CBFS" (for backward compatible
with annotation). There will be more new flags in follow up patches.
BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
Change-Id: Ie2d99f570e6faff6ed3a4344d6af7526a4515fae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31706
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These files suffer from .c includes.
Change-Id: Id836595290922fcbd108a5ed576fc640b2530711
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31696
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibaa5428df1832d3f18946d456fb0b6d2fff65c32
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31694
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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git diff needed to emit diffs without prefix (e.g. a/ and b/) for
clang-format-diff to be able to work.
Also require that the test succeeds, but note that it only runs on
trees whitelisted in $(top)/.clang-format-scope.
Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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80 chars + 2 tabs was the compromise we got to in the last round of
discussion.
Change-Id: I9293a69d1bea900da36501cde512004d0695ad37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Intel Braswell SoC contains SMBus controller but no support
is available for this controller.
This controller is compatible with the Intel SMBus support in the
southbridge common directory.
To be able using smbus support from the Intel common directory
the smbus.c is moved outside SOUTHBRIDGE_INTEL_COMMON
dependency block.
Use SOUTHBRIDGE_INTEL_COMMON_SMBUS to include support.
BUG=N/A
TEST= Facebook FBG-1710 LCD panel
Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.
Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.
Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)
Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#).
BUG=b:123342945
TEST=Verified BT function on Arcada DVT1 system
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I260a2312d47385da3c7ec215267ff63ada04f2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add 6GB dual-channel memory configuration for future use.
BUG=b:124634885
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I36d6c704ac6708b29cc570a2209eeb32de6148b3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31460
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie32f1d43168c277be46cdbd7fbfa2445d9899689
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31699
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31698
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function (preprocessor macro) we need is defined
in <endian.h> not <swab.h>.
Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Provide clean separation for PCI and PNP headers,
followup will also move PNP outside <arch/io.h>.
Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These resolved to <device/oprom/include/io.h> which
included <arch/io.h> that we really wanted.
Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31693
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the support for providing a MAC address for a dock to use based on
the VPD values set in the platform.
BUG=b:123925776
TEST=tested on sarien by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "ethernet_mac0"="AA:AA:AA:AA:AA:AA"
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
1) Test with no policy set, returns "dock_mac"
ACPI Debug: "VPD region RW did not verify"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
2) Test with policy set to "builtin", returns nothing
> vpd -i RW_VPD -s "dock_passthru"="builtin"
ACPI Debug: "Found VPD KEY dock_passthru = builtin" [AMAC returns Zero]
3) Test with policy set to "ethernet_mac0"
> vpd -i RW_VPD -s "dock_passthru"="ethernet_mac0"
ACPI Debug: "Found VPD KEY dock_passthru = ethernet_mac0"
ACPI Debug: "Found VPD KEY ethernet_mac0 = AA:AA:AA:AA:AA:AA"
ACPI Debug: "MAC address returned from VPD: AA:AA:AA:AA:AA:AA"
ACPI Debug: "AMAC = _AUXMAC_#AAAAAAAAAAAA#"
4) Test with policy set to "dock_mac"
> vpd -i RW_VPD -s "dock_passthru"="dock_mac"
ACPI Debug: "Found VPD KEY dock_passthru = dock_mac"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This change adds support for providing a MAC address that can be used
by the OS network drivers to change the MAC address that a NIC uses.
The Realtek r8152 driver in the Linux kernel supports a MAC address
passthru feature which can result in the dock ethernet port using the
same MAC address that is assigned to the internal NIC. This is done
by calling an ACPI method at \_SB.AMAC() which returns a formatted
string containing the MAC address for the dock to use.
The Linux kernel implementation can be found at
drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read()
This is implemented specifically for Chrome OS as it relies on VPD
to determine the MAC address to supply.
The policy which controls where the dock MAC address comes from is
written into RW_VPD property "dock_passthru":
"dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac"
"ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0"
"builtin": existing dock MAC address (return nothing)
The MAC address in VPD is the standard format AA:BB:CC:DD:EE:FF and
it must be converted into the string format expected by the OS which
involves some string manipulation which ACPI is not great at handling.
BUG=b:123925776
TEST=this was tested on a sarien board by setting the VPD keys to
their expected values and observing if the AMAC() method returns the
expected string.
Change-Id: I3335e5d924155431e299844e2aaace62168294e0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This ACPI device presents an interface that allows other ACPI devices
or methods to read VPD strings. The VPDF() method is provided the
VPD partition to look in, and the name of the VPD key to find and it
will return the VPD string if it exists.
For example: VPD.VPDF ("RO", "serial_number")
BUG=b:123925776
TEST=this was tested on a sarien platform by adding ACPI code that
searches for a VPD key and returns the value it finds, and then setting
that VPD string from the OS with the Chrome OS 'vpd' utility to ensure
the ACPI method returns the correct value.
Change-Id: I4668f66d7f7f364ac8c3b064d406b24135abb0f6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Store the memory address of VPD region start and length for the memory
mapped RO_VPD and RW_VPD into GNVS so they can be used by ACPI code.
BUG=b:123925776
TEST=boot on sarien and verify VPD start/length in GNVS
Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Move common definitions for PCH H and LP to a common header.
Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31621
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the ISH ACPI device so we can hang fields off of a _DSD table.
Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.
BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.
Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following remarks show up during cannonlake based platform coreboot
build:
dsdt.asl 55: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 136: Offset (0xa8),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Address those two remarks in coreboot.
BUG=N/A
TEST=Build coreboot and check build log to see no more remark.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Reviewed-on: https://review.coreboot.org/c/31666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Using ACPICA version 20180927 or greater, IASL detects Unnecessary/redundant
uses of the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset".
Offsets refer to the current offset are unnecessary.
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
Change-Id: Ie1f2a2ace335af7984209c9e286b9f85e5342a7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31671
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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using '--single-branch' when cloning the tianocore repo
prevents the use of other branches/commits outside of the
checked-out coreboot_fb branch, so remove it.
Test: build with TIANOCORE_REVISION selected and revision
set to origin/master, verify checkout succeeds
Change-Id: If8c93aa87957ba2ff9ab7a58e84d2a25b48ec346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.
To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.
BUG=chromium:936768
TEST=make; boots an x86 image.
Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 5e90ef8c356099e42612bc97976c67092d0810ff.
Reason for revert: The 1s interval causes early throttle in usage spike. (log in b/123895423#comment3)
BUG=b:113101335
BRANCH=None
TEST=learning from Nocturne
Change-Id: Id6467b51eb937b89b4c08641f36266544c8fa176
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Local APIC was not configured.
Add setup_lapic() to configure the APIC.
BUG=N/A
TEST= Ubuntu 4.15.0 reports correct local APIC information
on Intel CherryHill CRB
Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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HDA support did not configure the codecs correclty.
Use Intel common block support to configure the codecs.
To use common Intel HDA support file hda.c file has been
removed and Braswell HDA device ID is added to list of
supported PCI devices in intel/common/block/hda/hda.c.
CONFIG_SOC_INTEL_COMMON_BLOCK and
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled
to include hda.c in build.
When codec table is available at board level
SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled
and a codec table must be supplied.
BUG=N/A
TEST=Facebook FBG-1701 ALC298 configuration
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix regression after commit
c38d543 sb/intel/common: SMBus complete_command()
When evaluating HSTSTS register, BYTE_DONE bit must
be excluded from transaction completion and error criteria.
Change-Id: I49cc43d1fa58250988cc41b2ca747b9f1d7586d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocations for PC relative instructions must not emitted.
As PC64 are unlikely with current code, it never was an issue.
Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use a single group for all CONFIG_PCI=y sources.
Change-Id: I426f4398c01dfbf03b9dd2db8c7a964512c86d5e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A default is a build-time static value, fallback. Return
value does not depend of input parameter.
Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31679
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop the bus parameter, we do not use it.
It would still be possible to do per-bus selection
by evaluating the bus number, but currently we do
not have need for that either.
Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Having different signatures for the PCI config accessors
prevents them from having the same name in different
stages.
For now, work around this using __SIMPLE_DEVICE__.
Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch makes the way to protect flash regions selectable. If you
don't want to use ifdtool for modification of flash descriptor, enable
the new option. Otherwise, the previous config settings for all
mainboards will be retained.
Change-Id: I46ec6339008edcc78fe76682eed5714f85354937
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As we are running ACPI v3.0, references to older
than v3.0 are removed.
Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Applying microcode updates a second time seems to be only necessary
on newer platforms (Nehalem+) for "uncore" updates.
Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Masanori Ogino <masanori.ogino@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We load it once for the BSP in advance and let the MP init handle it for
the APs. The BSP load could also be done earlier, e.g. before CAR setup,
to align with other platforms.
TEST=Booted ThinkPad X200s and checked log: Microcode is loaded
correctly on the BSP before SMM setup, and reported to be up
to date on all cores after.
Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Some ITEs have more than 3 independent FAN controller outputs. As the
initial implementation assumed only 3 outputs some registers are not
consequently numbered. This change adds macros for accessing those
registers.
Additionally some chips have SmartGuardian always enabled, without the
option for turning it off. For these chips bits that were responsible
for ON/OFF control are either reserved or have different meaning.
Another Kconfig option is added to disable ON/OFF functionality on
platforms that do not support it.
Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/31616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There was CONFIG_ prefix missing in SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
option, this patch fixes it.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I52919671569175141560cb73e42344aa1725c112
Reviewed-on: https://review.coreboot.org/c/31674
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to prevent keyboard keys pressed at boot from causing issues
in the payload remove the PS2 keyboard driver so it does not get
initialized until it is needed in libpayload.
This was enabled initially because the keyboard controller on this
platform does not come up in translated mode, so unless coreboot
called keyboard_init() the keyboard would never work properly in the
kernel because it would come up as an "AT Raw" device instead of an
"AT Translated" device.
Instead of initializing the keyboard in coreboot a workaround is
added to the payload to put the keyboard into translated mode.
BUG=b:126633269
TEST=boot on sarien while pressing keys and ensure libpayload and/or
the kernel does not have any issues initializing the keyboard.
Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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If a PS/2 AUX device is not present then the AUX test command
during i8042_probe() will time out and add ~500ms to the boot time.
In order to avoid this only test the PS/2 AUX port if
CONFIG_LP_PC_MOUSE is enabled.
BUG=b:126633269
TEST=boot on device without AUX port and check that this command
does not get executed, saving ~500ms at boot.
Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If keys are pressed at boot some keyboard controllers will not
properly respond with an ACK to commands, which results in the
keyboard_init function aborting before it adds the keyboard to the
input device list.
This same keyboard controller will manage to properly return keyboard
data when keys are pressed later, so it is possible for it to be
functional in the payload even if it does not respond properly to
every command during initialization.
In order to allow payloads to use the keyboard when this happens a
new Kconfig option is added to ignore the keyboard ACK response and
always add the keyboard to the input device list. This option is
disabled by default and must be enabled by the specific boards that
need it.
BUG=b:126633269
TEST=boot on device with this controller and press keys during boot
and see that the keyboard is still functional in the payload.
Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add Kconfig options to use custom bootsplash file,
dependent on using MrChromebox's stable branch, with
help info conveying required file format.
Adjust Makefile to copy the custom bootsplash and
overwrite the default Logo.bmp file, handling both
absolute and relative paths, and restore the original
logo file after building so as to keep the working
directory clean.
Test: build with and without custom bootsplash, ensure
correct bootsplash displayed
Change-Id: I164f46777169801cff56633fd920bc81b7c8129a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds few more required EFI return status into FSP2.0
drivers so that coreboot code can make use of those.
Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This mainboard has a TPM located on the LPC bus. Enable the driver for
it so that it is initialized and the ACPI table entry is generated.
Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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On Sarien, change pin config of 0x19 (headset mic) and
0x21(headset headphone) to change jack location so that naming does
not use "Front" in the name."Front Headphone" --> "Headphone" so it
matches naming on Arcada.
BUG=b:126334749
TEST= verify with 'evtest' command that jack name is
"HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone"
Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61
Signed-off-by: Joyce Toh <joyce.toh@intel.com>
Reviewed-on: https://review.coreboot.org/c/31624
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The fdt in the maskrom cannot be used to start linux. The correct fdt
is dumped by replacing the bbl of the original firmware and used in
coreboot.
Correct the mac address in fdt by reading otp
Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/31047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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Calculation of memory reserved by FSP is incorrect.
Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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This patch adds SOC_INTEL_COMETLAKE Kconfig option.
Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Preliminary dptf change for Atlas
- Throttle charger using all temp sensors (not just ambient)
- Throttle charger with higher priority than CPU
- Update throttle temperature using data from surface thermistor
in thermal chamber test
BUG=b:113101335
BRANCH=None
TEST=based on preliminary data from thermal chamber test
Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
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Use 7w PL1 with DPTF throttle to enable better performance for atlas.
BUG=b:113101335
BRANCH=None
TEST=Recommend setting from thermal team. Build coreboot on atlas
Change-Id: Idcf44f213259634a507a013b31b410ed322e9479
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31627
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ISA dma controller is not configured.
Add call isa_dma_init().
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The level/edge mode of PIRQ is not configured and i8259 PIC not initialized.
Add calls to:
- i8259_configure_irq_trigger()
- setup_i8259()
- write_pci_config_irqs()
to correct the configuration of interrupts.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates.
These interrupt numbers are added to all LNKx.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29287
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Static scan does not know the contents of the fixed MTRR descriptor, so
it has no way to eval the result for variable num_ranges. If num_ranges
is less or equal to 0, the for loop will not be entered, and the values
of fixed_msrs will not be set. Asserting that num_ranges is greater than
0 ensures the loop enters at least once.
BUG=b:112253891
TEST=build grunt
Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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After loading compressed files in CBFS, we should check the decompressed
size is equal to the expected size. This might help us detect file
content corruption or compressor/decompressor bugs.
BUG=none
BRANCH=none
TEST=manually (we can still boot into kernel on Kukui, and verify that
loading files from CBFS still works by seeing ChromiumOS firmware
screen).
Change-Id: Ia756cc5477670dd0d1d8aa59d4160ab4233c6795
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31564
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, cbfs_decompress() calls ulzma() and ulz4f() for LZMA/LZ4
decompression. These two functions don't accept input/output size as
parameters. We can make cbfs_decompress more robust by calling ulzman()
and ulz4fn() instead. This could prevent us from overflowing destination
buffer.
BUG=none
BRANCH=none
TEST=boot into kernel on Kukui with COMPRESSED_PAYLOAD_LZMA /
COMPRESSED_PAYLOAD_LZ4.
Change-Id: Ibe617825bd000ed618791d8e3c5f65bbbd5f7e33
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Unused since the removal of `fsp_sandybridge`.
Change-Id: Iea31e341c3df680ed48db4f8734d9d0bde120be3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31646
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These marketing names are much easier to distinguish. My
mnemonic: Socket M => up to Merom, Socket P => up to Penryn.
Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31645
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These came for the Socket 479 which is not supported anymore.
Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31644
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These sneaked in and were never supported by this socket (nor expected
in the notebooks that have it).
Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.
The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.
Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Doesn't look like it could be used.
Change-Id: I8074df12d062bd15f2388b367b3698c9d3b7b5b6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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coreboot did not program all GPIOs from C0 to C7 correctly which are
SMBUS GPIO. Some of the GPIOs are left in default mode which is
native function but we need to configure as GPIO mode and provide proper
configuration as per schematic.
After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not
getting idle due to GPIO configuration and CSME was not getting power
gated due to SMBUS.
BUG=b:123702553
BRANCH=none
TEST=Check on hatch board. CSME was not getting power gated for s0ix.
After applying this patch CSME is power gated now
Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of
pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it
more aligned with the behavior on other Intel SoCs. However, as the
PMC device is hidden, it never gets enumerated and so init function
does not get called for it. This change moves the call to disable ACPI
mode to exit of BS_DEV_INIT instead.
BUG=b:126016602
TEST=Verified that:
1. pmc_set_acpi_mode is actually getting called.
2. EC panic event gets logged to eventlog correctly.
Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31633
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize RTC at ROM stage.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9d9c68755e8a6ac65dd794211e6ccf06e5057567
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch implements RTC initialization.
1. initialization dcxo
2. rtc clock using dcxo 32k
3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN
4. rtc register initialization
5. refactor the driver common part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Adding header files for FSP for cometlake platform version 1034
Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Assumed broken during review and rebase. The
SPD at address 0x52 will appear at index 1.
Change-Id: I213853d2b981294554d8d1b254da476905a41c13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix cases of using ENV_SMM where __SIMPLE_DEVICE__
should be used instead.
Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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TEST=Verify PM_STS1 value is is not 0xFF.
Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds CML-U 2+2 SA DID into systemagent.c and report
platform.
Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31638
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate pm timer emulation macros from soc
directory and makes use from common code msr.h
Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31610
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert. This
change fixes that and allows us to add asserts to protect
against other failures.
Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Instead of using 2, 0 is now used for non-CBI provisioned board or
corrupted CBI board to confrom to the sku encoding.
BUG=b:123676982
BRANCH=kukui
TEST=test with un-provisioned board to verify the sku_id.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce
Reviewed-on: https://review.coreboot.org/c/31623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For fast CBMEM console use minimum BIOS_DEBUG level.
For other consoles, Kconfig and/or nvram settings
apply.
Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Various instances of google_chromeec_command() can return non-zero number
(both positive and negative) to indicate error -- fixing cbi_get_uint32()
and cbi_get_string() so they follow the same convention.
BUG=b:123676982
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c
Reviewed-on: https://review.coreboot.org/c/31585
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function appeared previously unused (called only from rtc_display, also unused),
but it returned an incorrect weekday. Change the algorithm to use Zeller's Rule, a
well-known algorithm for calculuating weekdays.
Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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