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2020-01-03amdblocks/acpimmio: add missing MMIO functionsMichał Żygowski
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-03amdblocks/biosram: Force use of abstractionKyösti Mälkki
Hide the fundamental BIOSRAM accessors to force use of the memory space via abstraction functions. Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-03mainboard/google/puff: Clean up pcie 15.3 ep in dtEdward O'Callaghan
Clean up devicetree as nothing special is needed here. BUG=b:142769041 BRANCH=none TEST=builds Change-Id: I0790631233fdcaa6a785d2cb41e79b8f2f469d44 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-01-02lib/malloc: Implement a simple free() only for last malloc()Bora Guvendik
Implement a free() that supports only the last malloc(). Rewind the heap to the last allocation point if the ptr to be freed is matching the end of heap before last malloc(). With current situation, since free() is no-op, every call to malloc() is a memory leak. BUG=b:140124451 TEST=Wrote a test function to do malloc and free operations. Change-Id: I6d43cf54b79e6897cf6882335730b2310e4eae45 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-02intel/i82371eb: Drop unused codeKyösti Mälkki
Change-Id: I71b5e46efac718df6d4b52d27a20fe1cf6d96427 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02lib/: Drop generic_dump_spdKyösti Mälkki
Not built, relies on SMBUS for SPD and we do not have a globally defined spd_read_byte() prototype. Change-Id: Ifb9d3aa31207cb5b99f475b70f52a03aca73432b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02src/acpi: Update license headers to SPDXMartin Roth
While I was working on updating the headers to move copyrights into the AUTHORS file, I got a request to switch to SPDX headers as well. Linux has moved completely to SPDX headers, which are easier to maintain, have good definitions, are very short, and can be checked automatically. This is completely unlike our current header situation. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-02util/lint: Update license header text for SPDX headers.Martin Roth
In preparation to update to SPDX license headers, add identifiers for the licenses seen in the coreboot project and create a command line parameter allowing only SPDX license identifiers to be detected. Here are example locations of these licenses: Apache-2.0 - src/soc/sifive BSD-3-Clause - Throughout coreboot & libpayload source GPL-2.0-only - Throughout coreboot source GPL-2.0-or-later - Throughout coreboot source GPL-3.0-only - util/amdtools GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat] ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/ X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-01-02mb/**/acpi_tables.c: Drop lid settings on desktopsAngel Pons
Unlike laptops and some trash cans, desktop boards do not have a lid. Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-02MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-AMike Banon
These are the boards I have and currently working on. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I3f366105371c7d2568da6682b24cb52bce2d5467 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02amd/acpi: Drop empty PCSD device nodesNico Huber
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID), but they don't provide any information and are not referenced anywhere. Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02asus/am1i-a: remove unnecessary VGA_BIOS_ID defaultMike Banon
The majority of Socket AM1 APUs [1] - three out of five - have the integrated VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here. [1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC) Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02soc/intel/bsw/gpio.h: Drop unused valuesAngel Pons
Most of these are leftovers from the initial copy from Baytrail. Change-Id: I1c437f34902400022ac6a5e95ff6168545ca557f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-02src: Remove unneeded 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ie4293094ad703a2d8b68a8c640bd8d9cece2e6e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-02mb/ibase/mb899: Remove unused includesElyes HAOUAS
Change-Id: I496da344cc0d3845c308bca4d5da46d9ca6f88a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-02mb/*/*/acpi_tables: Remove unused includesElyes HAOUAS
Change-Id: Ie8b9df7a64b45167de542182f3dfe6b320b9f2e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02soc/qualcomm/qcs405: Remove unused QCS405_BLSP_SPIElyes HAOUAS
Change-Id: I73ff8adeb2751ed4035c60f7387576460bdd47e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-02arch/x86/Kconfig: Remove unused BOOTBLOCK_RESETSElyes HAOUAS
Change-Id: I792d271bdd2a93649bd9ca67c74b29fc5037542b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-02mb/intel/d945gclf: Remove unused includeElyes HAOUAS
Change-Id: I023ce20b4144d782f22243911f845f6e28fdb2a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-02mb/google/beltino/**/hda_verb.c: Correct pin configsAngel Pons
NIDs 0x18 and 0x19 are flipped, and the verbs for NID 0x1b are instead applied onto NID 0x1a. Fix that, so that it matches original Chromium sources for the boards. Change-Id: I20cc4b282602f8557fa4f25489adf899b7460a09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/google/beltino/**/hda_verb.c: remove preprocessor guardsAngel Pons
These files are not headers. Change-Id: Ibe6c9a96c1c4b0952a8d03b7a8b17869a66511f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/**/hda_verb.c: Correct codec ID on subvendor verbsAngel Pons
Looks like the subvendor verb for codec #3 is erroneously using zero as its codec number. Fix that. Change-Id: I760533c229287627dd0548a06300c376e045302c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/**/hda_verb.{c,h}: use denary numerals for codec IDsAngel Pons
Denary, also known as "decimal" or "base 10," is the standard number system used around the world. Therefore, make use of it. Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-01-02mb/ti/beaglebone: Remove unused includesElyes HAOUAS
Change-Id: Ifd1096cdf3700fa24ad8e5a701f48803650767bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-02drivers/pc80/mc146818rtc: Remove read_option_lowlevel()Kyösti Mälkki
This was a workaround for romcc. Change-Id: I34f41390afbd88f3ace7003fd18c2edd56712a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37954 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02Replace last uses of read_option() with get_option()Kyösti Mälkki
Change-Id: I63e80953195a6c524392da42b268efe3012ed41b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37953 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02src/include: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I9e5d18739e7c5b5c742a905ac482529c7e0866df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37827 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02mb/intel/jasperlake_rvp: Add initial mainboard codeAamir Bohra
This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Jasperlake". 2. Replace "icelake_rvp" with "jasperlake_rvp". 3. Rename "icl" with "jsl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake" as tigerlake SOC hosts jasperlake code as well. 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC 10. Replace icl_u and icl_y variant with jslrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per jasperlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 10MB BIOS region. TEST=Build jasperlake rvp board Change-Id: I3314215807959b7348b71933fbba98e6487c0632 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-01-02mainboard/google/puff: Enable net driver on pcie epEdward O'Callaghan
Let coreboot know there is a NIC device on the end so that the mac from vpd is set at early boot. Properly configure the link-leds in devicetree s.t. valid values are written out to the register at initialization. BUG=b:146592075,146999042,146999043 BRANCH=none TEST=Boot to kernel. Insert mac address into VPD vpd -s ethernet_mac=<address> reboot the system. Ensure we have ip address and corresponding mac address with ifconfig. Ensure ethernet controller shows up with lspci. Change-Id: I76ce6d8a5a26842fcb2544ee96567fe0da8603b1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-01-01nb/intel/sandybridge: replace .val_4028 with .io_latencyFelix Held
Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38027 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-01nb/intel/sandybridge/sandybridge.h: Do cosmetic fixesAngel Pons
Change-Id: I212f58bdaee538ad8f0197c0aec742aace1c7921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: Use the MC_BIOS_DATA defineAngel Pons
Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: Make `PM_PDWN_Config` uppercaseAngel Pons
Change-Id: Id37d2367d57ff925476c53bb0edab927c1c768f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01nb/intel/sandybridge: add and use memory thermal configuration registersFelix Held
Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: add and use ME stolen memory and lock bit definesFelix Held
Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BARFelix Held
Change-Id: Ie5a28ceb3d1b684b9c94dcae5b303a4dce75f273 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: add and use more MCHBAR register definesFelix Held
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.hFelix Held
Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01nb/intel/sandybridge: use MESEG register names from datasheetFelix Held
I used register names guessed on what the registers do, since the SNB documentation marked those registers as reserved; the IVB documentation (326765-005) has names for the registers, so I'll use those. Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31mb/**/acpi: Remove unused filesAngel Pons
Remove commented-out entries in dsdt.asl, and then remove files that do not get built. Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31device: Log times with millisecond resolutionKyösti Mälkki
To print times with 1 us resolution just adds unnecessary noise when comparing logs across different boots. Furthermore, just the printk itself is 1 ms if some slow console is enabled. Change-Id: Ibea43124a1937f404a6e71fd9431086b2b72290a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31console,boot_state: Reformat state times outputKyösti Mälkki
For each boot_state, report the times spent interleaved with other console output and remove the samples arrays. The time spent to report the times to console is not accounted for. Change-Id: I0c847da98901c56b356b4a933d9ae865dada98b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31nb/amd: Fix typoElyes HAOUAS
Change-Id: I7d27981dd7af53f0e8484d267a9a40fd3d269212 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31src/{soc,southbridge}/amd: Fix typoElyes HAOUAS
Change-Id: I7e3dc64648af05d51a319019397f24ba74c25c37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31sb/amd/cimx/sb800/cfg.c: Fix typoElyes HAOUAS
Change-Id: I46653d9530a136a56b762858de2bae2c7cbfd461 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31src: Remove some romcc workaroundsJacob Garber
Now that romcc is gone, move cmos_post_init() into post.c, and remove some preprocessor workarounds. Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-31mb/*/*/acpi_tables: Don't initialize already initialized fieldsPeter Lemenkov
Don't initialize fields with zeroes since gnvs structs were zeroed out in southbridge already. See * src/southbridge/intel/*/lpc.c Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31mb/*/*/acpi_tables: Don't zero out gnvs againPeter Lemenkov
The gnvs structure was zeroed out before calling acpi_create_gnvs(...) in the following files: * src/southbridge/intel/*/lpc.c Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31mb/hp: Add data.vbt files for folio_9470m and revolve_810_g1Bill XIE
Extracted from live running machines running vendor firmware. Change-Id: I5082af9349c25a5f1759ba00b3fbf8d18f8fde4d Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31ec/hp/kbc1126: Make firmware offsets user configurableBill XIE
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system starts to produce larger bootblock, conflicting with former default offsets. This change makes these offsets configurable before building, with default values lower than before, to better fit the larger bootblock. Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31mb/google/atlas: Add libgfxinit supportMatt DeVillier
Add Kconfig, panel delays extracted from VBT (and confirmed by Linux) Test: build/boot Atlas with libgfxinit and Tianocore payload Change-Id: I94c227cd4f020db719bf81118d983493752bb00f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31mb/google/peppy: Add Hynix memory HMT425S6CFR6A supportMatt DeVillier
Adapted from Chromium commit b8dcb1a [Peppy: Update Memory IDs] Add Hynix memory HMT425S6CFR6A support. RAM_ID: 011 4GB Hynix HMT425S6CFR6A RAM_ID: 111 2GB Hynix HMT425S6CFR6A Original-Change-Id: I26d5c4ad00509e7823c325ee8391e0b18fee44d8 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1074849 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4d165f61b8a13e5ed025e9ddbc4330db88e2fa3d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31mb/google/peppy: add _DSD to touchscreen ACPIMatt DeVillier
Recent changes to the Atmel touchscreen driver in the mainline kernel broke functionality with devices running upstream coreboot, due relying on another driver (chromeos_laptop) which makes the assumption that the i2c devices are be in PCI mode (as with the stock Google firmware) rather than in ACPI mode as they are in upstream coreboot. Mitigate this by adding the required devicetree property so the Atmel toushcreen driver will correctly attach without the use of chromeos_laptop. Test: build/boot peppy on 4.18+ kernel, verify touchscreen working Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolò Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADTMeera Ravindranath
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT). Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments. Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-31mb/google/hatch/akemi: modify DPTF parameters for new FANPeichao Wang
New FAN use NTN bearing, so tune DPTF parameters to satisfy requirement BUG=b:144370669 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6fbf0c80cd2421ce9a489c8923a97d860a11b545 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-31sb/i82801gx/nvs: Add missing <stdint.h>Elyes HAOUAS
Change-Id: I22b3fb31d8694c76b4a6fdfa40a72977e9099815 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37899 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31northbridge: Add missing include <device/pci_def.h>Elyes HAOUAS
Change-Id: Ib63835d2407bbabbd78b43927f7fbd407ca06a08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37841 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-30sb/amd/cimx/sb800: Remove unused BOOTBLOCK_SOUTHBRIDGE_INITElyes HAOUAS
Change-Id: Ie0dc165076644e225064568b4cb6f73b2af66438 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-30ibase/mb899: use common winbond/nuvoton HWM bank select functionFelix Held
Change-Id: I7f159074c25a0fdfe2ee15024c1ed6c062ce75d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-30kontron/986lcd-m: use common winbond/nuvoton HWM bank select functionFelix Held
Change-Id: I169b16c99a864ecff54112bcc073f2c141c2009f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-30superio/nuvoton: add common HWM bank select functionFelix Held
Change-Id: I828b6caa37e52c13e1876c7ca4edbd171e70d3f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37945 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29util/inteltool: Add chip detection for IceLake chipsJohanna Schander
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29nb/intel/sandybridge: simplify ME lock and memory enable bit writeFelix Held
Timeless build results in identical image for X230. Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29nb/intel/sandybridge: add and use defines for ME base and mask registersFelix Held
Timeless build results in identical image for X230. Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registersFelix Held
This patch didn't change the resulting binary for an X230 when using TIMELESS_BUILD=1 Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-29ec/google/chromeec: ignore LIMIT_POWER based on command code in responseRizwan Qureshi
Assume that LIMIT_POWER is not requested if the ec does not support it. Do this by checking the command code in the response message instead of return value. BUG=b:146165519 BRANCH=None TEST=Boot puff with EC which does not support LIMIT_POWER param. Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-12-28mb/lenovo/*/acpi_tables: Don't initialize already initialized fieldsPeter Lemenkov
Don't initialize fields with zeroes since gnvs structs were zeroed out in southbridge already. Change-Id: I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-28util/testing: Remove romcc from testingPatrick Georgi
Change-Id: If90193dc7c85133b10082c68a6cec6c1b0b35ffb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37958 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27soc/amd/common: Correct SPI FIFO size checkMarshall Dawson
When checking that command and data fit in the FIFO, don't count the first byte. The command doesn't go through the FIFO. TEST=confirm error (4+68>71) goes away on Mandolin BUG=b:146225550 Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-27util/docker/coreboot-sdk: Add libcurl4 requirements for em100Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia1cd7e12f12cb6d26a10fd358a3b32c31ce1c834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-12-27dram-spd: Remove free()Bora Guvendik
free() is not needed since the memory is not dynamically allocated. Change-Id: I90659722aaca6ced1e1cbc3db4180b0811205e95 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-27mb/lenovo/*/acpi_tables: Don't zero out gnvs againPeter Lemenkov
The gnvs structure was zeroed out already in the following files: * src/southbridge/intel/i82801ix/lpc.c (t400 and x200) * src/southbridge/intel/i82801gx/lpc.c (thinkcentre_a58) Change-Id: Id7d552e1c4084a0b36b98f9627a85a75c8b90e81 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-27mb/*/*/acpi_tables: Remove unnecessary function callPeter Lemenkov
Remove acpi_update_thermal_table local function. Change-Id: I4857348088feb8eaf1dd7f553c4efb29da8943cf Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27util/mainboard/google: add support for VolteerPaul Fagerburg
create_coreboot_variant.sh now supports the Volteer baseboard in addition to Hatch. The shell script and supporting python code are moved up one level, while retaining the ${BASE}/template/* file structure for each supported baseboard. kconfig.py has to add slightly different text to Kconfig.name depending on which baseboard is selected. BRANCH=None BUG=b:146646594 TEST=Create variants of Hatch and Volteer, check that the staged commits are correct. $ ./create_coreboot_variant.sh hatch sushi b:12345 src/mainboard/google/hatch/Kconfig and Kconfig.name will have new sections for SUSHI. src/mainboard/google/hatch/variants/sushi will have a copy of util/mainboard/google/hatch/template $ ./create_coreboot_variant.sh volteer ripto b:12345 src/mainboard/google/volteer/Kconfig and Kconfig.name will have new sections for RIPTO. src/mainboard/google/volteer/variants/ripto will have a copy of util/mainboard/google/volteer/template Also run the script with an existing board name to verify that you can't create a variant that already exists. Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-27mb/google/kohaku: Update reset_delay_ms for digitizer deviceSeunghwan Kim
We found the driver binding failure issue could be cleared with 100ms of "reset_delay_ms". Needs further check with device vendor, anyway it seems the IC need some time before communication after de-assertion of reset. BUG=b:129159369 BRANCH=firmware-hatch-12672.B TEST=Verified driver bound successfully. Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: Iccb33c13c9a390a2c971325c74c0c4ad4b08618e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-27cpu/intel/microcode: Apply more strict guard for assembly filesKyösti Mälkki
Change-Id: I8243be7c9a57402b2ac1cfa1c0552990d4a4ba74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27arch/x86: Remove <arch/cbfs.h>Kyösti Mälkki
There are no symmetrical headerfiles for other arch/ and after ROMCC_BOOTBLOCK and walkcbfs() removal this file ended up empty. Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-27arch/x86: Remove walkcbfs()Kyösti Mälkki
This was used in romcc bootblocks. Change-Id: Ie0cfbf124922d04a3320404d667610ad369ec00b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-27util/romcc: Drop romcc supportArthur Heymans
Finally all boards use a GCC compiled bootblock! Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27Makefile: Remove romccElyes HAOUAS
Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-27arch/x86: Drop ROMCC_BOOTBLOCK symbolArthur Heymans
Change-Id: I968c4392849045cd50bfe2c83de44daba38ee245 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-27bootblock: Support normal/fallback mechanism againKyösti Mälkki
Change-Id: I7395e62f6682f4ef123da10ac125127a57711ec6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37760 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27mb/google/hatch/var/dratini: Add a new sku for dragonairWisley Chen
Add a new sku for dragonair BUG=b:146504217 TEST=emerge-hatch coreboot Change-Id: I4492d65f35d3583df1606c5f2901228b3ae14e4a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-27ec/google: Fix wedging AP on early ec sw syncTim Wawrzynczak
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power limits to reasonable defaults and can wedge the AP by browning out at the end of vboot. BRANCH=none BUG=b:146165519 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27drivers/ipmi/ipmi_fru: Add missing <stdlib.h>Elyes HAOUAS
malloc() needs <stdlib.h> Change-Id: I0cf6a5b76543cb6dac584de6628cfc459d5a60a8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37884 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27src/include: Remove min/max() from <stdlib.h>Elyes HAOUAS
Change-Id: I9ded44422a267e244343502dd5d6ab355e5a788d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37378 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27mb/*/*/early_init.c: Remove defined but not used macroElyes HAOUAS
Change-Id: I69c3b0b96fde8dc44a961c3d687f5aadbbdddde0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37644 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26util/superiotool: alter Makefile to build the binary on FreeBSDIdwer Vollering
Change-Id: Ia96bee18abcdf278ae9178471cd4af2de454facf Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-26nb/haswell/minihd: correct subsystem IDMatt DeVillier
The subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: I74cbba31e93f9bb5b18d3ada780a0f24614ba029 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26soc/broadwell/minihd: correct vendor, subsystem IDsMatt DeVillier
Codec vendor ID was copy/pasted from Haswell, should be 0x80862808. Subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: Idf4446d3437de0dc533baa3b2b4eb49f816807a6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37860 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26mb/google/hatch: Clean up duplicate methodEric Lai
Moving Enable/disable GPIO clock gating to soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26mb/google/octopus/variants/dood: support LTE moduleRen Kuo
related LTE GPIOs: GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:146843935 BRANCH=octopus TEST=build and verify on the DUT with LTE Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Ief6c993ede2bb4b3effbb05cfe22b7af4fcf7faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26mb/google/octopus/variants/bobba: fix LTE power sequence and moveSheng-Liang Pan
get_board_sku to smm stage. fix Power_off section power sequence. power_off_lte_module() should run in smm stage, add variant.c in smm stage. also move get_board_sku() to mainboard_misc.c so that we can use it in smm stage and ramstage. BUG=b:144327240 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I287ba1cb092a95b3a9dd1f960a3b84fd85b9b221 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37649 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26mb/google/octopus: Add two new sku IDs for foobTommie
Declare these sku IDs: -SKU: 1 Foob, 1-cam, no touch, no pen. -SKU: 9 Foob360, 2-cam, touch, pen. BUG=b:145837644 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com> Change-Id: Iffcbb3f6f945ea299ff687a383a82b88dcd11ea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26Doc/tutorial/part2.md: Align headings with part1.mdAngel Pons
Substitute `Part` with `Step` on this file's headings and use present tense instead of gerund. Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26Doc/tutorial/part1.md: Fix minor formatting issuesAngel Pons
Make sure all titles are capitalized, and add a missing period. Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26Doc/index.md: Fix a typoAngel Pons
Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-26drivers/generic/cbfs-serial: Add driver to read serial from CBFSMatt DeVillier
Add a new driver to support reading a board serial number from a text file in CBFS and injecting into the SMBIOS tables. Allow driver to be selected at the .config level and not require inclusion at the board level. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 20:05:03 +0000