| Age | Commit message (Collapse) | Author |
|---|
|
Previously incorrect sets of SATA ports were enabled.
There are no publically available schematics, but I am almost certain
the new values are correct.
The original 0x33 value was carlessly copy pasted, and only enables
ports 0, 1, 4, 5, leaving 2, 3 disabled.
On the SFF, with 0x33 only the first 2 ports worked. I have verified
by plugging in devices under the stock firmware that 0, 1, 2 are the
ones that should be enabled, so setting the value to 0x7 per datasheet.
This was also tested in practice to work.
I don't have an MT, but I was told the two white ports didn't work
with 0x33, so those are most certainly ports 3, 4, hence me setting
the value to 0xf. If the MT's working ports are port 0, 1 on the PCH
this is correct.
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
<string.h> is supposed to provide <stdarg.h> and <stdio.h>
Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
<device/pci.h> is supposed to provide <device/pci_{def,type}.h>
Change-Id: Ia645b8dba8c688187a25916f508593f333821f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: If8be8dc26f2729f55dc6716e6d01e2b801d79e44
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: Ib81c81843a5252e2ead9ce175cea2fa42f0e8152
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Starting with version 18 LLVM puts code and data generated with
-ffunction-section -mcmodel=large inside sections with an 'l' prefix.
This would now also pick up const data in .rodata.
Change-Id: Ie07779ef548337772183ffe2d642f971d8cceae7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Fill GPIO table for Sundance.
BUG=b:327520553
TEST=emerge-nissa coreboot
Change-Id: I53ed5874347006985ca5231d1531fa519088f796
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613
Tested-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
|
|
Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
|
|
Change-Id: I66265727b68b6ad10722439314b466298dbfff28
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81819
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.
Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
As 0C is 273.15K you could argue that 2731 and 2732 are both correct.
However, 2732 is deemed as correct both throughout the codebase and in
the ACPI specification[1].
[1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/11_Thermal_Management/thermal-control.html#temperature-change-notifications
Change-Id: I845bc750681c7ae6f2d1342b32983b990ce6d296
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81197
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
|
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the
result won't be used. Also, reorder a condition so that compile-time
constants appear first, so as to help the compiler optimize it out.
Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
In next phase, craaskov will remove external fivr. Use the board
version to config external fivr for backward compatibility and
show message.
BUG=b:330253778
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:333605309
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared.
Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch adds a new variant trulo for the baseboard trulo.
BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya
Change-Id: I91157d252ef56c8938bfc08ed0f734c5dc7e614d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81627
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
This patch adds a new baseboard trulo. This commit is a stub which
only adds the minimum code needed for a successful build.
BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya
Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and
POSTCAR_STAGE which are used by all Xeon-SP platforms.
After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0
is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X,
POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE.
TEST=Build and boot on intel/archercity CRB
Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a good board for compiling TPM PPI sources for the following
reasons (based on `config TPM_PPI` definition):
- uses TPM
- the board is not related to ChromeOS
- ACPI tables are enabled
- it doesn't use EDK2 payload
At the moment drivers/tpm/ppi.c seems to not be compiled by CI at all,
see CB:69161 and CB:81590.
`CONFIG_TPM_PPI` is off by default but at least several configurations
under `configs/` (Protectli, MSI) should exercise the file because they
use EDK2 payload which changes default value. This is however negated
by abuild disabling all payloads and thus effectively preventing
`CONFIG_TPM_PPI` from being set. This board not using EDK2 also ensures
that `CONFIG_TPM_PPI=y` will not disappear after some future
`make savedefconfig`.
Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ibd35bef4182ea075ef5fa153e2e47678ffce171b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: I26c2abfce3417ed096d945745770fcae91a1e4ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81814
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Set orientation of KD_KD101NE3_40TI to LB_FB_ORIENTATION_RIGHT_UP to
align the volume up/down direction with menu up/down in FW screen.
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage, and check FW screen on
wugtrio, test volume key behaves as expected.
BRANCH=corsola
Change-Id: Ie101cc8b983d3d16587f88fa787ed622e59d27eb
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81752
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch renames the 16MB FMD file to remove the baseboard-specific
name 'Nissa'. This allows other supported baseboards to utilize the
16MB SPI flash. Additionally, the patch attempts to create a generic,
unified 32MB FMD file for both brya and nissa variants.
BUG=b:333314089
TEST=Build and boot Nivviks.
Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic7f6690786661e523292f7382df71ae4ad04d593
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The header file console/console.h is unused, just drop it.
TEST=abuild -t google/corsola -b wugtrio -a
TEST=abuild -t google/geralt -b ciri -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
|
|
Move the soc_get_ioapic_info for platforms with IIO IO-APICs to
a separate file from src/soc/intel/xeon_sp/acpi.c.
TEST=Build intel/archerticy CRB
Change-Id: I59022b7685539491604724ef3b550da1cfd53f13
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Iccdb4770890751b7f9d1b35248fe57993342fd50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: Ic71516ae73d61c9f13876a5acc071645bbe8e866
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81594
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To fix the build error below when include i2c_common.h, we should
include the necessary header for check_member.
"""
src/soc/mediatek/common/include/soc/i2c_common.h:24:42: error: expected ')' before numeric constant
24 | check_member(mt_i2c_dma_regs, dma_tx_len, 0x24);
| ^~~~~
| )
"""
TEST=abuild -t google/geralt -b ciri -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I266571686e452e2b7514afee42ff0a48f8891831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81684
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fine tune the panel clock to prevent mipi noise from affecting wifi
band. After tuning, the panel refresh rate keeps at 60Hz and wifi test
passed. Just keep consistent with the Linux kernel panel driver
panel-boe-tv101wum-nl6 [1] configuration.
[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/5029075/59
BUG=b:330807136
TEST=fw screen display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the
updated verbtable received from Realtek. Updated Version : 5.0.3.1. This
fixes the headset detection failure, when power_save is enabled in
legacy hda driver.
BUG=b:330433089
BRANCH=None
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.
Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Terry Cheong <htcheong@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Change-Id: I878c14058e1edc0f64e37c2fc16b8dcf75b90192
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81631
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
Starting with version 18 LLVM puts code and data generated with
-ffunction-section -mcmodel=large inside sections with an 'l' prefix.
Change-Id: Ib755673dfa9e71172bbef0a5aec075154c89a97b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81675
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A register dump between native and MRC.bin raminit showed a difference
in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses.
Tested on Lenovo X220: Still boots and works fine.
Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79759
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When DEBUG_SMI is selected, common code may use these helpers to handle
addressing and initialising the SoC-specific UART. Therefore, add uart.c
to be compiled into SMM.
Change-Id: If7c6f2346d5f9ffb371d51d1de6f0b695acedf10
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81072
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
When soc/amd/genoa was renamed to soc/amd/genoa_poc and mb/amd/onyx
was renamed to mb/amd/onyx_poc, the MAINTAINERS file wasn't updated, so
no reviewers were added automatically to patches on Gerrit that change
things in soc/amd/genoa_poc or mb/amd/onyx_poc. Fix this by updating the
folder names in the MAINTAINERS file too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib52781ebc98bd2ce9df495526cfaf9d884aace50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81679
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Place METEORLAKE SoC in alphabetical order.
Change-Id: Ic04163e746ee3e450e58563abbf994e6aa44e69d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81677
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Replace fixed-width integers for pointers and sizes with uintptr_t and
size_t, promoting portability across 32-bit and 64-bit architectures.
For FSP-API specific UPD assignments, rely on `efi_uintn_t` rather
fixed size datatype uint32_t/uint64_t.
BUG=b:242829490
TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and
64-bit compilation.
Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81615
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
This refactoring ensures bmp_load_logo() takes logo_size as an
argument, returning a valid logo_ptr only if logo_size is non-zero.
This prevents potential errors from mismatched size assumption.
BUG=b:242829490
TEST=google/rex0 builds successfully.
Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81618
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
unlock_pam_regions() is needed for SKX and CPX. Put the codes into
chip_gen1.c so that it could be shared among SoC generations.
After shared, unlock_pam_regions() is still called from SKX and
CPX SoC specific codes. SPR will also use chip_gen1.c, but it will
not call unlock_pam_regions().
TEST=Build and boot on intel/archercity CRB
Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This removes the runtime SMI call to set up the communication buffer
for SMMSTORE in favor of setting this buffer up during the installation
of the smihandler.
The reason is that it's less code in the handler and a time costly SMI
is also avoided in ramstage.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
Fast SPI code assumes only one SPI flash is present. The SPI flash
driver for older southbridges is able to detect multichip. See the
spi_is_multichip() in src/southbridge/intel/common/spi.c.
Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two
chips populated instead of one. With this change, both chips are probed,
and the correct total size is calculated. Otherwise, only the first one
was probed, which resulted in an error such as:
SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!
Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
<types.h> is supposed to provide <stdint.h>.
Change-Id: Ia68a0dc8fba4a48401e213ebb8356e32f0a019ab
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Add support for TigerLake Halo SoC, based on CNL profile.
Test: Convert GPIO dump from inteltool into coreboot macros for
out-of-tree TGL board.
Change-Id: I26eff225c2045edfe5836283be7b4c63f6b405e8
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
|
|
commit b7832de026 (x86: Add .data section support for pre-memory stages)
added a data section to the bootblock. This needs to be accounted for in
the linker script.
Change-Id: I39abe499e5e9edbdacb1697c0a0fc347af3ef9c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81434
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:332488817
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared
Change-Id: I6d7b35dbf8ac9b0abb42f64a947b4bb94f3c6b0f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Daniel Kang <daniel.h.kang@intel.com>
|
|
Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Call into FSP-T using the protected mode wrapper
and enter long mode in FSP-T support assembly code.
TEST: Booted on ibm/sbp1 in long mode.
Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Based on schematic and gpio table of sundance, generate overridetree.cb
settings for sundance.
BUG=b:328505938
TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage
Change-Id: I857be7bc7f98281cac57fef85bf9f3cef2ec14e9
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
I2C slave addresses 0x41.
BUG=b:332458912
BRANCH=None
TEST=emerge-nissa coreboot & working correctly in DUT
Change-Id: I2d26bfd4f415aa128b6256f83bc58987b15a557a
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81610
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I18bf67cae7af90a92a030e552af6dc6b134a8357
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
intel/common/block/acpi provides default soc_get_ioapic_info for
single IOAPIC model. Use the default soc_get_ioapic_info when
XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and
later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Include `fsp_header.h` from vendorcode for dynamic FSP_INFO_HEADER
selection.
BUG=b:242829490
TEST=google/rex0 builds successfully with 64-bit FSP.
Change-Id: If165e0517752f320d898cf82f298aa9f5699ae86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81624
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change refactors EDK2 essential header management within the FSP
directory to ensure compatibility.
Header selection is now dynamically based on:
* FSP specification version: Distinguishes between 1.1 and 2.x
* EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header
FSP Header
|
|-> FSP 1.1 specification FSP_INFO_HEADER
|-> FSP 2.0 specification EDK2 release
|-> EDK2_2017 FSP_INFO_HEADER
|-> EDK2_2020 FSP_INFO_HEADER
|-> EDK2_2021 FSP_INFO_HEADER
|-> EDK2_2023 FSP_INFO_HEADER
Any .C/.H file requires to include FSP_INFO_HEADER can now just add the
FSP header alone.
BUG=b:242829490
TEST=Able to build google/rex0 with 64-bit FSP.
Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch introduces the FSP_SIG macro into EDK2 headers to ensure
compilation compatibility when using FSP 2.x specifications.
Previously, the macro was only defined for FSP 1.1.
BUG=b:242829490
TEST=Successful build of google/rex0 with 64-bit FSP.
Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
Ensures the FSP debug handler adheres to the EFI calling convention,
enabling seamless integration with coreboot infrastructure.
This is critical for 64-bit coreboot and FSP communications.
BUG=b:242829490
TEST=FSP debug logs successfully captured via coreboot event handler.
Change-Id: I9085a6c7d50e58fb56cbbc61da3a0af094d0dc05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
This patch defines __efiapi (based on EFIAPI) for coreboot-compliant
EFI calls. This lays the groundwork for future 64-bit EFI calling
convention support within coreboot/FSP.
BUG=b:242829490
TEST=FSP debug log accessible via coreboot event handler.
Change-Id: I21660f8ebeed3b9ef060118928a940a470492bb8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81620
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities such as system power down.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:328729536
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
[When connected 60W adapter without battery]
Before:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
After:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:60000000
[When connected 45W adapter without battery]
Before:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
After:
constraint_0_power_limit_uw:15000000
constraint_1_power_limit_uw:45000000
constraint_2_power_limit_uw:45000000
Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
In order to avoid the noise caused by the codec output to the audio
jack during the shutdown and poweron process, we will use GPP_A11 for
the codec power supply gate, keep low during the startup process, and
wait for the driver to turn on. This change does not affect the beep
output of depthcharge.
BUG=None
TEST=There is no squeaking sound when turning on and off
Change-Id: I5982be5a8d965086b46861f4c2c758d9bdee6e75
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81629
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
It does not hurt to do this and makes it possible to link romstage
sources into bootblock.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79576
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This fixes a warning about casting an integer to a pointer, where the
integer has a different size than the pointer (UINT32).
Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81559
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fine tune the panel clock to prevent mipi noise from affecting wifi
band. After tuning, the panel refresh rate keeps at 60Hz and wifi test
passed. Just keep consistent with the Linux kernel panel driver
panel-boe-tv101wum-nl6 configuration.
BUG=b:330807136
TEST=fw screen display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I128b33fbcda9759330a363ebb6cf66415405c488
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81625
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Linux kconfig has its own implementation of KCONFIG_WERROR now, so use
that. This reduces our patch count by 2.
Change-Id: I4f5f1f552e96f8ef7a4c5c0ab2ab7e2b6d798ceb
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81223
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently the SRAT table only exposes one proximity group as
it uses the LAPIC node_id, which is always initialized to 0.
Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it
to make sure that at least one proximity group for every socket
is advertised.
For now the SNC config isn't taken into account.
Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Add a new Staryu follower device 'Wugtrio'. And also enables SD card
support and MIPI panel support.
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move starmie mipi panel selection from BOARD_GOOGLE_STARYU_COMMON
section to BOARD_SPECIFIC_OPTIONS section.
BUG=None
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: Ib5792542f55a78c0840b6169b5ecf092e7cefe98
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81602
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
This patch replaces UINT8 with uint8_t to align with coreboot's
standard data type conventions.
This promotes consistency within the codebase.
BUG=b:242829490
TEST=Verified firmware splash screen functionality on google/rex0.
Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81571
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
With this, `quilt pop -a` leads to an original Linux kconfig tree,
making it easier to apply kconfig updates.
Change-Id: I771bbd0f8244cae38317bd5b1f809b74771b176f
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Enable SMLINK1 interface for PMC-PD communication to configure Type-C
muxes.
Refer RPL EDS vol 1: 765585.
BUG=b:327622474
BRANCH=None
TEST=Boot image on SKU2 and check PMC-PD working.
Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
|
|
Make get_soc_power_limit_config() a public function to use on brya
variants. Add prefix 'variant_' for it.
BUG=None
BRANCH=brya
TEST=emerge-brya coreboot
Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add sundance supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE
BUG=b:332201349
TEST=Use part_id_gen to generate related settings
Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Deku has two Ethernet ports. Currently both get assigned the wrong
MAC address due to the LAN devices indices being swapped and
vpd ethernet_mac0() affects device eth1 and vpd ethernet_mac1() affects
device eth0.
Correct the device indices for LAN devices so ethernet_mac[0-1] in vpd
can apply to the correct ethernet ports.
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=vpd -s ethernet_mac0=<mac address0>
vpd -s ethernet_mac1=<mac address1>
reboot the system and check ifconfig
eth0 and eth1 MAC addresses are fetched correctly
Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81564
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for
THC0, and 0x7e4b for THC1.
0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0
and THC1 respectively.
Refer MTL EDS vol 1: 640228.
BUG=b:307775082
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81330
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
|
|
Add K&D panel KD_KD101NE3_40TI serializable data to CBFS.
Datasheet: KD101NE3-40TI-A003 _Pre SPEC_20231218.pdf
BUG=b:331870701
TEST=build and check the CBFS include the panel
BRANCH=None
Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81583
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, if something is overlapped, you get this:
ERROR: Ramstage region _ramstage overlapped by: fallback/payload fallback/opensbi
This change prints out the start and end of the sections.
Change-Id: Ica8c05b63ed9bbd28e2d3daa4dc7c2f9d8da3f55
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81544
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
GDB debugging is not implemented with x86 long mode.
Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81379
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
unlock_pam_regions routes Programmable Attribute Map (PAM) access
to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the
step to SoC specific codes.
TEST=intel/archercity CRB
Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
Add dynamic PCI domain _OSC ASL generation codes, supporting both
PCIe and CXL domains.
Dynamic SSDT generation is used to generate a list of ASL device
objects based on FSP outputs (e.g. the SoC/SKU configurations)
and _OSC is a method inside these objects (hence it would be
straightforward to be generated altogether, plus some C codes
managed boot configs could be referenced as well).
This usage is optional. It is helpful for cases where the same
code set supports multiple SKUs/SoCs (difficult to be handled by
one set of static SSDT), and the CPU performance is good enough
to run SSDT generation logics with minimal costs.
TEST=intel/archercity CRB
Tested with https://review.coreboot.org/c/coreboot/+/81377.
Change-Id: I711ce5350d718e47feb2912555108801ad7f918d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
IBL (Integrated Boot Logic) provides a subset of server
PCH logics for no-PCH solution. IBL is with limited features
and registers exposed, PCIe root ports/USB/SATA/LAN support are
removed.
Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/
UDS_SOCKET_RES and retires the usages of STACK_RES/
IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common
codes to work for both 6th Gen before and later.
Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81040
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.
I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c as a test for bug b/328729536.
```
const struct cpu_power_limits limits[] = {
{PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}
```
And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this patch: msr_pl4 was not changed, it's always 114
- After this patch: msr_pl4 was changed to 80
BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.
Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Update GPIO configuration according to the schematic changes. The
locations of speaker and DMIC are swapped.
- Speaker: I2S2 -> I2S1
- DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5
BUG=b:318584606
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81444
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
ISH Firmware name needs to be configured only when full sensing
capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA
property needs to be added only when UFS is enabled through STORAGE_UFS
FW_CONFIG. Hence configure the ISH device at run-time based on
FW_CONFIG.
BUG=b:319164720
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Add Synaptics touchpad via HID-I2C interface in I2C5 bus for glassway.
BUG=b:331677400
BRANCH=firmware-nissa-15217.B
TEST=emerge-brya coreboot and check touchpad function work.
[INFO ] input: PNP0C50:00 06CB:CE9B Touchpad as /devices/pci0000:00/0000:00:19.1/i2c_designware.5/i2c-17/i2c-PNP0C50:00/0018:06CB:CE9B.0001/input/input4
[INFO ] hid-multitouch 0018:06CB:CE9B.0001: input,hidraw0: I2C HID v1.00 Device [PNP0C50:00 06CB:CE9B] on i2c-PNP0C50:00
Change-Id: Ifbb2cb750a80bc6e8f96609257dcd1e695ad1fa4
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:328505938
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_SUNDANCE
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1aacff869663e1db74cd485787d7103b9ec5602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78448
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Use macros from the Linux kernel 6.5 to make the inline assembly also
compile on clang.
TEST: See that the generated code is identical on GCC and compiles on
clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Add a new Kingler follower device 'Kyogre'
BUG=b:318614302
TEST=emerge-corsola coreboot
Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c
Signed-off-by: Kei Hiroyoshi <hiroyoshi.kei@fujitsu.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81218
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
The RPL FSP currently uses HECI commands to retrieve the chipset
initialization version because the MBP HOB creation is disabled
(SkipMbpHob=1). This has resulted in an approximate 150ms increase in
boot time. Investigations are ongoing to determine the cause of the
delay when using HECI commands. As an interim solution, this patch sets
SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset
initialization version, which is expected to reduce the boot time.
BUG=b:328430167
TEST= Able to build,boot and collect boot time data of brya.
With this patch:
963:returning from FspMultiPhaseSiInit 1,337,481 (249,046)
Without this patch:
963:returning from FspMultiPhaseSiInit 1,496,268 (408,194)
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I8a99a57b644732074e41051d99e63576f1edd229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
GNR N-1 FSP headers are a set of stub headers used to fulfill
build sanity check for GNR SoC and CRB codes before the formal
FSP headers are published. The N-1 headers are forward compatible
with the later formal headers.
Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
