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2022-03-18Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run ↵Nick Vaccaro
serially"" This reverts a change that was causing hangs and exceptions during boot on an ADL brya4es. The hang (or APIC exception) occurs at what appears to be the FSP MP initialization sequence, prior to the "Display FSP Version Info HOB" log being displayed : [DEBUG] Detected 10 core, 12 thread CPU. [DEBUG] Display FSP Version Info HOB This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924. BUG=b:224873032 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es is able to successfully reboot 200 times without any issues. Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18soc/intel/common/block/cse: Change loglevel prefix to WARNINGWisley Chen
This message is not really an error message, so BIOS_ERR is inappropriate. The message does seem more like a warning though, that the developer could have multiple Kconfigs selected to send EOP, therefore switch to BIOS_WARN instead. BRANCH=firmware-brya-14505.B TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I57a34334007a6a7443302c2f25de3d5c87c85573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-17docs/contributing/gsoc: Add reference to easy projectsFelix Singer
Change-Id: I22e4a7c6385ffb9ba77e10edad41ef3d027ba694 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62906 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17Documentation/contributing/projects: Add "easy projects" sectionFelix Singer
Change-Id: Ibf91a879478e03b584756dc24fe33fb013803f9d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-17soc/intel/adl: Remove IOM Mctp command from TCSS ASLMAULIK V VAGHELA
TCSS ASL code was carried forward from TGL and it used to follow the same sequence. Recently as part of s0ix hang issue, it was found that sending IOM MCTP command as part of TCSS D3 Cold enter-exit sequence created an issue. We discovered that due to change in hardware sequence, ADL should not set/reset IOM MCTP during D3 cold entry or exit. This patch removes the bit setting from ASL file to prevent hang in the system. This patch also removes obsolete Pcode mailbox communication which is no longer required for ADL. BUG=b:220796339 BRANCH=firmware-brya-14505.B TEST=Check if hang issue is resolved with the CL and no other regression observed Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62861 Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17util/liveiso: Remove coreboot toolchain from todoFelix Singer
The coreboot toolchain is a huge blob and increases the size of the build a lot. If needed, the specific toolchain can be added before building the ISO or with `nix-shell` later in the live system, as shown below. $ nix-shell -p coreboot-toolchain.i386 Thus, remove this from the todo list. Change-Id: Ia24ceb84f202828f1c97d3ba5bafbf6af0361bdb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-17soc/amd/cezanne: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17soc/amd/picasso: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17soc/amd/sabrina: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-17mb/google/brya: Remove mainboard.aslEric Lai
Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya: Remove Pcie Generic driver for WWANCliff Huang
This was to merge PCIe ACPI code to WWAN device. But, now use recent _DSD generation changes in FM driver instead. PCie generic driver is not used for WWAN at this time. Also, RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya/var/banshee: Update DPTF parametersFrank Wu
Follow thermal team design to update thermal table. BUG=b:223492897 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-17mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreenFrank Chu
For galnat platform, support 2nd ELAN touchscreen via SSFC. Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8) for touchscreen controller switch. BUG=b:221002826 TEST=touch screen is functional. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17drivers/wifi/generic: Fix properties in generic-under-PCI device caseTim Wawrzynczak
In the devicetree case where a generic device underneath the Intel PCI CNVi device carries the device properties, the incorrect device was passed to wifi_ssdt_write_properties. Also while here, update the UUID for `DmaProperty` to match what Microsoft defined here: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports BUG=b:215424986, b:220639445 TEST=dump SSDT and see that _PRW for CNVi device is no longer garbage, but contains the value from the devicetree (GPE0_PME_B0). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2022-03-17driver/intel/usb4/retimer: Change loglevel prefixWisley Chen
In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message in not support dpf ports. It's not error and changes the loglevel prefix to BIOS_INFO. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17soc/intel/alderlake/retimer: Change loglevel prefixWisley Chen
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17ec/google/chromeec: Change loglevel prefixWisley Chen
In most boards, it doesn't write OEM_NAME in CBI to override the manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR" BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya/var/kinox: Modify 15W SOC power control settingDtrain Hsu
Modify 15W SOC default power settings for kinox. - PL2 39W - PL4 100W - Psys_PL2 65W - Psys_imax_ma 5000ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoCSubrata Banik
This patch refactors the current P2SB common code driver to accommodate the future SoC platform with provision of more than one P2SB IP in disaggregated die architecture. IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is renamed as SoC in MTL.) P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c is added only for PCH/SoC P2SB. BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-17mb/google/brask/variants/moli: set eMMC pin in bootblockRaihow Shi
1.Assert eMMC enable pin in bootblock 2.Deassert eMMC reset pin in bootblock BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17qualcomm/sc7280: Add mdp clock support to turbo in corebootTaniya Das
This change supports the configuration and enablement of mdp clock to vote for turbo and supports different display panel resolutions and framerates. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17qualcomm/sc7280: Add display external clock support in corebootTaniya Das
Add support for EDP (Embedded DisplayPort) clocks in coreboot. This change supports the configuration and enablement of EDP PIXEL, LINK, LINK_INTF and AUX clocks. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17mb/google/nissa/var/nivviks: Set gpio override to board_0Eric Lai
Follow the latest schematic change, gpio will match the baseboard. Return the current table as override. BUG=b:223677877 TEST=audio is functional on board_0. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-17ec/chromeec/ec_smbios: Set system manufacturer for ChromeOS devicesMatt DeVillier
Currently, many Linux drivers use DMI quirks to identify ChromeOS devices and handle them accordingly: namely they look for the SMBIOS system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be coreboot. Historically this was consistently the case, but recent model ChromeOS devices allow the OEM to set the mainboard manufacturer, which is also the default system manufacturer. This breaks many DMI quirks, notably ones used by SOF (sound open firmware) for audio. To fix this, set the system manufactuer for ChromeOS devices to "Google" for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM customization in place for the mainboard manufacturer. Since boards selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding the default mainboard manufacturer, they are the only ones which need this correction. Test: build/boot google/bloog with Linux 5.16, verify SOF drivers correctly detect device as a Chromebook and load the appropriate audio firmware. Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax valuesCurtis Chen
Add ADL-P MCH ID 4, 8, 9, 10 into this list. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17soc/intel/common/block/cpu: Enable ROM caching in ramstageSubrata Banik
Cache the BIOS region and extended BIOS region if the boot device is memory mapped, which is mostly the case with Intel SoC platform. Having the ROM region cached helped to improve the pre-boot time. TEST=Able to boot redrix to Chrome OS without seeing any sluggishness. Additionally verified on EHL board (from siemens), shows significant savings in payload loading time as below: Here is the timestamp snippet showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-17soc/intel/common/fast_spi: support caching `ext_bios` in ramstageSubrata Banik
This patch provides a way to cache `ext_bios` region for all stages to save boot time. TEST=Able to see the ext_bios region in MTRR snapshot when cached on the Brya variants. Here is the timestamp snippet showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-17include/efi: Clean up efi_datatype.h fileSubrata Banik
This patch cleans up `efi_datatype.h` to allow other SoC and/or driver code to use this file. `PiPei.h` file only gets added from UDK2017 hence, the platform with the older EDK2 base (prior to UDK2017) is unable to resolve this file dependency. This CL removed the `PiPei.h` header and only added the required header file `PiPeiCis.h` for platforms with UDK base >= 2017. BUG=b:200113959 TEST=Able to build Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17drivers/wifi/generic: Fix is_cnvi functionEric Lai
dev->ops = &wifi_cnvi_ops need is_cnvi be true. This cause the exclusive statement so is_cnvi never be true in !DEVTREE_EARLY. BUG=b:224317408 TEST=no assertion in coreboot. [EMERG] ASSERTION ERROR: file 'src/acpi/acpigen_pci.c', line 24 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I1ca6312ce164c43021686b483f6579164614cede Reviewed-on: https://review.coreboot.org/c/coreboot/+/62784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16soc/qualcomm/common: Add dram information to CBMEM tableRavi Kumar Bokka
BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-03-16mb/hp/snb_ivb_laptops: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is in one place and not distributed over two files. Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16mb/google/brya/var/kinox: Enable PCIe-eMMC bridgeDtrain Hsu
Enable PCIe-eMMC bridge for Kinox. BUG=b:218786363, b:211176722 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16mb/google/brya/var/kinox: Modify the DPTF/Fan parametersDtrain Hsu
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters. BUG=b:221180425, b:222020226, b:221182596 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16soc/intel/common: Retry MEI CSE DISABLE commandSridhar Siricilla
As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't respond or sends the garbled response. It retries the command additionally 2 more times. TEST=build and boot the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16soc/intel/common: Retry END_OF_POST commandSridhar Siricilla
As per ME BWG, the patch retries END_OF_POST command if CSE doesn't respond or sends the garbled response. It retries the command additionally 2 more times. BUG=b:200251277 TEST=Verify EOP retry mechanism for brya board. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-163rdparty/amd_blobs: advance submodule pointerJason Glenesk
This adds the following commits: * a069321 cezanne: Update SMU firmware to 64.62.0 * d8a51cb cezanne: Upgrade ABL to 0x22146070 Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-16soc/mediatek: PCI: Remove global variableJianjun Wang
Remove global variable and use 'pcidev_path_on_root()' to get the base address of PCIe controller. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16soc/mediatek: Add chip config for setting PCIe configJianjun Wang
Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16soc/amd/common/block: Add mainboard_handle_smiRaul E Rangel
The current SMM framework only allows the mainboard code to handle GPEs. i.e., Events 0 - 23. This change allows the mainboard code to handle any SMI events not handled by the SoC code. This will allow the mainboard code to handle `SMITYPE_ESPI_SMI`. BUG=b:222694093 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-16mb/hp/snb_ivb_laptops: Rename `BOARD_HP_SNB_IVB_LAPTOPS`Felix Singer
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON` to indicate and to make it clear that this option serves as base for others. Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with `INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical. Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16mb/hp/snb_ivb_laptops/Kconfig{,.name}: Reorder selects alphabeticallyFelix Singer
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and coreboot.rom remains identical. Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16mb/google/brya: set GPP_D0 to GPOMark Hsieh
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP firmware successfully. BUG=b:222188263, b:223906569 TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint Firmware Test. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-16libpayload: Parse DDR Information using coreboot tablesRavi Kumar Bokka
BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15i2c: Add configurable I2C transfer timeoutJes Klinke
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15util/ifdtool: Add Meteor Lake platform support under IFDv2Subrata Banik
BUG=b:224325352 TEST=Able to build ifdtool. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3564efa27d0271286435284e745458aada987008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15intel/common/block: Add APL and GLK PCI IDs for HDASean Rhodes
Add PCI ID's for APL/GLK so they can use HDA. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-15mb/google/guybrush/var/nipperkin: update APU STT settingKevin Chiu
BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-15mb/google/brya/var/banshee: Add camera privacy settingFrank Wu
Using the GPP_F19 as privacy switch for camera in banshee. BUG=b:223712143, b:216110896 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-15lib/spd: Do not print part number if it is not availableWerner Zeh
If the DRAM part number is not available in the SPD data (meaning filled with 0x00) do not print it in the log. Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15soc/mediatek/mt8186: change pmic hwcid from warning to infoRex-BC Chen
The pmic hwcid dumping should not be a warning, so we modify it to info. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15soc/mediatek/common: Add halt() after triggering wdt resetRex-BC Chen
It's more reasonable to halt when we trigger watchdog reset because the whole system should be reset afterwards. BUG=b:222217317 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15mb/google/brya: Disable C1-state auto demotion for Brya & BraskMAULIK V VAGHELA
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since Brya sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results in 110 mW power savings during video playback. Note that C1state Autodemotion feature is not applicable for ADL-P SoC. Hence recommendation is to keep it disabled. BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also power and performance impact has been measure by respective teams. Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-15soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotionMAULIK V VAGHELA
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Check code compiles and correct value has been passed to FSP. Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15Documentation/tutorial/part1.md: Add Fedora package `patch`Eloy Degen
It is necessary to build crossgcc. Change-Id: I32f6507b4d8346bf94aaccd3eef4f22697c33965 Signed-off-by: Eloy Degen <degeneloy@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15soc/intel/common: Pass `FSPM_UPD *` argument for spd functionsSubrata Banik
This patch adds `FSPM_UPD *` as argument for mem_populate_channel_data() and read_spd_dimm(). This change will help to update the architectural FSP-M UPDs in read_spd_dimm(). BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-14mb/google/herobrine: consolidate hoglin/herobrine QUP initsShelley Chen
Hoglin and Herobrine (proto1) should share majority of GPIOs. Conslidating the QUP initializations in mainboard. Also, putting fingerprint init in a conditional as not all devices will have an FP sensor. BUG=b:182963902,b:223826899 BRANCH=None TEST=booted BIOS on hoglin and check for i2c errors in dmesg Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14mb/google/trogdor: Add variant GelarshieMars Chen
New board introduced to trogdor family. BUG=b:223101874 BRANCH=none TEST=make Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com> Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14Documentation: Describe our Coverity Scan integrationPatrick Georgi
Change-Id: I0a2b68a4b4b54c7345280b252d624799316641b1 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-14payloads/seabios: Update stable version to 1.16.0Felix Singer
SeaBIOS 1.16.0 was released on March 2nd. Thus, update the stable version from 1.14.0 to 1.16.0. Change-Id: I475a9be47171bfbe3b3c2d4d1d14bb753d8575a8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-03-14mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstageCasper Chang
Currently the BayHub eMMC enable pin is using the default configuration from the baseboard, which leads to RTD3 not being able to control the GPIO when exiting and entering suspend. To fix this, program the GPIO in the ramstage GPIO table. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage scope enable pin while performing suspend stress and enable pin works as expected. test suspend stress 1000 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/starlabs/labtop: Pull SSD Pin to low when entering S3Sean Rhodes
Pull GPP_D16 to low when suspending, otherwise it will remain active and use power. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytesWerner Zeh
DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14MAINTAINERS: Remove myselfPatrick Rudolph
Change-Id: Ie75912698e58088ff4a334403cb331542abb40fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62754 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14soc/intel/common: Use generic enum type valuesSridhar Siricilla
The patch uses generic enum type values for EOP command handler. So, it renames cse_eop_result enum type to cse_cmd_result and also renames the enum values to have generic name. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14soc/intel/common: Use heci_reset() in the CSE TX and RX flowsSridhar Siricilla
The patch implements error handling as per the ME BWG guide. The BWG recommends HECI interface reset if there is a timeout or malformed response is received from the CSE. Also, the patch triggers HECI interface reset if the CSE link state is not ready in the heci_send() API. TEST=Verify HECI Interface reset in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14soc/intel/common: Implement error codes for for heci_send_receive()Sridhar Siricilla
The patch implements below changes: 1. Implements different error codes and use them in appropriate failure scenarios of below functions: a. heci_send() b. recv_one_message() c. heci_receive() 2. As heci_send_receive() is updated to return appropriate error codes in different error scenarios of sending and receiving the HECI commands. As the function is updated to return 0 when success, and non-zero values in the failure scenarios, so all caller function have been updated. BUG=b:220652101 TEST=Verified CSE RX and TX APIs return error codes appropriately in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/brya/var/kinox: update overridetreeDtrain Hsu
1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. BUG=b:218786363, b:214025396, b:212183045 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCKRaul E Rangel
The verstage.c file contains PSP verstage specific code. We don't need it when using x86 verstage. BUG=b:193050286 TEST=Build and boot guybrush with x86 verstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/google/brya: Set EPP to 45% for all Brya variantsCliff Huang
This sets EPP value to be 45% for all Brya variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. BUG=b:219785001 BRANCH=firmware-brya-14505.B TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14soc/intel/alderlake: Add EPP override supportCliff Huang
This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/dedede: Update DPTF settingTeddy Shih
Update PL1, PL2, and temperature sensor values from thermal team, as well as, we remove unused temperature sensors according to baseboard/devicetree.cb and mainboard schematic. After we check DTT setting, the thermal and performance test pass. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, run following commands: localhost /tmp # cat /sys/class/thermal/thermal_zone*/type x86_pkg_temp INT3400 Thermal TSR0 TSR1 TCPU localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp 45000 20000 32800 32800 39000 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2Felix Held
The one USB2 port on the XHCI2 controller should have the port ID 2.0, since it's the first USB2 port on that XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devicesFelix Held
GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14mb/google/nissa/var/nivviks: Hook up SD host controller GL9750Eric Lai
Select GL9750 driver and add power sequence according to datasheet: GL9750S-OIY04 rev1.22. BUG=b:223304292 TEST=check GL9750 can get enumerated by kernel 5.15. 01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01) Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-14mb/google/nissa/var/nivviks: Enable pen garageEric Lai
Enable pen garage. Pen detect is active low. And wake system when eject. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-14Documentation: Fix broken linksMartin Roth
This change mostly changes links that were identified as broken by the 'website_scans' jenkins job. There were some links that seem to be up at times, but that are identified by link-checker as broken because of SSL issues. At least one other link was changed to point to archive.org so that it doesn't break at some point in the future. We should probably try to make sure that everything is archived there and point to those versions when possible. There are still lots more links to do. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef Reviewed-on: https://review.coreboot.org/c/coreboot/+/62672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-11Documentation: Move firmware flashing tutorial to tutorial sectionFelix Singer
There is no need that the tutorial for flashing firmware has its own point in the main menu. Thus, move it to the tutorial section. Change-Id: Ife6d97254af4c006fe01480a78c76303f9cb34bb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2022-03-11Documentation: Use file paths to flashing firmware tutorialFelix Singer
In preperation for CB:62424, replace HTTP links pointing to the flashing firmware tutorial with file paths to the Markdown files. Change-Id: I6a271a912348cbe002bc9cced9922ed743e1133c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-11docs/contributing/gsoc: Add a collection of useful GSoC linksFelix Singer
Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62660 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10drivers/pcie/generic: Add support to generate code under companion device ↵Cliff Huang
instead Only one ACPI device should be added to a PCIe root port. For the root ports which already have device created, the generated code from this driver needs to be merged with the existing device. By default, this driver will create new device named DEV0. This change allows to generate code under an existing device. ex: (generate code under PXSX): Scope (\_SB.PCI0.RP01.PXSX) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } BUG=b:221250331 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10cbmem: Fix console banner matchesJulius Werner
Since the new loglevel markers were added, there will now be a marker character at the beginning of the coreboot banner string, and this will make the existing regular expressions meant to find it fail to match. This patch fixes the problem by just allowing for a single extra character there (any character to avoid the hassle of having to match the marker explicitly). The extra character is optional so that we will still continue to match banners from older versions of coreboot as well. Since the `?` glyph is not available in basic POSIX regular expressions, we have to switch to REG_EXTENDED syntax (should otherwise make no difference). (Also, move side effects out of assert() while I'm here, that's not actually safe for the standard libc implementation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62720 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10soc/intel/alderlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table after normalizing to the zero-point value. Although consumer CSE sku also supports this feature, it was validated on CSE Lite sku only. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset on Brya/Redrix 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 88,000 945:CSE started to handle ICC configuration 88,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000) 0:1st timestamp 330,857 (48,857) 11:start of bootblock 341,811 (10,953) 12:end of bootblock 349,299 (7,487) Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10mb/google/skyrim: Configure WLANJon Murphy
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mappping derived from Skyrim schematic. BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10mb/google/skyrim:Update GPIO 32Jon Murphy
GPIO 32 was not allocated correctly, updating to reflect the native function use of the pin BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/herobrine: Add trackpad initializationRavi Kumar Bokka
Initialize trackpad on Qualcomm reference boards BUG=b:182963902,b:223826899 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I93e866d92cf37887a98de88b4b2d768562515670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/guybrush: Enable DEBUG_SMI for non-serial firmwareRaul E Rangel
In order to copy the PSP verstage logs into x86 cbmem, we need to enable DEBUG_SMI. This will include the CBMEM console code in SMM. I only enable DEBUG_SMI when UART is disabled because SMM doesn't currently save/restore the UART registers. This will result in clearing the interrupt enable bits and makes it so you can no longer use the TTY. BUG=b:221231786, b:217968734 BRANCH=guybrush TEST=Build serial and non serial firmware and verify DEBUG_SMI is set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmemRaul E Rangel
Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10cpu/x86/smm: Add weak SoC init and exit methodsRaul E Rangel
This change provides hooks for the SoC so it can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10mb/google/guybrush/var/nipperkin: turn off WWAN DPRKevin Chiu
Sets GPIO 42 to high to turn off WWAN DPR BUG=b:216735313 BRANCH=guybrush TEST=emerge-guybrush coreboot make sure GPIO42 is high Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10soc/mediatek/mt8195: Enable PCIe supportJianjun Wang
Enable PCIe support for mt8195. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10soc/mediatek/mt8195: Add driver to configure PCIeJianjun Wang
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10spd/lp5: Add new part MT62F2G32D8DR-031Amanda Huang
Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10soc/amd/cezanne/psp_verstage: Log the platform boot mode reportKarthikeyan Ramasubramanian
Log the platform boot mode reported by PSP verstage to PSP stage 1 bootloader. This helps to improve the debuggability. BUG=b:193050286 TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot mode is logged in the verstage logs. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I752ee56f2af48215a770d799432d02f0609757cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-10mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRMKarthikeyan Ramasubramanian
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2. But it is programmed incorrectly in the concerned ACPI device. Pass the correct GPIO. BUG=b:204401306 TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object contains the right GPIO. Ensure that the screen visibility gets updated by pressing the privacy screen button. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10soc/intel/adl: Send EOP early in the boot sequenceMAULIK V VAGHELA
As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-10intel/common/block/cse: Add option to send EOP early via SoCMAULIK V VAGHELA
Earlier while trying to optimize boot time End Of Post (EOP) time kept increasing (~80 ms) when boot time decreased to around 1 second. This was because CSE was busy with own firmware loading. When EOP was moved later in boot stage it again created issue since CSE got busy with other payload loading for OS boot, so response to EOP got delayed by ~70-80 ms. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board. Since this setting might vary for each SoC, SoCs can decide when to send EOP in the boot sequence. This patch adds Kconfig option to send EOP via SoC BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Code compilation is fine for Brya board. Boot time test is done using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms. Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>