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2021-05-03util/sconfig: Add support for discontiguous FW_CONFIG fieldsTim Wawrzynczak
Sooner or later, some board was going to need extra FW_CONFIG bits for a field that was already in production, so this patch adds support for adding extra (unused) bits to a field. The extra are appended via a syntax like: `field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...` and the suffixed bits are all treated as if they are contiguous when defining option values. BUG=b:185190978 TEST=Modified volteer fw_config to the following: field AUDIO 8 10 | 29 29 | 31 31 option NONE 0 option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 option MAX98360_ALC5682I_I2S 5 option RT1011_ALC5682I_I2S 6 option AUDIO_FOO 7 option AUDIO_BAR 8 option AUDIO_QUUX 9 option AUDIO_BLAH1 10 option AUDIO_BLAH2 15 option AUDIO_BLAH3 16 option AUDIO_BLAH4 31 end which yielded (in static_fw_config.h): FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700 Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747 Reviewed-by: Duncan Laurie <duncan@iceblink.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03nb/intel/common: Replace `_bar_clrsetbits_impl` macroAngel Pons
This macro contains a cast on the and-mask, which can suppress actual type overflow issues. Replace it with wrapper functions around the existing macros in device/mmio.h which still contain a type cast, but it is a non-issue because the wrapper functions now allow compilers to check for overflows. Change-Id: I975bf8152fc961767f0292bff4a03aecd8c65f56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51886 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03nb/intel/common: Drop deprecated fixed BAR accessorsAngel Pons
Now that all code has been switched to make use of the new accessors, the old ones can be dropped. Follow-ups will clean up bitwise accessors. Change-Id: Ib4cb24ca71f3c3717ea50d147ddca74aaf0288fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-03nb/intel/haswell: Move PEG registers to a separate headerAngel Pons
To keep the "main" haswell.h header short and simple, move PEG register definitions into a separate file, as done with most other registers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ibfca00456115a4a0c861dd6738605214a7d43fd9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51891 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02nb/intel/common: Turn `*bar_{read,write}*` macros into functionsAngel Pons
These accessors were defined as macros in order to allow verifying the patches that replaced the accessors using BUILD_TIMELESS=1. Now that all replacement is done, turn the new accessors into static functions to let the compiler perform overflow checks on the arguments. Change-Id: Iaa2ba208fba11c4a00f2b8a05eb1129a32c6c092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52816 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02nb/intel/haswell: Uniformize include guardsAngel Pons
Remove leading and trailing underscores and change `RAMINIT_H` to be more consistent with other headers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02nb/intel/haswell: Clean up haswell.h headerAngel Pons
Drop unused chipset type macros, remove unnecessary guards and reorganize contents so that headers can be included at the top. Also drop the inclusion from ASL, as it is no longer necessary. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I6fcc0d428d0fdbf410bcbeb6ae4809870b7b498f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51889 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequencyWerner Zeh
All the boards in the patch have a constraint for the I2C bus to operate on 100 kHz. Provide dedicated values for rise time, fall time and data hold time on mainboard level to get a proper timing which takes the bus load into account. Giving these values the driver computes the needed timings correctly. TEST=Measure I2C frequency on all boards while coreboot accesses external RTC and make sure it is 100 kHz. Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02mb/google/dedede/var/magolor: Support VBT for MagisterDavid Wu
Default VBT supports only integrated Display port. Magister supports a HDMI port and hence support a separate VBT for Magister. BUG=b:180666608 BRANCH=dedede TEST=Build and boot to OS. Cq-Depend: chrome-internal:3661227 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I52c10452887312959f68cfc4e25d5897dae388f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51279 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02soc/intel/cannonlake/include: Drop unused codeFelix Singer
`soc_vtd_resources` from the else-part is unused since Cannon Lake was removed. Thus, drop it and that if-else-condition. Change-Id: I21689d1eae6952a80c98096443e7506a1466c07e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-02soc/intel/skylake: Remove useless help textsFelix Singer
Remove useless help texts since they don't add any more value. Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02soc/intel/cannonlake: Remove useless help textsFelix Singer
Remove useless help texts since they don't add any more value. Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52777 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02soc/amd/cezanne: add verstage filesKangheui Won
Add support for psp_verstage compilation. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-02vendorcode: add code for cezanne psp_verstageKangheui Won
These are mostly copied from picasso code with exception for bl_syscall_public.h. For some SVCs svc number and/or prototype has been changed. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-01soc/intel/skylake: Add Kconfig option for LGA1151v2Timofey Komarov
Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 4) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 5) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-01soc/intel/skylake: Add microcodes for Coffee Lake CPUsTimofey Komarov
The Z370, H310C and B365 PCHs use the same silicon as 200-series PCHs and they are supported by soc/intel/skylake codebase (not by soc/intel/cannonlake). Mentioned PCHs are meant to be paired with Coffee Lake CPUs, so add the corresponding microcodes. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-30mb/google/brya: select GOOGLE_SMBIOS_MAINBOARD_VERSIONZhuohao Lee
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:186721096 TEST=1. emerge-brya coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Change-Id: I8eeb958f73607afb801794f91fbf91ec7bd5cd8b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-30drivers/i2c/designware: Use safe defaults for SCL parametersKyösti Mälkki
Inspired by discussion in CB:22822. If I2C bus step response has not been measured, assume the layout to have been designed with a minimal capacitance and SCL rise and fall times of 0 ns. The calculations will add the required amount of reference clocks for the host to drive SCL high or low, such that the maximum bus frequency specification is met. Change-Id: Icbafae22c83ffbc16c179fb5412fb4fd6b70813a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52723 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/mancomb: Add SPI configuration to KconfigMartin Roth
Mancomb will have the boot flash on a daughterboard, so the SPI speeds need to be low for now. BUG=b:182211161 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icacb68d65fb414197d7b8d45799527d8d2568dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/guybrush: Remove the GPIO_SIGN_OF_LIFE codeMartin Roth
Guybrush is pretty definitely alive, so this can be removed, as the TODO line said. BUG=180721202 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/mancomb: Remove lid swtichIvy Jian
There is no lid switch in mancomb so remove it. Will replace the lid switch with a fake gpio in depthcharge. BUG=b:182211161 TEST=Depthcharge no longer halts complaining that coreboot didn't sample the pin Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-30amdfwtool: Cleanup the message of helpZheng Bao
1. Wrap the long lines. 2. Align the message. 3. Add new SOC name, Cezanne. 4. Fix the cases. Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-30soc/amd/common: Move external oscillator config away from commonKarthikeyan Ramasubramanian
The usage of external oscillator has got nothing to do with Audio Co-processor (ACP). Hence move it out of common config and put it into the SoC config where it is being used. BUG=None TEST=Build Dalboz and Vilboz mainboards. Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-30mb/google/guybrush: update the telemetry settingChris Wang
Update the telemetry setting for guybrush vddcrvddfull_scale_current : 92165 #mA ddcrvddoffset : 412 vddcrsocfull_scale_current : 30233 #mA vddcrsocoffset : 457 BUG=b:182754399 TEST=Build, boot to guybrush Change-Id: Ib92bb169693634665fc8e165837e7ae3e6137bcf Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52736 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30amd/cezanne: Add telemetry setting to UPDChris Wang
Add telemetry setting to UPD, the value comes from the SDLE testing. BUG=b:182754399 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3787638 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/mancomb: Add STAPM values to overridetreeChris Wang
Follow the FP6 IRM(#56328) to set the stapm parameter and allow other mancomb variants boards can customize those parameters. BUG=b:1181157669 TEST=build. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-30Makefile,tests: Move cmocka checkout into top level MakefileRaul E Rangel
cmocka is currently ignoring the UPDATED_SUBMODULES flag. Move the cmocka checkout with the other submodule checkouts. BUG=none TEST=Make sure cmocka is not checked out if UPDATED_SUBMODULES=1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a1db809368a77d2c0f9c9a796d62555ec476dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-04-30ACPI: Use acpigen for NVS OperationRegionsKyösti Mälkki
The intermediate base and length are not required in ASL. Change-Id: I0c72e2e4f7ec597adc16dbdec1fd7bbe4e41bfd6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51637 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google: Move ECFW_RW setting for non-ChromeEC boardsKyösti Mälkki
The boolean is stored in ChromeOS NVS, not GNVS. Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-30vc/google/chromeos: Refactor GNVS initKyösti Mälkki
Move the support code for filling ChromeOS GNVS from acpi/chromeos-gnvs.c to vc/google/chromeos/gnvs.c. Change-Id: I7e92206561812eb3dc69739df49b6c3a93853858 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50612 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30soc/mediatek/mt8192: devapc: Add ADSP domain settingTinghan Shen
Configure ADSP domain from 0 to 4 and lock it to prevent changing it unexpectedly. TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Ib938ba05e8d0342572c57366c97ebb0185da8aba Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52728 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/dedede/var/galith: Support Wifi SAR for DVT phaseFrankChu
Because galith/gallop both non-suport tablet mode, remove un-use fw_config conditional. BUG=b:176206495 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic9bb76c207ef033f81ecdd57849535b8ac8d13ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/52565 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30drivers/intel/gma/Kconfig: Simplify CFL/WHL/CML conditionsAngel Pons
Change-Id: Id56761b2a57754b8f8d726a4bd2674ffa6fd1159 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-30cpu/x86/msr: introduce helpers msr_read, msr_writeMichael Niewöhner
The existing helpers for reading/writing MSRs (rdmsr, wrmsr) require use of the struct `msr_t`, which splits the MSR value into two 32 bit parts. In many cases, where simple 32 bit or 64 bit values are written, this bloats the code by unnecessarly having to use that struct. Thus, introduce the helpers `msr_read` and `msr_write`, which take or return `uint64_t` values, so the code condenses to a single line or two, without having to deal with `msr_t`. Example 1: ~~~ msr_t msr = { .lo = read32((void *)(uintptr_t)0xfed30880), .hi = 0, }; msr.lo |= 1; wrmsr(0x123, msr); ~~~ becomes ~~~ uint32_t foo = read32((void *)(uintptr_t)0xfed30880); msr_write(0x123, foo | 1) ~~~ Example 2: ~~~ msr_t msr = rdmsr(0xff); uint64_t msr_val = (msr.hi << 32) | msr.lo; ~~~ becomes ~~~ uint64_t msr_val = msr_read(0xff); ~~~ Change-Id: I27333a4bdfe3c8cebfe49a16a4f1a066f558c4ce Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52548 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBIEric Lai
Brya uses CBI to store dram part number. So enable the config. BUG=b:186571840 BRANCH=none TEST=dmidecode -t 17 can show the dram part number. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-30src/acpi: Add APEI EINJ supportRocky Phagura
This adds full EINJ support with trigger action tables. The actual error injection functionality is HW specific. Therefore, HW specific code should call acpi_create_einj with an address where action table resides. The default params of the action table are filled out by the common code. Control is then returned back to the caller to modify or override default parameters. If no changes are needed, caller can simply add the acpi table. At runtime, FW is responsible for filling out the action table with the proper entries. The action table memory is shared between FW and OS. This memory should be marked as reserved in E820 table. Tested on Deltalake mainboard. Boot to OS, load the EINJ driver ( modprobe EINJ) and verify EINJ memory entries are in /proc/iomem. Further tested by injecting errors via the APEI file nodes. More information on error injection can be referenced in the latest ACPI spec. Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rocky Phagura
2021-04-29mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOsFrancois Toguo
This CL configures TCSS, BT and WiFi related GPIOs based on schematics. BUG=None TEST= BT, WIFI and TCSS functionalities validated with this change. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/volteer/variants/copano: Modify touchpad I2C sequenceHao Chou
Modify touchpad I2C sequence to meet requirement. BUG=b:186372071 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the touchpad I2C5 sequence by EE. Change-Id: I9d4dcc764edfbdc14eef5ad82db20e40b31de295 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52690 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/volteer/variant/lindar: Modify ELAN touch screen IRQ trigger methodKevin Chang
According to SED team provided ELAN touch screen SPEC. IRQ trigger method need set with level trigger, that modify IRQ trigger to level from edge. BUG=b:174972088 TEST=Build FW and boot to OS and check with test result. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I9237d9aad6166a5754afe464ce8453129a58d283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-29soc/amd/common: Remove eSPI decode workaroundRaul E Rangel
We no longer lock up if we clear the port 80 bit. I'm assuming this was fixed when we configured the PSP to no longer setup eSPI. BUG=b:183974365 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29mb/google/guybrush,mancomb: only print warning in mainboard_smi_gpiFelix Held
guybrush and mancomb don't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/google/zork/smihandler: only print warning in mainboard_smi_gpiFelix Held
zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29psp_verstage: make temp_stack optionalKangheui Won
Temp stack for verstage is only needed for picasso, so make it optional in the layout file. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I44196103a3531e9d01c96ab8f454c8b580fe9807 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29psp_verstage: make get_max_workbuf_size optionalKangheui Won
From cezanne we have enough space in PSP so we don't have to worry about workbuf size. Hence the function only exists in picasso and deprecated for later platforms. So wrap svc_get_max_workbuf_size and provide default weak function so future platforms don't have to implement dumb function for it. TEST=build and boot zork, check weak function is not called in zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I16e8edf8070aaacb3a6a6a8adc92b44a230c3139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29soc/amd/picasso: move PSP_SRAM addrs to separate headerKangheui Won
These addresses will be changed in cezanne. Before start working on cezanne, move these out to separate header as a clean-up. TEST=emerge-zork coreboot Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29mb/google/guybrush: Configure Audio Co-processorKarthikeyan Ramasubramanian
Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix the scope in which ACP is defined in the devicetree. BUG=b:182960979 TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is enabled in the appropriate scope in SSDT. Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/cezanne: Enable Audio Co-processor driverKarthikeyan Ramasubramanian
BUG=b:182960979 TEST=Build and boot to OS in Guybrush. Change-Id: I73d1d3e5c1c4eb30ebf44f38d381beba84075351 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29mb/google/guybrush: Set system_config to 2 for guybrush boardsMartin Roth
All guybrush boards should have system_configuration set to 2, so put this in the main devicetree. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: chris wang <Chris.Wang@amd.com>
2021-04-29cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OSTim Wawrzynczak
Some platforms which have large amounts of RAM and also write-combining regions may decide to drop the WC regions in favor of the default when preserving MTRRs for the OS. From a data safety perspective, this is safe to do, but if, say, the graphics framebuffer is the region that is changed from WC to UC/WB, then the performance of writing to the framebuffer will decrease dramatically. Modern OSes typically use Page Attribute Tables (PAT) to determine the cacheability on a page level and usually do not touch the MTRRs. Thus, it is believed to be safe to stop reserving MTRRs for the OS, in general; PentiumII is the exception here in that OSes that still support that may still require MTRRs to be available. In any case, if the OS wants to reprogram all of the MTRRs, it is of course still free to do so (after consulting the e820 table). BUG=b:185452338 TEST=Verify MTRR programming on a brya (where `sa_add_dram_resources` was faked to think it had 32 GiB of DRAM installed) and variable MTRR map includes a WC entry for the framebuffer (and all the RAM): MTRR: default type WB/UC MTRR counts: 13/9. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x00003fff80000000 type 6 MTRR: 1 base 0x0000000077000000 mask 0x00003fffff000000 type 0 MTRR: 2 base 0x0000000078000000 mask 0x00003ffff8000000 type 0 MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x00003fff00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x00003ffe00000000 type 6 MTRR: 6 base 0x0000000400000000 mask 0x00003ffc00000000 type 6 MTRR: 7 base 0x0000000800000000 mask 0x00003fff80000000 type 6 MTRR: 8 base 0x000000087fc00000 mask 0x00003fffffc00000 type 0 ADL has 9 variable-range MTRRs, previously 8 of them were used, and there was no separate entry for the framebuffer, thus leaving the default MTRR in place of uncached. Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-29mb/google/asurada: Fix power on delayYu-Ping Wu
From ANX7625 spec, the delay between powering on power supplies and GPIO should be larger than 10ms. Since it takes about 4ms for the previous GPIO EN_PP3300_EDP_DX to be pulled up, increase the delay from 2ms to 14ms. BUG=b:157716104 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: If73747bdaec5ac069b048920d27e27178bc3cedc Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-29ec/lenovo/h8/h8.c: Skip setting volume if out of rangeAngel Pons
This change is needed to update the option API to use unsigned integers. The CMOS option system does not support negative numbers. The volume field is only 8 bits long. Do not set the volume if it is out of range. Also, use an out-of-range value as fallback to skip setting the volume when it cannot be read using the option API, to preserve the current behavior. Change-Id: I7af68bb5c1ecd4489ab4b826b9a5e7999c77b1ff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-29mb/google/brya: Enable ELAN9050 touchscreenEric Lai
Enable ELAN9050 touch screen. Follow below spec: eKTH7913U_eKTH7915U_eKTH7918U_Product Spec_V1.0_20200807 IPM-11 BUG=b:186342801 TEST=touchscreen is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I4c247fae33b9178c8706552aba2f950c9a674ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29mb/google/brya: Adjust WWAN power sequenceEric Lai
Follow L850GL spec to adjust power sequence. RST need to drive low before power on then drive to high. SPEC:FIBOCOM_L850-GL Hardware User Manual_V1.0.8 BUG=b:186374631 TEST=WWAN is detected by lsusb. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I13357677bb1ab185abf1d4c915a762a9d6894312 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29chromeec: Fix google_chromeec_status_check timeoutRob Barnes
Rewrite google_chromeec_status_check to use stopwatch instead of a delay in a while loop. In practice the while loop ends up taking much longer than one second to timeout. Using stopwatch library will accurately timeout after one second. BUG=b:183524609 TEST=Build and run on guybrush BRANCH=None Change-Id: I363ff7453bcf81581884f92797629a6f96d42580 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29docs/mb/supermicro/x11ssm-f: rework flashing sectionMichael Niewöhner
The board can be flashed without adding a diode by just leaving VCC unconnected. Rework the flashing section to describes that. Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29migrate out of flashrom deprecated optionsDaniel Campello
This change replaces --diff and --fast-verify for the supported equivalent flashrom options Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I8c48c7f819f968c3ddd94278415e5e9e0ef93924 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-04-28mb/google/volteer: Add EC_HOST_EVENT_USB_MUXJohn Zhao
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source. BUG=b:183140386 TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC synchronized. AP got port partner disconnection. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I53bd4fee21e2e2d1f16f558ab0341a50ef9a0e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52716 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28.gitmodules: update vboot submodule to track branch=mainBalaji Manigandan B
vboot has been updated to track main branch, however the .gitmodules defaults to master branch following the coreboot default. This impacts the rebase of submodule git submodule update --remote --rebase 3rdparty/vboot/ With this change the rebase to latest commit is successful Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Change-Id: I7713aecdec43a5d5623ef81803ac0fc02ce14070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52664 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel/common/block/hda: Use azalia device codePatrick Rudolph
The code is already compiled in on all platforms. Use it as it provides the same functionality. Note that GCAP is no longer R/WO on these platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case. This will be dropped in a follow-up. Tested on Prodrive Hermes, still detects and initializes both codecs. Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVPAnil Kumar
This patch adds UART0 config in early GPIO table Branch=None Test=Build coreboot and boot on ADLRVP-M board. Check UART logs Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/amd/common/smi_handler: Print warning when receiving an SCI SMIRaul E Rangel
We don't have any infrastructure setup to handle SCI SMIs. Instead of just silently ignoring the SMI, print a warning saying that it is being ignored. BUG=none TEST=Trigger an SCI SMI and see warning printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I803e572250925b7d5ffdbb3e8958f9aff1f808df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28superio/nuvoton/npcd378: Fall back to non-negative valueAngel Pons
This change is needed to update the option API to use unsigned integers. The CMOS option system does not support negative numbers. So, adjust the call to get_int_option() to use 3 as fallback instead of -1. Change-Id: I46c5f5c6f47f99379cbafc0d60258b99dc512e9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-28mb/dell/optiplex_9010: Always log chosen fan modeAngel Pons
Always print the chosen fan mode, not only when get_int_option() returns the fallback value. Callers of get_int_option() should not try to handle option-related errors, and simply proceed using the fallback value. This change is needed to update the option API to use unsigned integers. The CMOS option system does not support negative numbers. Change-Id: Ic8adbe557b48a46f785d82fddb16383678705e87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-28soc/amd/cezanne: copy psp_transfer.h from picassoKangheui Won
Cezanne version of psp_transfer.h lacks some necessary definitions. Currently we don't have any plan to change transfer buffer structure in cezanne, so just copy'em over. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I9361c4ab76c8ded06358a7718d5e447c16414721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52540 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/amd/cezanne: copy Kconfig options for psp_verstageKangheui Won
These are just copied from picasso one. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I701d6af63b24e86f8e132fad73504e20148a2bf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-28mb/google/dedede/var/metaknight: Define stop_gpio for goodix touch screenDavid Wu
Define TOUCH_RPT_EN pin(GPP_A11) as the stop_gpio for the touch screen and control TOUCH_RPT_EN pin to keep low. BUG=b:176253069 TEST=Build and boot metaknight to OS, confirm GPP_A11 pin keep low. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I816e29eccac0f1935aeaa3b94c907870e2451e3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52653 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28drivers/intel/gma/Kconfig: Simplify Skylake/Kaby Lake conditionsAngel Pons
Use `SOC_INTEL_COMMON_SKYLAKE_BASE` to simplify conditions. Change-Id: Ie69bde31b58bbd973db00bd578a51477c5b21cab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel/skylake: Shorten report_platform PCH-H namesAngel Pons
For brevity's sake, just print the PCH model. Change-Id: Ib9e96683e3cb0b63a11344f3b5383292bff88e13 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52701 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel/skylake: Drop Lewisburg PCHs from report_platformAngel Pons
These PCHs are used with Xeon-SP processors, which use different code. Change-Id: I05f67cd57aa9f867e2fab88cd49e0384073a0b20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52699 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/google/brya: remove WLAN PCIE settingEric Lai
Brya uses CNVi WiFi module, PCIE setting is not required. TEST=WiFi is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28mb/asus/p5q: Document working fan control and FireWire portStefan Ott
Fan control and FireWire work fine on my board. Signed-off-by: Stefan Ott <stefan@ott.net> Change-Id: Idc69e902370c4094daef93e843abc6ae564625f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-28mb/amd/majolica:Set IRQ for GPIO controllerJason Glenesk
AMD GPIO driver will not load if IRQ is not set. As a consequence, it does not clear the interrupt when waking from S0i3. BUG=178728116 TEST=Perform 2 S0i3 cycles, confirming second cycle does not return instantly due to first interrupt not being cleared. Change-Id: I3072263e8e68f939a47ed4125444c60133087824 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-28mb/prodrive/hermes: Drop Vref configuration for older boardsPatrick Rudolph
Drop Vref verbs from the baseboard table as it's not required for Rev. 3 and earlier. Change-Id: I41c207f97dad6c9107c1999eb46d2d6304a6c217 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-28soc/mediatek/mt8195: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/mediatek: Move the common part of PMIC drivers to common/Yidi Lin
The PMIC drivers can be shared by MT8192 and MT8195. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie17e01d25405b1e5119d9c70c5f7afb915daf80b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-27mb/google/guybrush: Fix EC SCI configurationRaul E Rangel
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. BUG=b:186045622, b:181139095 TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I764b9ec202376d5124331a320767cbf79371dc07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-27sb/intel/common: Refactor _PRT generation to support GSI-based tablesTim Wawrzynczak
Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-27vc/amd/agesa/f15tn/Config/PlatformInstall.h: enable the AMD CPB featureMike Banon
Enable the AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) feature [1] for f15tn boards - like it's already done for f14 and f16kb. According to CB:51394 [2] it improves the performance of Lenovo G505S by up to 50%, and is unlikely to cause regressions for the other boards. [1] https://en.wikipedia.org/wiki/AMD_Turbo_Core [2] https://review.coreboot.org/c/coreboot/+/51394 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1eaa8ff3953c492e8f9431d7b4a09b86e0ef77a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-26MAINTAINERS: Add myself as reviewer for some boards that I ownStefan Ott
I have a Lenovo X200, a Lenovo X201 and an Asus P5Q. Signed-off-by: Stefan Ott <coreboot@desire.ch> Change-Id: I9577a848cb799fca237487fc20d6aa9135599f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/volteer/variant/lindar: Disable acoustic mitigationKevin Chang
Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2" Because baseboard modify slow slew rate setting to "SLEW_FASE_8" for all project, but Lindar and Lillipup is using "SLEW_FAST_2", so this setting need to roll back. BUG=b:186140230 TEST=Build FW and boot to OS checking with CPU log. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/guybrush: Add STAPM values to overridetreeMartin Roth
This enables STAPM power management. Values follow the AMD specification. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib9f2ec9a8ac118c55ae53b9419ea4ff74ce7b599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26soc/amd/cezanne: Update STAPM vars with unitsMartin Roth
Like the Picasso platform, it's very useful to have units on these variables. BUG=b:185209734 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I592c807c5e9a2c17b1c5959e56a01237352c5204 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth
These values will be added in the upcoming STAPM configuration update. BUG=b:185209734 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3780259 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26mb/system76/oryp6: Add System76 Oryx Pro 6Tim Crawford
https://tech-docs.system76.com/models/oryp6/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe - M.2 SATA - MicroSD card slot - All USB ports - Integrated graphics using Intel GOP driver - Webcam - Ethernet - Internal microphone - Combined headphone + mic 3.5mm jack - Combined microphone + S/PDIF 3.5mm jack - Booting to Ubuntu Linux 20.10 and Windows 10 - Flashing with flashrom Not working: - S3 suspend/resume: System hangs on wake from S3 - Discrete/Hybrid graphics: Requires a new driver - Internal speakers: Enabled in separate patch Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/hp/snb_ivb_laptops: Do not set EC SLPT on S5Iru Cai
Linux kernel now uses S5 for reboot, which makes reboot fail if EC SLPT bit is set. Tested on HP EliteBook 2560p, reboot and S3 resume work after this change. Change-Id: I9b3ea737f85cc4045714263657bcdaac08f3a20d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26mb/**/cmos.layout: Drop unreferenced `iommu` optionAngel Pons
No code in coreboot uses this option, so it might as well be dropped. Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mainboard: Drop unreferenced CMOS optionsAngel Pons
Remove CMOS options that are not read anywhere in the code. They may have been used in the native AMD platform code, or got copied around from board to board and never did anything to begin with. Change-Id: Ib19ace4fa6e610a28e68fe2612b4e623f200f064 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52638 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Remove elog.cTan, Lean Sheng
Remove elog.c from EHL soc as EHL does not support chromebook and hence does not need it. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h. GPIO communities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel EHL PCH Datasheet with Document number 614109 and Chapter 21. Also update GPIO COM3 Port ID and 2 GPIO register values (HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-04-26mb/google/mancomb: Add mancomb APCBs into buildIvy Jian
This adds the Mancomb APCBs into the AMD firmware binary. BUG=b:182211161 TEST=Build and check log showing APCB sources present. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ifdf1e813fce6f93378c2495cf76bdace81d87c16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52600 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26src/soc/amd/picasso: Add HDMI 2.0 disable settingPatrick Huang
hdmi2_disable bit0~3 is used to disable HDMI 2.0 function in DDI0~3 BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I383bfd04e01f5202db093105662344869e475746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26src/vendorcode/amd/fsp/picasso: Add HDMI 2.0 Disable setting section of ↵Patrick Huang
FspmUpd.h This change adds HDMI 2.0 Disable setting BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Ie00389074f3718a23440c41ae0b116455aa8b603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26mb/google/mancomb: PCIe GPIOs - enable enables, disable resetsIvy Jian
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-26mb/google/volteer/variant/lindar: Create dynamic fan table mechanismKevin Chang
Add dynamic fan table mechanism for Lindar and Lillipup. Create different fan tables that provided from thermal team. BUG=b:185308432 TEST=Build FW and boot to OS modify CBI test with DPTF tool. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-26mb/google/guybrush: Enable S0i3Karthikeyan Ramasubramanian
BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>