summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-11-27 Make xcompile support multiple architecturesRonald G. Minnich
With this change the the xcompile script now creates environment variables for more than one architecture. Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Change-Id: I349a1fd1d865ef16979f1dfd6aeca12b1ee2eed6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1915 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-27Conditionally #include mc1468181rtc if CMOS_POST is enabledDavid Hendricks
This will omit the mc1468181rtc header if it is not needed. Currently it contains a lot of inlined functions which depend on architecture- specific IO. Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1916 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-27Make POST codes written to IO port optionalDavid Hendricks
This adds more configurability to POST codes. The current assumption is that POST codes should be written to an IO port (e.g. LPC) if POST codes are enabled. This changes the assumption so that POST codes can be written to the serial console without being written to an IO port. This enables POST codes by default using "default y" to avoid changing current behavior. Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1685 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24Remove duplicate VGA BIOS interrupt handlersPatrick Georgi
Some boards have two instances of the int15 handler that supports the onboard VGA BIOS, for YABEL and realmode. These are now similar enough that they can be deduplicated. Due to minor differences this requires manual effort. Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
Makes it more similar to what realmode looks like. Change-Id: I4407431f2d979c43dd186114d67ed11845907afe Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Use x86emu register file + definesPatrick Georgi
By using the (global) register file as defined by x86emu, we can use the same register access for YABEL and realmode interrupt handlers. - the x86 realmode interrupt handlers changed in signature - to access registers, use X86_$REGNAME now (eg. X86_EAX) - x86_exception_handler still uses struct eregs *regs to avoid spilling the x86emu register file stuff everywhere Coccinelle script that handled most of this commit: @ inthandler @ identifier FUNC, regs; @@ int FUNC( -struct eregs *regs +void ) { ... } @ depends on inthandler @ identifier regs; @@ -regs->eax +X86_EAX @ depends on inthandler @ identifier regs; @@ -regs->ebx +X86_EBX @ depends on inthandler @ identifier regs; @@ -regs->ecx +X86_ECX @ depends on inthandler @ identifier regs; @@ -regs->edx +X86_EDX @ depends on inthandler @ identifier regs; @@ -regs->esi +X86_ESI @ depends on inthandler @ identifier regs; @@ -regs->edi +X86_EDI @ depends on inthandler @ identifier regs; @@ -regs->eflags +X86_EFLAGS @ depends on inthandler @ identifier regs; @@ -regs->vector +M.x86.intno Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Adapt to x86emu/YABEL style return codesPatrick Georgi
realmode int handlers must return the same codes as the YABEL int handlers now: 1 for "interrupt handled", 0 for "not handled" (ie. error). Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86emu: Move realmode handler into own directoryPatrick Georgi
It's really a feature in parallel to YABEL/x86emu. Reflect this in the directory structure. Change-Id: Ie88e4fa6bfef13d23c55b2db3faacbd90f8cc30b Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24crossgcc: update to acpica-20121114Idwer Vollering
Update acpica to release 20121114 and update patches/ to build with this version of acpica. Correct the creation of crossgcc-build.log Bump CROSSGCC_VERSION. Change-Id: I269454ebc3c78b5852e4a67e55bb5642edad191d Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/1861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24libpayload: Fix interrupt-queue cleanup for OHCINico Huber
We have to free TDs more carefully if they have been processed by the controller yet. The current code tries to force the controller to post them back to the done queue, but that seems wrong. We can't be sure, when they get written back. This resulted in leaking TDs with an invalid reference to a freed interrupt queue. The new approach: Mark the interrupt queue to be destroyed and handle the freeing later, when the controller posted the last TD to the done queue. Change-Id: I79d80a9dc89e1ca79dc125c4bbccbf23664227b3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24libpayload: Rework connection state detection for OHCINico Huber
The connection state detection in the OHCI root hub driver was broken if you used more than one device per root hub. Change-Id: Ica5c735426beac45ef6f591ce68a72d8283a00f5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1904 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24libpayload: Handle errors in UHCI interrupt queuesNico Huber
If somethings goes wrong during an interrupt transfer, drop the transfer. Change-Id: I450c08a7a0bf23fbee74237e0355d4a726ace114 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1901 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-24libpayload: Handle underruns in UHCI interrupt queuesNico Huber
If usb_poll() isn't called fast enough, the UHCI controller marks an underrun interrupt queue as done (terminating the queue at the head). We can recover from this situation, when usb_poll() gets called again, and the queue is processed. Change-Id: Id56c9df44d6dbd53cd30ad89dfb5bf5977799829 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1898 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-24libpayload: Implement correct interrupt-queue linking for UHCINico Huber
The linking of interrupt queues into UHCI controller's framelist (in uhci_create_intr_queue()) was incomplete. The implementation of uhci_destroy_intr_queue() was even worse, looking like it wanted to clean up more than uhci_create_intr_queue() did. This patch follows the simple approach that we used for OHCI and EHCI: Each slot in the framelist holds only one interrupt queue. Therefore, we have to look for free slots each time we want to link an interrupt queue into the framelist. In return, we have a much simpler structured framelist. With this, USB devices using interrupt transfers (e.g. keyboards) can be detached cleanly from UHCI controllers. Also, more than one of such devices can be attached without further risk. Change-Id: I07b81a3b6f2cb3ff69515c973b3ae6321ad969aa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1897 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-23libpayload: Make USB HID support multiple keyboardsNico Huber
The USB HID driver had some static variables with keyboard state. This moves them to the driver's instance, so multiple attached keyboards don't effect each other. Change-Id: I3f1ccfdea95062b443cebe510abf2f72fdeb1916 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1907 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: ehci: Prevent some race conditionsNico Huber
Prevent race conditions, when an interrupt-queue underrun occurred and the controller is currently working on our queue head or a transfer is still in progress. Change-Id: Ia14f80a08071306ee5d1349780be081bfacb206a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1902 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: Detach devices behind removed USB hubsNico Huber
When a USB hub got removed, we should also remove all devices that were attached to it. Change-Id: I73c0da1b7570f1af9726925ca222781b3d752557 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1903 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: More compliant error recovery in USB MSCNico Huber
If an endpoint gets stalled by an MSC device, after successful transmission of a command (CBW), we should still ask for the status (CSW). Otherwise, the driver and the device get desynchronized on the command tags. Change-Id: I53167f22c43b3a237cb4539b3affe37799378b93 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1900 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: Reduce error output from EHCINico Huber
Stalled transfers are not fatal, so don't spew on the console on every tiny failure. Change-Id: I175c1e83a6af09c1abbd43d045ed6dbf0c79f871 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1899 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: Fix random warningsNico Huber
dump_td() is orphaned but looks useful => commented out. The delay identifier shadowed the global one => renamed to total_delay. Change-Id: I4f3766a07db9194b2552ebf9302bd7ef8a66371f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1895 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: ehci: Fix warnings about discarded volatileNico Huber
We can trust free() and memset() to work correctly on volatile references, so cast volatile pointers to (void *) when calling them. Change-Id: Ieff7f78133b72f303349cca0a0ca3bbf37ec52bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1896 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-23libpayload: Fix some missing-prototype warningsNico Huber
usb_controller_initialize() is not declared in any header file nor called from outside of usbinit.c, so make it static. set_configuration() looks like beeing non-static on purpose (like the other helpers around it in usb.c), so put a prototype into usb.h. Change-Id: I08d93b3769d8398bb43462d9afdfeec81fef93ec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1894 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-23libpayload: Fix memalign() for fragmented alignment regionsNico Huber
Found a bug in the memory allocator ;-) If the total free space in an alignment region is large enough for an allocation but fragmented, such that there is no contiguous, sufficient large, free space in the region, memalign() was looking at the same region again and again in an endless loop. The advancing to the next region was just missing. Change-Id: I3fad833804675ee495577ca2749b007f46b5ff69 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1906 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-22crossgcc: properly test for flexPatrick Georgi
This is no GNU tool, so testing for "GNU" in the version string is bound to fail. We now accept everything that returns success on "flex --version" and then hope for the best. I tested both cases Change-Id: If325f613fde1648847b998b7e8e5782d0f22b484 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1884 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-20Persimmon: Disable the unused GPP PCIe clocksDave Frodin
Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-20Unify use of bool config variablesStefan Reinauer
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-20secondary.S: Fix dropping ramstage.aStefan Reinauer
This unused code was not silently dropped as before. Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1863 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20Make sure only one udelay function is availableStefan Reinauer
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions, so don't shove in UDELAY_IO Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1864 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-19siemens/sitemp_g1p1: Drop copy of cmos checksum calculationPatrick Georgi
This code used a special case for checksum calculation to prevent the century byte from messing things up, since writes "sometimes" didn't happen. That should be stable now, so the special case isn't necessary. Downside: On century rollovers (ie. 1999-12-31, 2099-12-31) CMOS will be reset to the defaults. Change-Id: Ibe589a1ec953b7b3ba39be30cebd9fc2b27326ae Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1870 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19bootblock: Guard CMOS rewrite in disable/enable RTCPatrick Georgi
This ensures that there's only one disable/enable cycle for the entire rewrite instead for every single byte. Change-Id: Ic06e6dcb08976d158ff784660838c0fbad875176 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1869 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19mc146818rtc: disable RTC before writing to nvramPatrick Georgi
In principle this isn't necessary. However there's a byte (or several) outside the first 14 bytes that are part of the RTC, and require locking (century/altCentury). Since their location is mostly unknown, guard writes properly. Change-Id: I847cd4efa92722e8504d29feaf7dbfa5c5244b4e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1868 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19Add nvramcuiPatrick Georgi
nvramcui is a small libpayload based utility that provides an interactive CMOS editor for pre-boot environments. Change-Id: I514b8a7682f89d242d1b31b6907cc6bff34da4bf Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1871 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19build system: use strip_quotes on cbfs-filesPatrick Georgi
If they come from the build system, file names might be guarded in quotes, which confuses make. Drop them here. Change-Id: Ice0d3c4bc2c45a3f121a85e1b9f5f6420c5761d5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-17Cleanup sconfigKyösti Mälkki
Fix side-effects of name translation, treat original name as const. Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17Drop no-op bootblock.cKyösti Mälkki
Deletes unused file: src/northbridge/amd/agesa/family15tn/bootblock.c Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17Use new system agent binariesStefan Reinauer
Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1879 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16buildgcc: Print error if flex is missingStefan Reinauer
flex is needed by acpica. This patch makes the build fail early instead of after gcc has been compiled, if flex is not there. Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1860 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Fix Kconfig GENERATE_*_TABLE usageStefan Reinauer
Some boards selected GENERATE_ instead of HAVE_ Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Clean up KconfigStefan Reinauer
- move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop Kconfig.deprecated_optionsStefan Reinauer
Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET are not likely to go away any time soon, so let's not keep them in Kconfig.deprecated_options but move them close to the code they control. Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1839 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop unused Kconfig variable PCIE_TUNINGStefan Reinauer
It's only mentioned in Kconfig and never set nor used. Change-Id: Icc0ac56ae7b325a9e93ed5cdce9dc4b7bab43140 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1838 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop Kconfig variable BOARD_HAS_HARD_RESETStefan Reinauer
hard_reset was indeed consolidated and moved into the southbridge code a while ago, but the config variable was still kept alife, with some duplicate code. Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Reduce number of per-mainboard changesStefan Reinauer
- Add mainboard_smi.c from arch/x86/Makefile if it's there - Add mainboard's chromeos.c from the chromeos Makefile Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1835 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-15libpayload: Always use virtual pointers in struct sysinfo_tNico Huber
We had mixed virtual and physical pointers in struct sysinfo_t. Some being virtual by accident which led to problems when we tried to reinitialize lib_sysinfo after relocating FILO (to get intentionally virtual pointers valid again). I guess this didn't cause much trouble before, as lib_get_sysinfo() was always called with physical addresses being equal to their virtual counterparts. For FILO, two possibilities seem practical: Either, have all pointers in struct sysinfo_t physical, so relocation doesn't hurt. Or, have all pointers virtual and call lib_get_sysinfo() again after relocation. This patch goes the latter way, changing the following pointers for situations where virtual pointers differ from physical: .extra_version .build .compile_time .compile_by .compile_host .compile_domain .compiler .linker .assembler .cb_version .vdat_addr .tstamp_table .cbmem_cons .mrc_cache We could also just correct the accidentally virtual pointers. But, IMO, this would lower the risk of future confusion. Note 1: Looks like .version gets never set. Note 2: .option_table and .framebuffer were virtual pointers but treated like physical ones. Even in FILO, this led to no problems as they were set before relocation. Change-Id: I4c456f56f049d9f8fc40e62520b1d8ec3dad48f8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-15libpayload: Use #ifdef for CONFIG_* checksNico Huber
Libpayload uses the linux kernel's config style, where CONFIG_* defines don't get written for unset tristates. Change-Id: I3f832cf86bca9a1e153d96af4bf6434a19eba2f6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1847 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14Use mainboard hook for HP DL165Kyösti Mälkki
The board incorrectly overrides the southbridge hook, so use the new mainboard hook instead. This change also activates the actual southbridge hook to enable decode of complete 4 MB flash memory region. Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14ms9652: fix misuse of LIFT_BSP_APIC_IDStefan Reinauer
It's a bool, not a number Change-Id: I70d52c6af6703101dbd534970ec65275902a283d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1842 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14mainboard/siemens/sitemp_g1p1: Fix YABEL usageNico Huber
The board was broken for use with CONFIG_PCI_OPTION_ROM_RUN_YABEL. Change-Id: Ia57d630143386fe637af83b9e7345d0d3750b089 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Make YABEL's version of mainboard_interrupt_handlers() usableNico Huber
YABEL's version of mainboard_interrupt_handlers() was hidden behind an inline stub. This fixes it. Change-Id: Ie53424a8ce074e93a720c0ef94cb39994cacd023 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14mainboard/siemens/sitemp_g1p1: Fix CMOS checksum algorithm here, tooNico Huber
Some time ago our CMOS checksum algorithm was changed under the topic: Fix our CMOS checksum algorithm so it matches what /dev/nvram expects Here is another copy of the algorithm that had to be updated. Change-Id: I58659c7b8a89c89c76efdff405ee0620e7302277 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14libpayload: Add init() function to hci_t and rework uhci_reset()Nico Huber
uhci_reset() differs in semantics compared to the other HCI's reset() implementations. uhci_reset() does some initialization work after a controller reset. So move the initialization part to a new function, uhci_reinit(), which get's exported through a new entry in hci_t: hci_t.init(). Warning: This breaks code that relies on the current, special, counterintuitive behaviour of uhci_reset(). If one wants a working host controller after calling hci_t.reset(), he should call hci_t.init() afterwards. Change-Id: Ia7ce80865d12d11157645ce251f77f349f8e3c34 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14libpayload: Do not call ohci_reset() from ohci_init()Nico Huber
When ohci_reset() was implemented, OHCI controllers stopped working since the stub ohci_reset() is called at the end of ohci_init(). This is fixed by removing the call. To prevent further problems the call to the xhci_reset() stub is removed, too. Change-Id: If89825c8e6caf40f7f4fe078e8b2e90054a54ba2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1850 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14libpayload: Free usb host controller instance after shutdownNico Huber
All shutdown() implementations but ehci_shutdown() free the hci_t structure. This seems correct and the reference to the hci_t shouldn't be used after shutdown(), so do it in ehci_shutdown(), too. Change-Id: Ie3506d769e73007735f3211710734a5f0107e43a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1849 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14libpayload: Document USB host controller setup functionsNico Huber
The semantics of the controller functions, start(), stop(), reset() and shutdown(), are not self-explanatory which let to some confusion. At least the reset() functions of the different host controller drivers were implemented following different interpretations. Let's make the intended behaviour of these functions clear. The stated inconsistencies will be addressed in following commits. Change-Id: Id2e300f65c21039218b6ba3f87c0fcd4f0dda0a8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1848 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14libpayload: Export device count in storage interfacePatrick Georgi
FILO can use this as offset to enumerate AHCI and its own IDE devices together. Change-Id: I57380e7bd1df6db5c882427e9a34d068f4348fb2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1846 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14nvramtool: fsync for mingw.Zheng Bao
Change-Id: Ifdec69ca46ba8cbd3eb154d8f4af4b3cafa8019d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-14Move HAVE_SMI_HANDLER from mainboards to chipsetsStefan Reinauer
Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14VIA chipsets: fix compilation without real mode codeStefan Reinauer
The VIA chipsets CX700, VT8623 and VX800 required to be configured with real mode option rom code enabled. This patch fixes the issue and drops some unneeded header files. Change-Id: I0d8a3f8f99c2eacec7666f08f85b99f09c06af84 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1833 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Tell CBMEM code about ACPI GNVS sectionStefan Reinauer
We moved GNVS to it's own section, but forgot to tell the cbmem code about it. This is purely cosmetical, but add it anyways. Change-Id: Icb3788c0325ea79cc1efff4a876412d07da7936e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1782 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Fix save state searching for GSMIDuncan Laurie
The search for save state was comparing the entire RAX value when it needs to just operate on the bottom byte so it can find the GSMI command in bits 7:0 but not the extended command code in bits 15:8. Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1774 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Save the GNVS pointer when creating APCI tablesDuncan Laurie
At boot time when the ACPI tables are created and the location of GNVS is determined then save that address for resume time. This also sets the values of USB charging in S3/S5 to the expected default values for Stout/Butterfly that were not set correctly. Change-Id: I9b94b868aa6e81aced06c0262cc2697ad4faf1e6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1768 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Pass the ACPI GNVS pointer via state save mapDuncan Laurie
Instead of hijacking some random memory addresses to relay the GNVS pointer to SMM we can use EBX register during the write to APM_CNT register when the SMI is triggered. Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1766 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
Using global variables with the TSEG is a bad idea because they are not relocated properly right now. Instead make the variables static and add accessor functions for the rest of SMM to use. At the same time drop the tcg/smi1 pointers as they are not setup or ever used. (the debug output is added back in a subsequent commit) Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1764 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Extract function for finding save state nodeDuncan Laurie
This is currently used by the ELOG GSMI interface but is a good way to pass data to SMM so move the current searching code to a separate function and make it a bit more versatile with the checks it does to find a match so it can be used in other situations. Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Restore GNVS pointer in the resume pathDuncan Laurie
The SMM GNVS pointer is normally updated only when the ACPI tables are created, which does not happen in the resume path. In order to restore this pointer it needs to be available at resume time. The method used to locate it at creation time cannot be used again as that magic signature is overwritten with the address itself. So a new CBMEM ID is added to store the 32bit address so it can be found again easily. A new function is defined to save this pointer in CBMEM which needs to be called when the ACPI tables are created in each mainboard when write_acpi_tables() is called. The cpu_index variable had to be renamed due to a conflict when cpu/cpu.h is added for the smm_setup_structures() prototype. Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
If the PEI System Agent doesn't run PCIe initialization, the PEG clock gating will not be setup. Add the PEG clock gating when pei_data->pcie_init is 0. Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
The IvyBridge reference code does some slow and extensive PCIe init that we do not need on Link. Hence, add a flag to disable/enable running that init code from coreboot. NMode was used during bringup. We'll switch the setting back to auto, to let MRC decide the right thing. Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
This will enable DDR3 1.35V support for memory training in the reference code. It requires the board to be setup for 1.35V with whatever board-specific GPIOs are available. Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14pei_data.h: Fix commentMarc Jones
I added a comment to the pei_data.h to remind users about how the OC pins are mapped. Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
Let memory initialization code use the coreboot romstage console. This simplifies the code and makes sure that all output is available in /sys/firmware/log. The pei_data structure is modified to allow passing the console output function pointer. Romstage console_tx_byte() is used for this purpose. Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add spinlock to serialize Intel microcode updatesStefan Reinauer
Updating microcode on several threads in a core at once can be harmful. Hence add a spinlock to make sure that does not happen. Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13cros: Inform U-Boot via fake gpio when VGA Option ROM is loadedBill Richardson
This prepares the way for vboot to inform coreboot when it needs the VGA Option ROM loaded. Coreboot can't always know when it's needed (with keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not). By the time we get to U-Boot, it's too late, so we need two extra bits - one for vboot to tell coreboot to load the Option ROM and another for coreboot to let vboot know it's been done. This change sets up the communication, but doesn't act on it just yet. Even with this CL we always load the VGA Option ROM, so there's nothing to test. There should be no user-visible change. Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/1822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Export optionrom status on Stumpy/LumpyVadim Bendebury
ChromeOS' top of the tree u-boot expects coreboot to export information about option ROM status (started/not started). Stumpy and Lumpy were left behind and are not exporting this information. This CL fixes the problem. Change-Id: Id90035bd76ab177e4fc269efc2b74f15f641c77d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Make EmeraldLake2 work againDuncan Laurie
Fix GPIO exporting for new Vboot for oprom-matters GPIO and to make the power button static. Change-Id: Ic042c428a1d43512228c686121fa057d876606e1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add method for delaying adding of timestampsStefan Reinauer
In hardwaremain() we can't add timestamps before we actually reinitialized the cbmem area. Hence we kept the timestamps in an array and added them later. This is ugly and intrusive and helped hiding a bug that prevented any timestamps to be logged in hardwaremain() when coming out of an S3 resume. The problem is solved by moving the logic to keep a few timestamps around into the timestamp code. This also gets rid of a lot of ugly ifdefs in hardwaremain.c Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1785 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add Kconfig option to lock/unlock ME firmware during buildStefan Reinauer
For reasons of security and testing we want to be able to enable/disable ME section locking through a config option. Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1798 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
- drop changelog and add license header instead - 80+ character fixes - make stacks array static because it's not used externally - rename copy_secondary_start_to_1m_below() Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
There are some function dependancies that didn't work when MAX_CPU was set to 1 and the build would fail. Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1819 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
This change allows us to figure out how much of the AP stacks we are using, as well as to catch any case of an AP overrunning its stack. Also, the stack is poisoned, which is a good way to catch programming errors -- code should never count on auto variables being zerod. The stack bases are recorded in a new array, stacks. At the end, when all APs are initialized, the stacks are walked and the lowest level of the stack that is reached is printed. Build and boot and look for output like this: CPU1: stack allocated from 00148000 to 00148ff4:\ lowest stack address was 00148c4c CPU2: stack allocated from 00147000 to 00147ff4:\ lowest stack address was 00147c4c CPU3: stack allocated from 00146000 to 00146ff4:\ lowest stack address was 00146c4c Note that we used only about 1K of stack, even though in this case we allocated 4K (and in the main branch, we allocate 32K!) Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1818 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13SandyBridge/IvyBridge: Add IFD and ME firmware automaticallyStefan Reinauer
Right now coreboot's build process produces images that are not booting on actual hardware because they are smaller than the actual flash device and also don't have an IFD nor an ME firmware in them. In order to produce bootable images, you needed a wrapper script / extra step until now. With this change, the resulting coreboot.rom is actually bootable. Change-Id: I82714069fb004d4badc41698747a704bd9fed4da Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1771 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12libpayload: Use EXTRA_CFLAGS for additional GCC optionsGabe Black
-CFLAGS = $(INCLUDES) -O2 -pipe -g +CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe Change-Id: Icb228d173312a974746e72b6bbae059103b837fc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1723 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12vboot: Add option to skip TPM resume on S3 resumeStefan Reinauer
Change-Id: Ie4a98cc8af0dbcf09c7ace79668949ace5938c12 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1752 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12mmio pci config: Remove register constraintsAaron Durbin
The currently encoded register constraints fails compilation for SMM code or any code that compiles with -fPIC. The reason is that the ebx register is used for GOT base register. I don't believe the comment eluding to register constraints for AMD processors still applies. Therefore remove mmio_conf.h, and use the mmio methods in io.h. Change-Id: I391e5c2088ebc760b3a6ed6c37b65bbecab40a5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/1801 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12cbfstool: Rework to use getopt style parametersStefan Reinauer
- Adding more and more optional and non-optional parameters bloated cbfstool and made the code hard to read with a lot of parsing in the actual cbfs handling functions. This change switches over to use getopt style options for everything but command and cbfs file name. - This allows us to simplify the coreboot Makefiles a bit - Also, add guards to include files - Fix some 80+ character lines - Add more detailed error reporting - Free memory we're allocating Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7 Reviewed-on: http://review.coreboot.org/1800 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
Change-Id: I9e57c5792409830895a1147799acab95d910a336 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12cbfstool: Update LZMA encoder to LZMA SDK 9.12Stefan Reinauer
This removes almost all C++ code (except the wrapper) Change-Id: I0f84070e3b6dc57c98d49a53150a140479b3221f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1799 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12romcc_io: add pci_or_configX functions.Aaron Durbin
Some of the modules use their own rolled pci_or_configX functions. Therefore, make them first class so everyone can use them without copying them. Change-Id: I9a4d3364c832548dbfe18139c27cce2d60c3316d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/1797 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12x86/Makefile.inc: Test if the strings are equal by single equal signZheng Bao
Double equal sign like "test a == b" works. It really does, except NetBSD. But I haven't found any clue in the manual for the command test about "==". Change-Id: I37254cfeb688fd1092f2e549d24f8eb270f02fd8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1817 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-12cbmem compilation needs to use the hardened toolchainVadim Bendebury
The appropriate compiler (provided by the build system) is used to ensure proper toolchain options are used. cbmem.c is being modified to suppress pointer to integer typecast warnings. Change-Id: Ibab2faacbd7bdfcf617ce9ea4296ebe7d7b64562 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1791 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12If cmos is invalid, always set the rtc date and timeStefan Reinauer
If cmos is invalid for any reason, always set the date and time before marking RTC valid. Change-Id: Ib9d154802f75221d58bf28ba9c813f2529904596 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1790 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Remove duplicate defines from mc146818rtc.cMarc Jones
Remove the duplicate #defines and use what is set in mc146818rtc.h. Change-Id: Ic471e03c68b591d19c0646fdbea78374af11c8b8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1789 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
The MRC cache code, as implemented, in some cases uses configuration settings for MRC cache region, and in some cases - the values read from FMAP. These do not necessarily match, the code should use FMAP across the board. This change also refactors mrccache.c to limit number of iterations through the cache area and number of fmap area searches. Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1788 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
Adding an entry for 0x306a0 will make sure that all CPUs with CPUIDs 0x306aX will execute the driver (analog to Sandybridge behavior) Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Store timestamps before resuming from suspendStefan Reinauer
in the resume case, timestamps were collected in RAM stage but not stored in CBMEM. This leads to only a single time stamp covering 200ms being available for all of ram stage. Change-Id: Ibf0bb92caf5e032c12fe4e1b9b84b3624d499511 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Reduce default stack size to 4KStefan Reinauer
coreboot uses about 2K of stack on the BSP, and about 1K of stack on the APs. No reason to use an overdimensonal stack of 32k per core/thread. Change-Id: I734c240b992d40e1e35db3df5437c36da0a755cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1780 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>