summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2011-08-04northbridge/intel/i440bx: Registered SDRAM modules support and fixesKeith Hui
Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD; also drops an unneeded intermediate variable used in setting them. Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under Linux and memtest86+. Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04libpayload: Add liblzma, libcbfsPatrick Georgi
Add cbfs core from coreboot into libpayload, and to support lzma decode, add coreboot's lzma code, too. Carl-Daniel agreed to relicense the lzmadecode wrapper as BSD-l, solving licensing problems. Change-Id: Id28990fe7e951d99447e265a4880d70a8f208dd2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-04split CBFS support into shared core and extended functionsPatrick Georgi
The core is data structures and basic file finding capabilities, while option ROM handling, and loading stages and payloads is "extended". The core is rewritten to be BSD-l (its header already was), so can be copied to libpayload verbatim. It's also more robust in finding files in corrupted images, eg. after partial erase or update. Change-Id: Ic6923debf8bdf3c67c75746d3b31f3addab3dd74 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/114 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04libpayload: Add PDCurses and ncurses' libform/libmenuPatrick Georgi
PDCurses provides an alternative implementation of the curses library standard in addition to tinycurses. Where tinycurses is really tiny, PDCurses is more complete and provides virtually unlimited windows and the full API. The PDCurses code is brought in "vanilla", with all local changes residing in curses/pdcurses-backend/ In addition to a curses library, this change also provides libpanel (as part of the PDCurses code), and libform and libmenu which were derived from ncurses-5.9. As they rely on ncurses internals (and PDCurses is not ncurses), more changes were required for these libraries to work. The build system is extended to install the right set of header files depending on the selected curses implementation. Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/106 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-03Remove debugging code, or convert it to be selected by kconfigJonathan A. Kollasch
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03Use preferred style of fixed-width integer typesJonathan A. Kollasch
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-26crossgcc: update w32apiPatrick Georgi
crossgcc also needs lzma support as w32api is distributed in .tar.lzma Change-Id: Ia1938fa30262fe0c8bd655a08f9dc731a02e46ba Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/120 Tested-by: build bot (Jenkins)
2011-07-26buildgcc: Break if parts of the toolchain are missingPatrick Georgi
We test for the presence of a couple of tools and even print an error. But the tool didn't stop there. Change-Id: I40dcf7894408ea7b24d5f68c76df4b7541f469bd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/111 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add xhcbios and ahcibios rom handlingefdesign98
This change adds xhci and ahci bios rom handling that is similar to the vgabios rom handling in the arch/x86 Makefile.inc to the Persimmon and Torpedo mainboards. It also adds the basis for AHCI BIOS rom handling to the Persimmon Kconfig. Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/109 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add the SuperMicro H8QGI platformefdesign98
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add SSE3 dependent codeefdesign98
This change separates out changes that were initially found in the commit for XHCI and AHCI changes to "arch/x86/Makefile. inc". It also corrects a comment. The SSE3 dependent code adds a pair of CR4 access functions and a blob of code that re-sets CR4.OSFXSR and CR4.OSXMMEXCPT. Change-Id: Id97256978da81589d97dcae97981a049101b5258 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-21Libpayload: default DESTDIR for 'make install'Tadas Slotkus
If you would try download FILO via svn, then you probably get error message about libpayload install. This enables manually installing libpayload in legacy style :) Change-Id: I9f52be939303c5913611f21477d681e11d286382 Signed-off-by: Tadas Slotkus <devtadas@gmail.com> Reviewed-on: http://review.coreboot.org/102 Tested-by: build bot (Jenkins) Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-20libpayload: Provide dummy getenv()Patrick Georgi
Change-Id: I419fcb16e0b10dee9195072e0e6befa6c9e61a69 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/105 Tested-by: build bot (Jenkins) Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-18Add AMD Family 10 support to cpu folderefdesign98
This change adds the AMD Family 10 cpu support to the cpu folder. It also updates the makefiles of the Families 12 and 14 to take advantage of a pair of shared files that are moved to the cpu/agesa folder. Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/97 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18Add AMD Family 10 cpu support to northbridge folderefdesign98
This change adds the AMD Family 10 cpu support to the northbridge folder. The northbridge/amd/agesa Kconfig and Makefile.inc are changed as well. Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/98 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18Fix coreboot revision detectionPatrick Georgi
Neither do we publish coreboot via svn, nor is git-svn a useful indicator anymore. Instead, fetch a shortened commit id. Change-Id: I1b990384553209a7d39ecf7f5e8a2db7c7e34d0b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/110 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-17port_enable and port_reset must change atomically.Steven A. Falco
I have observed two separate EHCI host bridges that do not tolerate using C bit-fields to directly manipulate the portsc_t register. The reason for this is that the EHCI spec says that port_enable must go to 0 at the time that port_reset goes to 1. Naturally this cannot be done using direct bit-field manipulation. Instead, we use a temporary variable, change the bit-fields there, then atomically write the new value back to the hardware. Signed-off-by: Steven A. Falco <sfalco@coincident.com> Change-Id: If138faee43e0293efa203b86f7893fdf1e811269 Reviewed-on: http://review.coreboot.org/101 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-16Workaround the errata #181.Rudolf Marek
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the FID/VID SMAF is blocked by not yet configured internal VGA. The memory controller is enabled later, nor the workaround makes any harm to non-affected CPUs. This update unbreaks compilation by declaring the tmp variable. Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/69 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-16libpayload: Improve compatibilityPatrick Georgi
Define INT_MAX, EOF and make sure size_t is available. Change-Id: I1b4b717d2545ea8312ec52339300307a5bd68f8a Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-15Add the AMD Family10 Agesa codeefdesign98
This change officially adds the Agesa code for the AMD Family 10 cpus. This code supports the G34 and C32 sockets. Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/95 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-14Print a warning when an unknow USB controller type is detected.Steven A. Falco
The Intel E6XX Atom processor reports an unknown USB controller type (in addition to the standard EHCI and OHCI ones). Add a default case to print a warning when an unknown controller type is detected. Change-Id: I885d0ccec4c46fd212cceac599290e9bf85edbbb Signed-off-by: Steven A. Falco <sfalco@coincident.com> Reviewed-on: http://review.coreboot.org/100 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-14Move AMD SB800 early clock setup.Scott Duplichan
Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/96 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-14EHCI driver missing bus_address assignment.Steven A. Falco
Other USB drivers set the bus_address field. EHCI should do this too. Signed-off-by: Steven A. Falco <sfalco@coincident.com> Change-Id: Ic4274c6744951ef7fa0cb135caf8b9f177d8bcaf Reviewed-on: http://review.coreboot.org/99 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-14Set SB800 ROM decode size based on kconfig.Marc Jones
Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/94 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-13Enable SMI on M2V-MX SERudolf Marek
Finally the SMI routines are in good shape on AMD, lets enable this and later implement ACPI on/off SMI commands. Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/83 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-13Make AMD SMM SMP awareRudolf Marek
Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define, later all 0xa0000 could be changed to use it. Remove the unnecessary test if the smm_init routine is called once (it is called by BSP only) and also remove if lock bit is set becuase this bit is cleared by INIT it seems. Add the defines for fam10h and famfh to respective files, we do not have any shared AMD MSR header file. Tested on M2V-MX SE with dualcore CPU. Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/82 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-12Do full flush on uart8250 only at end of printk.Kevin O'Connor
The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-on: http://review.coreboot.org/90 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-07-11libpayload: Add qsort()Patrick Georgi
It's taken from OpenBSD and thus appropriately licensed (and reasonably tested). Change-Id: I5767600c9865d39e56c220b52e045f3501875b98 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/88 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-11T60: enable GPIO before using GPIO I/O port rangeSven Schnelle
Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/93 Tested-by: build bot (Jenkins)
2011-07-11T60: dont use X60 USB init flagSven Schnelle
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch initialization. Don't touch it on T60. Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/92 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2011-07-10ASRock E350M1: ACPI-related BSOD fixScott Duplichan
On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/91 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-09Fix memory size reporting on AMD family 14h systems for >= 4GBCristian Măgherușan-Stanciu
Applying Scott Duplichan's fix for memory >=4GB Adjusted it to the new directory structure (agesa_wrapper was renamed to just agesa). Boot-tested and confirmed to work, on my board Linux can now access the whole RAM. Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/48 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-07libpayload: Don't declare mouse support in tinycursesPatrick Georgi
Change-Id: Id1ff3d85617e3ec063ce332cf13920dfbbb7cf26 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/87 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-07libpayload: Provide atol(), malloc.hPatrick Georgi
Change-Id: I807ca061115146a6851eef481eb881b279fba8e1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/86 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-07libpayload: Implement strlcpyPatrick Georgi
Change-Id: Ibd339957690afe2cded46895c3088eba87f0ffd1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/85 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-07libpayload: fix wborder()Patrick Georgi
wborder didn't provide default characters to draw a border. Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/84 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-07Fix lint-002-build-dir-handlingPatrick Georgi
That lint test requires some Kconfig defaults and uses allyesconfig for that. Unfortunately that also draws in ccache and scanbuild support, which significantly change the behaviour of the toplevel Makefile. Notably, the ccache support breaks if no ccache is installed. Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/80 Tested-by: build bot (Jenkins)
2011-07-07T60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/89 Tested-by: build bot (Jenkins)
2011-07-07Run 'git fetch' in SeaBIOS only when really neededCristian Măgherușan-Stanciu
This allows coreboot to compile without Internet connectivity Change-Id: I969471e44e417f127fdc8744e868211500acee3e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/11 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-04Small SMM fixupsRudolf Marek
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG). While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just spinlocking. The rep nop could not be used because "as" complains that rep is used without string instructions. Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/81 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-03Fixes to the libpayload build systemPatrick Georgi
- its Makefile is part of the libpayload project - fix conversion bug in powerpc's Makefile.inc Change-Id: I84f2da092c3733ea7d0f232cb3768078cf13dfd5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/79 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-07-02whitespace-only changes in acpi.c, replaced spaces with tabsCristian Măgherușan-Stanciu
Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/74 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-07-02added a config option for ACPI debuggingCristian Măgherușan-Stanciu
Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/36 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-07-01Relicense Makefile to match libpayloadPatrick Georgi
libpayload's license is more liberal than coreboot's. If we are to use the coreboot build system for libpayload (bringing a couple of new features to libpayload), we should adopt it for this shared part even if not strictly necessary. Change-Id: I1349616861e193b3e01407debbec3d82e09e72c2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/70 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-30Add local copy of commit-msg hookPatrick Georgi
To avoid using untrusted network to download code, copy the relevant file to the repo and adapt "make gitconfig" to copy from there. Change-Id: I21f0b58d59250aa5d795cf289267ad93bd8d74db Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/73 Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de> Tested-by: build bot (Jenkins)
2011-06-30Reduce warnings/errors in libpayload when using picky compiler optionsPatrick Georgi
The new build system uses quite a few more -W flags for the compiler by default than the old one. And that's for the better. Change-Id: Ia8e3d28fb35c56760c2bd0983046c7067e8c5dd6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/72 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-06-30Use coreboot build system for libpayload, too.Patrick Georgi
This change makes building coreboot related projects more unified. Change-Id: I0f1181e2fffde1e03675523f7dc9eef3119052c3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/71 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-06-30Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP andRudolf Marek
for the transmit clock driving control. Unfortunately this is not enough to make the HT1000 work reliably, therefore blacklist this for now in CPU HT code. If ever anyone figure out what is wrong, it could be removed. The downgrading now makes the board work on HT800, which is certainly better than not at all with a HT1000 CPU. Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/68 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29Added support for Aaeon PFM-540I RevB PC104 SBCMark Norman
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU. More infomation about the board available at www.aaeon.com. Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd Signed-off-by: Mark Norman <mpnorman@gmail.com> Reviewed-on: http://review.coreboot.org/30 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29i82801gx: read RTC status register to prevent IRQ stormSven Schnelle
My Thinkpad appeared dead. After investigation, it turned out that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI handler didn't read the status register, so it was triggered again. This is a really nasty situation, as it means you have to dissemble your Notebook just to unplug the RTC battery. Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/67 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-29Libpayload needs to clear the bss region.Marc Jones
Libpayload shouldn't count on coreboot or other payloads to clear memory. This fixes problems with payloads being loaded after or on top of each other. Change-Id: I30303d47e465e8921f47acab667c7998ba79fca7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/66 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29amd southbirdge sb800 wrapper, pci bridge fixKerry She
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Add the AMD Torpedo mainboardefdesign98
The Torpedo mainboard is the reference platform for the AMD Family 12 cpus and the AMD Hudson-2 (SB900) southbridge. Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/54 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28msrtool: added support for Intel CPUsAnton Kochkov
Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/50 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28SMM: add guard and include types.h in cpu/x86/smm.hSven Schnelle
Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/64 Tested-by: build bot (Jenkins)
2011-06-28X60: remove pci config register save/restoreSven Schnelle
SMM code already makes sure this register is saved and restored, so we don't have to do it. Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/65 Tested-by: build bot (Jenkins)
2011-06-23Add SMSC SCH3114 superio register descriptions to superiotool.Mark Norman
This has been tested on a Aaeon PFM-540I RevB PC104 SBC. Change-Id: Ie02875a1fa2d90d7cc843ce745f727312f7b7aec Signed-off-by: Mark Norman <mpnorman@gmail.com> Reviewed-on: http://review.coreboot.org/43 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-23T60: undock on external power lossSven Schnelle
If power is unplugged/lost, we should undock the docking station. The power loss can also be caused by the fact that the user removed the thinkpad from the docking station without pressing the Undock button/hotkey first. Without undocking it on this event, the thinkpad LPC switch will still connect the Docking connector, which causes crashes when docking it again. Change-Id: I9ed783e491827bde20264868eab2b3a79c232922 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/62 Tested-by: build bot (Jenkins)
2011-06-23T60: enable userspace EC eventsSven Schnelle
EC events 0x50-0x5f are never triggered by the EC. Instead they can be generated by writing the wanted events to register 0x2a. Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/61 Tested-by: build bot (Jenkins)
2011-06-23T60: add additional EC eventsSven Schnelle
We missed a few bits, i.e the battery and some hotkey events. Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/60 Tested-by: build bot (Jenkins)
2011-06-23Add ThinkPad modelsSven Schnelle
Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/59 Tested-by: build bot (Jenkins)
2011-06-23T60: add missing License HeaderSven Schnelle
Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/58 Tested-by: build bot (Jenkins)
2011-06-22X60: add missing License HeaderSven Schnelle
Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/57 Tested-by: build bot (Jenkins)
2011-06-22H8: add missing License HeaderSven Schnelle
Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/56 Tested-by: build bot (Jenkins)
2011-06-22PMH7: add missing License HeaderSven Schnelle
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/55 Tested-by: build bot (Jenkins)
2011-06-22Move SB800 clock init earlierScott Duplichan
Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/32 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Add the coreboot config to CBFSCristian Măgherușan-Stanciu
The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build the current coreboot image. For space savings, all the comments and empty lines were removed from the original config, except for one that lists the coreboot git revision that's built into the image. This is done in order to easily reproduce the work of someone else when only having their ROM image. In theory the reproduce could even be automated by a new dedicated make target. This should work even with abuild now. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/46 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21Add AMD SB900 CIMx codeefdesign98
This code is added to support the AMD SB900 southbridge. Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/41 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21Add AMD Family 12 cpu Agesa codeefdesign98
This is the addition of the AMD Family 12 cpu code. Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c Signed-off-by: Frank Vibrans<frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/40 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20sb800: move spi prefetch and fast read mode to sb bootblock.Stefan Reinauer
So we don't waste time on the first cbfs scan. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> [adapt persimmon with the same change, and work around romcc bug in bootblock code: it doesn't like MEMACCESS[idx] |= value;] Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997 Reviewed-on: http://review.coreboot.org/9 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20Introduced support for 8MB and 16MB flash sizesCristian Măgherușan-Stanciu
Change-Id: I217ff84be3575ec09781710f19ad272c88227663 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/49 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20ASRock E350M1: Enable USB3 supportMarshall Buschman
Requires Scott Duplichan's patch for NIC support. Enables required PCIe port for USB3 - does not interfere with normal operations on non-USB3 model. Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9 Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/45 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-19ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nicScott Duplichan
Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/44 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction. For reference, the mail i've sent to ML with the bugreport: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how docking/undocking works: 1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock) 2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows: a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range b) Store(0, 0x808) // Generates I/O Trap to SMM c) // SMM is executed d) Return (SMIF) // Return Result in SMIF I've verified that a) is really executed with ACPI debugging in the Linux Kernel. It writes the correct value to GNVS Memory. After that, i've logged the SMIF value in SMM, which contains some random (or former) value of SMIF. So i've added the GNVS area to /proc/mtrr which made things work. I've also tried a wbinvd() in SMM code, with the same result. After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized that it starts with: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 /* Enable protected mode */ data32 ljmp $0x08, $1f ...which disables caching in SMM code, but doesn't flush the cache. So the problem is: - the linux axpi write to the SMIF GNVS Area will be written to Cache, because GNVS is WB - the SMM code runs with cache disabled, and fetches SMIF directly from Memory, which is some other value Possible Solutions: - enable cache in SMM (yeah, cache poisoning...) - flush caches in SMM (really expensive) - mark GNVS as UC in Memory Map (will only work if OS really marks that Area as UC. Checked various vendor BIOSes, none of them are marking NVS as UC. So this seems rather uncommon.) - flush only the cache line which contains GNVS. Would fix this particular problem, but users/developers could see other Bugs like this. And not everyone likes to debug such problems. So i won't like this solution. Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/39 Tested-by: build bot (Jenkins)
2011-06-18T60: set dock LED's in mainboard.cSven Schnelle
The docking takes place in romstage to have early serial I/O for debugging. But to keep romstage small and prevent linking the EC code to romstage, set the status LED's in ramstage. Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/42 Tested-by: build bot (Jenkins)
2011-06-16X60/T60: disable USB power during suspendSven Schnelle
Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/38 Tested-by: build bot (Jenkins)
2011-06-16Lenovo H8 EC: add usb_power_enable()Sven Schnelle
Can be used to disable/enable Power output on USB ports. Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/37 Tested-by: build bot (Jenkins)
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/34 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15i945 GMA: restore tft brightness from cmosSven Schnelle
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/24 Tested-by: build bot (Jenkins)
2011-06-15Remove old ACPI codeSven Schnelle
it isn't used anywhere, and could be fetched from git/svn history if needed. Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/35 Tested-by: build bot (Jenkins)
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/33 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15Update README with newer version of the text from the web pageStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027 Reviewed-on: http://review.coreboot.org/19 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-06-15X60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/27 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15X60: trigger save cmos on volume/brightness changeSven Schnelle
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/25 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15CMOS: add set_option()Sven Schnelle
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/23 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-13X60/T60: set CMOS defaultsSven Schnelle
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/26 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-12ASRock/E350M1: Skip memory clear for boot time reductionMarshall Buschman
Applying Scott's patches to e350m1, svn r6600: Memory clear is not required for non-ECC boards. Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/20 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-12X60/T60: fix return value of mainboard_io_trap_handler()Sven Schnelle
The handler should return 1 if it handled the request. The current code returns 0, which causes 'Unknown function' logs. Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/29 Tested-by: build bot (Jenkins)
2011-06-12log ec data with DEBUG_SPEWSven Schnelle
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/28 Tested-by: build bot (Jenkins)
2011-06-10Add ACPI automatic PIC/APIC interrupt routing logic for ck804Jonathan A. Kollasch
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/13 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-09superiotool: Cosmetics and coding style fixes.Uwe Hermann
Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Reviewed-on: http://review.coreboot.org/18 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2011-06-09H8 EC: add volume CMOS settingSven Schnelle
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/12 Tested-by: build bot (Jenkins)
2011-06-09util/crossgcc: Add build-without-gdb Makefile targetPeter Stuge
Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/16 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09util/crossgcc: Add buildgcc -G and --skip-gdb optionsPeter Stuge
Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/15 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09Change make crossgcc to build without gdb by defaultPeter Stuge
Using gdb with coreboot is not (yet) very common, so at least for now it makes sense to not build gdb by default. A make crosstools target is also added, which runs the full build in util/crossgcc and thus generates a toolchain with both compiler and debugger. Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/17 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 11:16:14 +0000