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Use the correct SPD size for crc calculation. sizeof(*spd) returns 4
while sizeof(spd_raw_data) returns the expected value of 256.
Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log.
Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H.
Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10629
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h
/// PCIe PSPP Power policy
typedef enum {
PsppDisabled, ///< PSPP disabled
PsppPerformance = 1, ///< Performance
PsppBalanceHigh, ///< Balance-High
PsppBalanceLow, ///< Balance-Low
PsppPowerSaving, ///< Power Saving
MaxPspp ///< Max Pspp for boundary check
} PCIE_PSPP_POLICY;
Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10461
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Bettong, Lamar and Olivehill Plus have many same Kconfigs.
Move them to northbridge/amd/pi/Kconfig.
Change-Id: I758d5a09f27eee7a7bd60268a2aaed6f16fd0294
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10421
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a new mainboard based on AMD's Family 15h Model 60h processor.
TEST: Bettong can boot Ubuntu 14.10, Windows 7 and Windows 8.
Change-Id: Id807369ff0f04ba303383c65ddd1bd512f184e6a
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10420
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Tested on Bettong. Windows 7, Windows 8.1 and Ubuntu 14.04 can boot.
Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10419
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS
with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with
S3_DATA_BLOCK.
Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10526
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ic48a08d1067c850555cf04ad29e65e9bdb7c4243
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10619
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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The symbols used in these expressions were not correct and would never
evaluate as true.
Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10437
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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At present, no option exists for "Keep VESA framebuffer", which
means that text-mode will be used. Add the appropriate Kconfig
option.
Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/10553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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On i945 legacy brightness control is enabled by a single
bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
reverses polarity). Set the bit to enable brightness
controls.
Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/7048
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I2ddb5a8b183b21cbd3c3b22c537b815e86bd4738
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10592
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I5ff309948c36289eedeb8a18030cdd2b4c337690
Reviewed-on: http://review.coreboot.org/10595
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10591
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10584
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10577
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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The EARLY_CONSOLE Kconfig symbol was removed in
commit 48713a1b - console: Drop EARLY_CONSOLE option
The arm64 and mips directories don't even have early_console.c
to include.
Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Kconfig sometimes fails to parse the last line of a file if there's
no newline at the end. Add one to be safe.
Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Because Kconfig uses the first valid default that it comes across, the
'source' commands to load sub-Kconfigs should be ordered from the
most specific (mainboards) to less specific (chipsets) to least specific
(architectures). This allows the mainboards to override chipsets and
architecture Kconfig files.
Because the architecture files were getting loaded ahead of the chipset
and cpu Kconfigs, the preferred defaults values for things such as
NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set.
Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10609
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these
don't actually select anything.
Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10608
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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buildgcc fails if g++ or clang isn't found on the host. This
was failing on OSX due to the string used to check for clang
doesn't match "Apple LLVM". Add an additional search string for
clang "LLVM".
Change-Id: I05e36cfc690061b3233376d57f44f197cab933ea
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10569
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10580
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10578
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I782007fe9754ec3ae0b5dc31e7865f7e46cfbc74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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This does not optimize memcpy for 64bit, it merely makes it compile.
Change-Id: I69ad6bd0c3d5f617d9222643abf7a2ba7c2a0359
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10575
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I03eb1c0f1e0b0c6213ec6b26cf41dadd4df9b910
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10574
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Pick up the latest from blobs.
34b0926 AMD Merlin Falcon: remove build warnings
e581a5c AMD pi: replace LocateModule with agesawrapper_locate_module
c5ddfb6 AMD PI: remove unuseful code
Change-Id: I2b9d2b61cb00aa651b90dc76368d215077e27cad
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10603
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There's a separate target -P iasl for that now.
Change-Id: I95c0fe8fc266859d8a31b7bea890775dc9f19694
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10567
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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With this change, the x86_64-elf-gcc can compile i386-elf
binaries by specifying -m32. The patch against GCC is needed
to enable building the 32bit libraries when building x86_64-elf-gcc
Change-Id: Ic86a009eccfdf3e33a398bcdcc13b15c8dfc0d31
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic36727104e5c2f620f9b2b7b340de8548b467397
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10547
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit
Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Provide ACPI devices with devicetree-compatible annotations for the
three leds and the button of the APU1, as well as the GPIO driver.
This will cause the Linux kernel to automatically load the following
modules:
leds_gpio (CONFIG_LEDS_GPIO)
gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED)
gpio_sb8xx (CONFIG_GPIO_SB8XX)
See
http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf
and https://lwn.net/Articles/612062/ for some more information on how
the PRP0001 HID works.
To make this usable a Linux GPIO driver for the AMD chipset is also
required, which I am currently working on, but have not submitted
upstream yet.
Leds have been named after the convention in
Documentation/leds/leds-class.txt:
LED Device Naming
=================
Is currently of the form:
"devicename:colour:function"
For comparison, on an OpenWRT device:
GPIOs 0-21, ath79:
gpio-1 (tp-link:green:usb ) out hi
gpio-2 (tp-link:green:system) out lo
gpio-3 (reset ) in hi
gpio-5 (tp-link:green:qss ) out lo
gpio-7 (qss ) in hi
gpio-9 (tp-link:green:wlan ) out lo
gpio-18 (rtl8366rb ) in hi
gpio-19 (rtl8366rb ) in hi
On the apu1:
GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver:
gpio-475 (switch1 ) in hi
gpio-477 (apu1:green:led1 ) out hi
gpio-478 (apu1:green:led2 ) out hi
gpio-479 (apu1:green:led3 ) out hi
Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10540
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c
Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276779
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10562
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Allow calls to cpu_phys_address_size and its support functions during
romstage. This enables the proper display of MTRRs during romstage
without duplicating this code.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0
Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277392
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10561
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add macro to calculate size of a structure member
BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully
Change-Id: I71bcefe1c3b32ad559d7764e77369c67d09422a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b425a310c14eabad79caf97649db6469380bd602
Original-Change-Id: I377fff062729aa664f7db469b86764b0ad941c38
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276809
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch checks for following conditions
(1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found
then don't enable LTR.
(2)
2.1) set_L1_ss_latency is member if ops_pci, which could be NULL.
so confirm ops_pci is not NULL before calling its member function.
2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency.
BUG=none
BRANCH=none
TEST=build and boot coreboot with L1 substate enabled on sklrvp3.
Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181
Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/10559
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This CL is in preparing for tegra mtc that is invoked by dev init.
mtc currently requires floating point instructions support.
BUG=chrome-os-partner:40999
BRANCH=none
TEST=Build and boot smaug
Change-Id: I470dfcd86026812d617f9ff4f4fcdce601195857
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e3f7336fc7cedf96dab4eff204616519856f831
Original-Change-Id: I14c0003ce76ddf4b4ebb0cf171ea3c62cab55ef9
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/275112
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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For consistency in user output, move the check for all
required utilities after printing the banner and parsing
options.
Change-Id: I5bf31368885c73e35f18b02d53d099f3f3871acc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10566
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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When required tools are missing, try to give the user more detailed
information on how to solve the problem.
Change-Id: Ifa21c1af38a036a7d4f5a786041a87a7d45f4ec5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10555
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iee5ab0d3bdc8b754669356f2046d290d9ca555c2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10511
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Don't print error messages if an unpatched clang is detected.
Change-Id: If77722a40a59e99f01d121a0c43999f05f3c4421
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This moves the CMAKE definition down into the case statement
for $PACKAGE so that it is only required when the user wants to
build clang.
With this approach, "./buildgcc -P clang" will error out with the
"ERROR: Missing tool:" message if cmake is not installed.
Change-Id: I1e5c1bd67ade8f93ba0390df7f234deb47b9b18a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10556
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add support for detecting an x86-64 cross compiler in xcompile.
Change-Id: Icd2c9af7903956216db1fd54902eab6da0fe3e21
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8669
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibcfdc08c9aac02fe263afd629fc262f71da80e9a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8695
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I1535fea97c676ed6465d777f444b0a1a0e023474
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8694
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Almost all of the code between x86 and x64 can be shared, so select it for
either architecture.
Change-Id: I681149ed7698c08b702bb19f074f369699cef1bf
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8693
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I81f6d8a21ea0d8218f5a4aab2feb39be32f88e01
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8692
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For now, share code with x86, and use the "large" code model.
Also align the architecture specific CFLAGS in toolchain.inc
for cosmetics.
Change-Id: Ie84893d3460115802fbd70c28b10e709029c6b4e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I2a9304a6b573a10e896f9ff77bfb09f20b21eb50
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10541
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I12ef633009b5c63b08fbeb76d58cb08c776485ac
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10546
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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The smbus.asl operation regions prevent the Linux i2c driver (i2c_piix4)
for this chipset from claiming the ioport ranges and thus it fails to
load.
The methods defined in smbus.asl are not used in the DSDT and also don't
exist in the DSDT of the vendor firmware.
In particular due to the following check in i2c-piix4.c will fail unless
acpi_enforce_resources=no is explicitly set on the Linux kernel
parameters:
if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
return -ENODEV;
Depending on kernel options the only error message printed is
ACPI Warning: SystemIO range 0x0000000000000B00-0x0000000000000B07 conflicts with OpRegion 0x0000000000000B00-0x0000000000000B0B (\SMB0) (20150410/utaddress-254)
ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
However since it does not implement a standard interface there is no
native ACPI driver for smbus.asl.
Change-Id: Id8401e8b36f0e2412d490a92c20540a04d853125
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10539
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Recently ck804/lpc.c started generating pstates for us.
Change-Id: Ie47fff0516e0e838fdcd5084074ce2cabfe7e290
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8318
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The same values are used on my Lenovo R400 as reported by Francis Rowe
from his T400 and T500.
TEST: Read /proc/asound/card0/codec#0, see that the jack locations
correspond to the board layout, e.g. headphone and microphone
connectors are on front of the laptop, not right. Read
/sys/class/sound/hwC0D0/init_pin_configs, see that it has the same
content as with factory firmware.
Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/10431
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Commit 8d80a3fb (ASRock DSDT: Split the ASRock DSDT) creates the file
`acpi/smbus.asl` in the board directory, but includes the identical
southbridge file in `dsdt.asl`.
So, the file is actually unused. Therefore remove it.
Change-Id: I26c5a2eaf3822d37da2402da65b278a3ee6d42f0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10544
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I1ea1b1efedfea2926a24f06beeb8d7d0464057e5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10543
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It's not used outside of very old AMD CPUs.
Change-Id: Ide51ef1a526df50d88bf229432d7d36bc777f9eb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10538
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Kern is the southbridge of AMD Merlin Falcon(Carrizo).
This add support of HD audio, lpc, sata and usb for Kern.
Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10418
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds the AMD Family 15h model 60h CPU.
S3 suspend/resume currently is not supported.
Tested on the amd/bettong platform.
Change-Id: I5dea55a5664d29c07a54937ed1e5c2f84715d8ea
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10417
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of having three copies of amdlib, the glue code for Agesa,
let's share the code between all implementations (and come up with
a versioned API if needed at some point in the future)
Change-Id: I38edffd1bbb04785765d20ca30908a1101c0dda0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10507
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB. This includes the gcc makefiles,
some Kconfig, and the AGESA standard library functions.
Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.
Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10416
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Otherwise dummy contains uninitialized data, which leads to non-reproducible
builds (and a leak of 4 bytes of stack data).
Change-Id: Iaaf846580ec436fdd4f0800c7576b544f50d6ae0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10524
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds support for the Fintek F81866AD-I SuperIO,
which is very similar to the fintek/f81865f.
This code adds some fan control support, inspired by fintek/f71869ad.
Furthermore its possible to change the temp sensor type (thermistor or diode).
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10287
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Initialization for the Winbond W631GG6KB part using Synopsys
DDR uMCTL and DDR Phy.
This code adds a separate function for DDR3 initialization
and moves all the necessary defines in a separate header file.
The programming procedure that is executed at power up to bring
up the uMCTL, PHY and memories into a state where reads and
writes to the memory can be performed is the following:
1. uPCTL (Universal DDR protocol controller) initialization
The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH
needed for driving the memory power-up sequence are programmed
as a function of the internal timers clock frequency.
Organization (memory chip specific) values are set
(column/bank/row address width and number of ranks), together
with other static values (latency, timing, power up configuration).
All these values are static, provided by the datasheet,
being determined by the memory type, size and frequency.
2. PHY initialization
The PHY is programmed with datasheet provided values,
specifying the initialization values for it to send to the
external memory (timing parameters).
Also, delay lines (DLL) and strength of drive pads are
calibrated (based on external conditions: temperature,
voltage, noise) and locked. After that, the PHY goes
through a trainig process (also dependent on the
current conditions at boot time) to establish precise
timing configuration between the DDR clock and DQS (data strobe)
and between DQS and DQ (data).
3. Memory power up
4. Switch from configuration state to access state.
It was tested on Pistachio bring up board where DDR was initialized
properly and ramstage executed correctly
Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Switching from active windowing DQS gating scheme to
passive windowing mode resolves boot stability issues
on chips found to have memory corruption issues during
boot or memory tests.
It was tested on Pistachio bring up board where DDR is
initialized properly and ramstage executed correctly;
We have cycled units over 12,000 times with no boot errors.
This option was chosen over the alternative of using
passive windowing mode for DQS training and after switching
back to active mode, as this option was recommended by
Synopsys. Using the alternative would give different
timing values during training that were not longer accurate
during normal activity.
Change-Id: Ie604eddc0a9a982b2f89198f44deb88a01b7b322
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10528
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fix by checking the actual function return value (the search
address pointer), rather than the search length value (which isn't
guaranteed to be sane or useful).
Change-Id: I226c635ddbbc916b02494fcd97df27d141cc2c7f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10516
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The precise phrase returned by 'type' differs between locales and shells.
It also doesn't matter because it returns an error code when it hasn't found a
match.
Let's simply assume there's no build_$OneOfOurPackages commands around that
could also match.
Change-Id: I44f021243149701e8da9dd74c368ca2ad4509419
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-on: linux bash, linux dash, solaris sh, solaris ksh.
Reviewed-on: http://review.coreboot.org/10517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ic6ce697af6102da7d8c53947c9d3b5ac39817d7c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10333
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Commit 899d13d (cbfs: new API and better program loading) broke
panther's lan init when no vpd.bin present from which to read
the MAC address. Fix this by checking the validity of the search
address pointer, rather than the search length.
Change-Id: I8c7ca410d8ce5c5d92242a21c4c2ff4c001a68bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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libpayload is the only Kconfig based project under
the coreboot umbrella that is using Config.in as its
name for Kconfig config files. Rename that to Kconfig
as on the other projects for consistency.
Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10520
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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using grep is an extra process invocation, but it's not a bashism.
Also match precisely, so AGCC doesn't trigger on GCC (we don't have collisions
right now, but we won't have to deal with them in the future)
Change-Id: I242833c350b7f1e6a6793f288c1aae0b50d57a26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10518
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The proper log level for any given printk statement is up to the
interpretation of the developer. This results in console output with
somewhat inconsistent levels of verbosity. This patch clearly defines each
log level and its use case, hopefully resulting in less ambiguity for
developers.
The concern with this patch might be that it leaves a lot of preexisting
printk statements using a log level that is inconsistent with the
description. I think that *most* statements map to these extended
definitions very nicely. The most discrepancies are between debug and
spew, but I'm willing to say that 95% of statements with a level lower than
debug are correct by these definitions.
There was some discussion dating back to 2010 on the mailing list about
renaming these constants to lose the 'BIOS_' prefix and to consolidate
some of them into a single constant. I disagree that it is necessary
to merge any of them, I think they all have unique use cases. But I do
think that if you all agree with these definitions, it might be useful to
rename them to reflect their use cases.
I also will add that I believe removing BIOS_NEVER is a good idea. I do
not see the use case, and it's used in only 4 files.
Change-Id: I8aefdd9dee4cb4ad2fc78ee7133a93f8ddf0720b
Signed-off-by: Nicky Sielicki <nlsielicki@wisc.edu>
Reviewed-on: http://review.coreboot.org/10444
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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New marker includes:
3d5af98 microcode: Update Broadwell to MC0306D4_0000001F
349fd55 microcode: Update Baytrail to M0C30678_000082D
9077293 Add BLOBs to support AMD Embedded "Merlin Falcon" processor
Change-Id: I53f8f95079c6436ad316a11d432fcf92c03332b5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Locales differ in the order in which they sort entries. This ensures
predictable behavior.
Change-Id: I4ceec90a56bbc368a847d14298db0a21cc21e77c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10510
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's derived from EEPROM on Lenovo machines and not from user config
which is ignored.
Change-Id: I54fb76a3160e47cd36d33d2937c4bfaddcd36a69
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7055
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
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This change adds cache management after loading stages.
Before jumping to a new stage we should flush the data
caches to memory and invalidate instruction cache.
After all segments are loaded CBFS cache is also
flushed.
With this change all stages of coreboot are now executed
successfully. This was tested on Pistachio bring up board,
also known as Urara.
Change-Id: I86e07432c21a803ef1cfc41b633c5df42b99de90
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10456
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The coreboot table address is passed as an argument when jumping
to payload.
With this change depthcharge is loaded and executed properly on urara.
Change-Id: I230d474a91b8d38aff070aa4aac623b6c8f0809c
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Place included header files in alphabetical order.
Change-Id: Ice23178d1f07e2cb0178efbc7ce487d54bf3f708
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10459
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use cbmem_initialize_empty() after DDR configuration so that
cbmem is always initialized from scratch on each boot.
Change-Id: Ic9ca34867b26aab82cf3154280694b6fb61ee11f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10458
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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sata.asl and superio.asl are empty files. Remove them.
Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The default ordering for the base kconfig entries has the CPU
directory coming before the SOC directory, which means that the
values in the CPU Kconfig take precedence.
The first visible consequence of this is that CONFIG_SMM_TSEG_SIZE
will be set to 0 on all SOC implementations.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Change-Id: Ifd56a2ceb73ab335a86126e48d35ff4c749990ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0cddae37d3de1cbf3dd6afcf4a0707b7af9436fa
Original-Change-Id: I98e3bf249650b50667dde62b6be9c1bf587ad0b2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/276189
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10478
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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BUG=none
BRANCH=none
TEST=Boot from mickey board
Change-Id: I6eadf52bddcf89011a112a8e5dee5e752556add9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e3c865f0bf8567c3183d7948a0f9e8361db70695
Original-Change-Id: I438527ee0870044f48b23a6842986e7cf166e191
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276290
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10477
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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BUG=chrome-os-partner:41185
BRANCH=None
TEST=Compiles successfully for ryu.
Change-Id: I78ccc4b5ef8b49bae533e5a82323f07aaab01a7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf9d288d4bbc91301dc814408bf5e3686b869974
Original-Change-Id: I24df0eb51883a634ec3d26d46f79a059a4f8394a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/275749
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10476
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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Copy the Peppy directory. No changes.
Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10499
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9320
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Build with bfd and gold linker, but use bfd linker per default
and make sure that lto is enabled in both binutils and gcc
Change-Id: I0584396b4580674cfdca24fbed0d8eeb1ee38806
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10496
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Instead of building IASL and GDB implicitly when building
GCC, this patch changes buildgcc to let you explicitly specify
what you want to build.
This will prevent IASL from building over and over again, when
all you need is GDB.
The new command line option is -P | --package <package> where
package is one of the following: GCC, GDB, CLANG, IASL
If no package is specified, buildgcc will default to GCC.
Change-Id: I8836bed16fc2bc39e0951199143581cc6d71cb4d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10492
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I707802befe5b8aaafafc34b17cbdfe795777b6f6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10501
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The type1 family setting from chromium was mis-merged into the
type2 function. Move it to the correct type1 function.
Bad commit: 51bdc4781635b99d89e6b7a414a2172be8cb690c
Change-Id: I72e6ef80bbf185a39fcf169c8247dc16462e6bc3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10498
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Change-Id: I8e8b6e7c123e641749c42a7c706176e285902bb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10502
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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IASL was broken when compiling without GCC.
Change-Id: Ib859ce41c1dda10181781c025fc378504f5ebb91
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10495
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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GDB stopped building ever since we updated from version 7.6
but nobody noticed ;)
Update from 7.9 to 7.9.1 and bring the required patches forward.
Change-Id: I2f357525a46d5540e9f57b80d830943bbd5dfcaf
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10494
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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This groups all tasks happening in the main program,
orders them according to their dependencies and adds
comments on the various tasks.
Change-Id: Ib62bd213977cbc3307ef62e9a7e64515563968c1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10490
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
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Change-Id: I7be9b39a0d92882fa437f666d7f4a85e6f0a23f6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10489
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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- don't capture build_$package in a subshell by piping it
- move HOSTCFLAGS to build_GMP
- only create a build directory if a build happens
- automatically collect packages to build
Change-Id: Ic5a9f3f222faecd3381b413e5f25dff87262a855
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10475
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
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Change-Id: Ic3503938b996bbf31f1417923f019a7bc722b9fd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10429
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
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Change-Id: If2d48b84fe7bd7b144e96171e54067891e3c4e2e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9316
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I8e78cbae132566b6ca27e0a68af2656364c82b8f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9332
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The type of a resource is really an enumeration but our implementation
is as a bitmask. Compare all relevant bits and remove the shadowed
declarations of IORESOURCE bits.
Change-Id: I7f605d72ea702eb4fa6019ca1297f98d240c4f1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8891
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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No board in the tree selects this and it looks like the implementation
was done at chipset level while it should be part of PCI subsystem.
When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test.
Feature of placing prefetchable PCI memory above 4GB may not work if
there is any 32-bit only prefetchable PCI BARs in the system.
Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On modern mainboards with multiple PCI-e devices and a single
graphics card the default MMIO hole size of 512M is inadequate,
leading to resource-hungry PCI-e devices (such as an external
graphics card) being assigned invalid MMIO ranges. This, in
turn, causes the entire PCI subsystem to become unavailable,
leading to a failure to boot.
TEST: Booted KGPE-D16 with NVIDIA 7300LE and verified proper
operation of PCI/PCI-e devices, including text mode VGA operation
via the add-on card and its VGA option ROM.
Change-Id: I8d25f4b19f2d0860644ab1ee002c15041437121f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10428
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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