summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-09-08samus: Disable SMBus controllerDuncan Laurie
Nothing is connected to this port. Change-Id: If3e466a3053fa694a511c2335c16381f77f56f47 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174089 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5ddb6a444d5c3141868eaf618ecb014b0262a796) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6827 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-08tegra124: return the UART base address based on indexIsaac Christensen
Change-Id: I73a8e56559c7ffdaab39a5c19311221c91565004 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Tweaks from bringupDuncan Laurie
- GPIO29 is no longer connected so we don't need the SMI workaround on the entry to sleep states. - Disable touchscreen wake source until the kernel driver is working so it does not wake immediately. - Update a few GPIOs and disable the codec for now as it is leaking into the 1.8V DDR rail. Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Fix up memory SPD informationDuncan Laurie
The LPDDR3 memory is x32 and dual rank with 14 row bits. In addition the memory is actually elpida, even though they are owned by micron it is confusing to label it as such. And the ram strap options were inverted from what I expected so the memory table needs to be updated. Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6828 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Add onboard device configurationDuncan Laurie
Change-Id: Ib7b6688982e9f74cffe40d11d4a9ec69acd55d37 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174088 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 41624b073fb59b1372ee5a8eba3ed64c7e633311) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6826 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-08samus: Change thermal behavior to match other haswell platformsDuncan Laurie
Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2014-09-08nvidia-cbootimage: add submoduleIsaac Christensen
Change-Id: I3ad8eed42255db426987065190c197baead40673 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6836 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-06romcc: avoid use-after-freePatrick Georgi
Windows bugchecks on this for a while, so we ifndef'd the free() call out. Now some Linuxes (depending on their glibc) also fail on it, so just remove the call altogether at the cost of some leaked memory (couple hundred kilobytes) because tracking down the precise fix is too hard. In case someone wants to fix it, valgrind sees the issues, so revert this change and work on romcc's memory management until valgrind is happy. To get a fix in, provide a good explanation why your change is actually the right way to fix it - for silencing valgrind, this change will do. Change-Id: Iae3f847e09a0d7bcb8bb4f50983a1b0727570b23 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6846 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-09-05Implement ACPI in a per device wayVladimir Serbinenko
This approach avoids having same basic tables 150-lines mantra over 100 times in codebase. Change-Id: I76fb2fbcb9ca0654f2e5fd5d90bd62392165777c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6801 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-05Consolidate intel vga int15 hooksVladimir Serbinenko
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05i82801gx: Kill unused TCG and SMI1Vladimir Serbinenko
SMI1 is being written to but never read from. Change-Id: I82c0800713e3093eb1317b5e1f6f228771134857 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6808 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05what-jenkins-does: kill build results earlyPatrick Georgi
This reduces disk use and simplifies using abuild on a ramdisk. Change-Id: I3fb8d273dcbb5008fa9cfaa9465a59e3bbcb974b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05roda/rk886ex: Move device changes to mainboard code from acpi tables codeVladimir Serbinenko
Change-Id: I3d694e5b3092d78bce89f6baa7b2dedffddf3012 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05azalia: Use convenience macros throughoutVladimir Serbinenko
Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05azalia: Change specific PIN_CFGs to generic AZALIA_PIN_CFGVladimir Serbinenko
Change-Id: I3463d0c283793547b00a7628f27f2f1777c21238 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05azalia: Add convenience macrosVladimir Serbinenko
Change-Id: Ie605efdda3b486ae6ef780266e6c651e41bb5392 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-04mainboard: Add AMD DB-FT3b (Olive Hill+) with Steppe Eagle SoCBruce Griffith
Create a new mainboard based on the AMD DB-FT3 development board (Olive Hill) using an AMD Steppe Eagle processor. The actual DB-FT3 and DB-FT3b mainboards are identical except for the soldered-down SoC device. The new AMD DB-FT3b development board (Olive Hill+) features: * Mini-ITX form factor * 2x DisplayPort * 1x VGA * Integrated Realtek RTL8111-compatible Ethernet * 2x USB 3.0 ports * 2x USB 2.0 externally-accessible ports * 2x USB 2.0 internally-accessible ports (via headers) * micro LPC header * Integrated platform security processor * 2x Full-size DDR3 DIMM support (1 channel) * Realtek ALC272 HD audio * 2x SATA ports * 1x SD card slot * 1x PCIe (x4) slot * 1x mini-PCIe slot * 8-pin programming header Eliminate the extraneous headers included in PlatformGnbPcie. BiosCallOuts normally has a bunch of extraneous references to the mainboard name. Rather than correct the spelling of a bunch of instances, just get rid of them. For the most part, use the Olive Hill ACPI definitions since the DB-FT3b board ("Olive Hill+") and Olive Hill are the same board with different processors. Change some function prototypes for functions without parameters to void instead of AGESA's VOID. There are no parameters for these functions, so there is no real reason to use VOID. S3 and fan control are not supported. HD audio is not working. Change-Id: I794d7a8f4f948346cfe7cbd443c9aed5f70c99ed Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6681 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-09-04cbfstool:linux_trampoline: config CS and DS segment descriptorsCurt Brune
The Linux trampoline code does not set up the segment descriptors for __BOOT_CS and __BOOT_DS as described in the Linux kernel documentation: ... a GDT must be loaded with the descriptors for selectors __BOOT_CS(0x10) and __BOOT_DS(0x18); both descriptors must be 4G flat segment; __BOOT_CS must have execute/read permission, and __BOOT_DS must have read/write permission; This is not a problem when launching a Linux payload from coreboot, as coreboot configures the segment descriptors at selectors 0x10 and 0x18. Coreboot configures these selectors in the ramstage to match what the Linux kernel expects (see coreboot/src/arch/x86/lib/c_start.S). When the cbfs payload is launched in other environments, SeaBIOS for example, the segment descriptors are configured differently and the cbfs Linux payload does not work. If the cbfs Linux payload is to be used in multiple environments should the trampoline needs to take care of the descriptors that Linux requires. This patch updates the Linux trampoline code to configure the 4G flat descriptors that Linux expects. The configuration is borrowed from the descriptor configs in coreboot/src/arch/x86/lib/c_start.S for selectors 0x10 and 0x18. The linux_trampoline code is slightly refractored by defining the trampoline entry address, 0x40000, as TRAMPOLINE_ENTRY_LOC. This definition is moved into a separate header file, linux_trampoline.h. This header file is now included by both the trampoline assembly language code and the trampoline loader C code. The trampoline assembly language code can now use TRAMPOLINE_ENTRY_LOC as scratch space for the sgdt CPU instruction. Testing Done: Verified the Linux payload is booted correctly in the following environments: 1. Coreboot -> Linux Payload 2. Coreboot -> SeaBIOS -> Linux Payload: (previously did not work) Change-Id: I888f74ff43073a6b7318f6713a8d4ecb804c0162 Signed-off-by: Curt Brune <curt@cumulusnetworks.com> Reviewed-on: http://review.coreboot.org/6796 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-04build: add what-jenkins-does targetPatrick Georgi
This target does (pretty much) exactly the same what jenkins is doing on our build nodes: - complete abuild run of our tree with a given payload - building all libpayload configs we ship - building the cbmem utility In fact at some point we could tell jenkins to just run this command. For debugging, pass along V and Q variables so inner make processes are slightly more noisy on demand. Change-Id: Ib515170603a151cc3c3b10c743f1468a9875dbdc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6797 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-04AMD Steppe Eagle: Disable "No Snoop Enable" to stop HDMI audio stutterBruce Griffith
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. The posted amd_late_init.c northbridge code is missing a test for Steppe Eagle northbridges. See coreboot Gerrit change 3934, commit ID 4ca721399c (AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu). Change-Id: I89894d0ce4ad72ea16d61b445edb9e67920bca24 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6822 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-04libpayload: usb: Refactor USB enumeration to fix SuperSpeed devicesJulius Werner
This patch represents a major overhaul of the USB enumeration code in order to make it cleaner and much more robust to weird or malicious devices. The main improvement is that it correctly parses the USB descriptors even if there are unknown descriptors interspersed within, which is perfectly legal and in particular present on all SuperSpeed devices (due to the SuperSpeed Endpoint Companion Descriptor). In addition, it gets rid of the really whacky and special cased get_descriptor() function, which would read every descriptor twice whether it made sense or not. The new code makes the callers allocate descriptor memory and only read stuff twice when it's really necessary (i.e. the device and configuration descriptors). Finally, it also moves some more responsibilities into the controller-specific set_address() function in order to make sure things are initialized at the same stage for all controllers. In the new model it initializes the device entry (which zeroes the endpoint array), sets up endpoint 0 (including MPS), sets the device address and finally returns the whole usbdev_t structure with that address correctly set. Note that this should make SuperSpeed devices work, but SuperSpeed hubs are a wholly different story and would require a custom hub driver (since the hub descriptor and port status formats are different for USB 3.0 ports, and the whole issue about the same hub showing up as two different devices on two different ports might present additional challenges). The stack currently just issues a warning and refuses to initialize this part of the hub, which means that 3.0 devices connected through a 3.0 hub may not work correctly. Change-Id: Ie0b82dca23b7a750658ccc1a85f9daae5fbc20e1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170666 Reviewed-by: Kees Cook <keescook@chromium.org> (cherry picked from commit ecec80e062f7efe32a9a17479dcf8cb678a4a98b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6780 Tested-by: build bot (Jenkins)
2014-09-04drivers/gma: remove unused codeRonald G. Minnich
We had brought this code in from the kernel but found it best to use mainboard- or chipset specific versions. Firmware should strive to be as non-generic as possible. Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172625 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7dba0dfd25bf9e367f9e5128b15edb018e958c3a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-04libpayload: usb: Unify USB speed between XHCI stack and USB coreJulius Werner
This patch removes the confusing concept of a special "xhci_speed" with a different numeric value from the usual speed used throughout the USB core (except for the places directly interacting with the xHC, which are explicitly marked). It also moves the MPS0 decoding function into the core and moves some definitions around in preparation of later changes that will make the stack SuperSpeed-ready. It makes both set_address implementations share a constant for the specification-defined SetAddress() recovery delay and removes pointless additional delays from the non-XHCI version. Change-Id: I422379d05d4a502b12dae183504e5231add5466a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170664 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit f160d4439c0d7cea1d2e6b97207935d61dcbb2f2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-03lint: simplify board-status checkPatrick Georgi
git can do lots of things by itself, no need to parse its output and redo that. Change-Id: Id2cdd2ea8d34c1ba2b0abddc88e1f3260d74f47d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6798 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-02acpigen: Correctly handle root scopeVladimir Serbinenko
Change-Id: I9b3c9109b01e348259e64e93a4397212216ab152 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-02smbios.c: Fix mismerge which led to laptop being default typeVladimir Serbinenko
Change-Id: I97ccd08a5e7f094908ed3a85ddae53b158124995 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-02acpi_tables: Remove roda-specific access to 60f [copy-paste error]Vladimir Serbinenko
Change-Id: I12ce0dda823d7733c473ed5ef3b0470d95d794ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6805 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-01google/link: Use common i915_reg.h.Vladimir Serbinenko
Checked by comparing binaries and seeing no differences other than build info. Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-01stout: Kill dead i915 filesVladimir Serbinenko
Not referenced anywhere. Change-Id: I6529f2ecbc34a2fa9ca720fea1224670eb98bdcd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-01lenovo/x60: Remove leftover declarationVladimir Serbinenko
Change-Id: I1ab2118a3127dfacef6a389abd59050493e640fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6817 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-01AMD Steppe Eagle: Update reference to BLOBs repo (3rdparty)Bruce Griffith
The BLOBs repo has been updated with AMD PI header files, peripheral BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for Steppe Eagle, the Steppe Eagle video BIOS, and platform security processor firmware. Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-31samus: Change SPD to indicate LPDDRDuncan Laurie
There is some magic new SPD SDRAM type 241 to indicate LPDDR. I cannot find it specificed in any JEDEC document but it is what the reference code uses. Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6777 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-31libpayload: xhci: Ensure to reset dequeue pointer on stopped endpointsJulius Werner
This patch fixes a bug in the XHCI stack that occurs when a multi-TRB TD times out before the last TRB is processed. The driver will correctly issue a Stop Endpoint command in that case, but the xHC will still preserve the transfer state and just pick up right after that on the next doorbell ring. It will then process the leftover TRBs from the old TD the next time a transfer is issued. (cf. XHCI 4.6.9) We fix this by changing the existing xhci_reset_endpoint() calls in transfer functions to not only trigger on Halted (2) and Error (4), but also on Stopped (3). That function will not actually issue a Reset Endpoint command in this case, but it will nuke the whole transfer ring and issue a Set TR Dequeue Pointer command, which is sufficient (though slightly overkill) to solve our problem. Change-Id: I3abbe30ff9d4911a8af1f792324e018d427019e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170833 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Kees Cook <keescook@chromium.org> (cherry picked from commit f12424af0e29ac12963e8e5a7970fadcc0bb6cee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6787 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-31lenovo/x200: Kill access to nonexisting device [copy-paste error]Vladimir Serbinenko
Change-Id: I1be939e870e8792f5ebb23623fe8f7f119adec36 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6806 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-31iWRainbowG6: Kill unused fileVladimir Serbinenko
Change-Id: I7b9b91519d87d70405b57920b3f1ab98c50526d1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30smbios: reorganise OEM strings handling.Vladimir Serbinenko
OEM strings should not be handled by mobo code but by common code with strings collected from all devices. Change-Id: Ibde61a1ca79845670bc0df87dc6c67fa868d48a9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6788 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-30ec/lenovo/h8: Implement thinkpad-acpi compatible LED functionVladimir Serbinenko
Change-Id: I9998b0b4a1413ab65f1dbdf59b2f84d331ce9c3d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30ec/lenovo/h8: Rename LED to avoid conflicting with thinkpad-acpiVladimir Serbinenko
Change-Id: I9fd7f894d0e611f61e8702e4eacb12d7b81154d8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30lenovo: Read mainboard version from AT24RF08C.Vladimir Serbinenko
Tablets have different mainboard version than laptop variants. Change-Id: I77a1e2b50d30dcf3fa064e0c378ceca7ccf96e89 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6785 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-30lenovo/h8: Support tablet eventsVladimir Serbinenko
_QXX numbers are determined experimentally, hotkey scancodes from thinkpad-acpi module. Change-Id: I1f7548ef62529ae25dcdcbed0fc74390b7529a2e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6765 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30AMD Steppe Eagle: CPU files for new SoCBruce Griffith
Add the CPU files required to support the Steppe Eagle and Mullins models of Family 16h SoC processors from AMD. This CPU is based on the Jaguar core and is similar to Kabini. Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6679 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30AMD Steppe Eagle: Add northbridge files for new SoC familyBruce Griffith
Add the northbridge file for AMD's new Mullins and Steppe Eagle processor family. Since the processor family name is not the same across AMD's sales and marketing channels, I have elected to use part of the processor ID as the family name. The intent is to reduce confusion since the processor ID is the same for both families. This northbridge support has only been validated on the AMD Embedded variants ("Steppe Eagle"). The AGESA wrappers in coreboot have a function that is intended to mirror the UMA memory allocation performed during memory initialization by AGESA. Update the Steppe Eagle memory allocation to mimic the memory reservation done inside the AGESA BLOB. Change the default CBMEM address, the default video BIOS device ID, and a couple of other defaults to match changes in coreboot community code. The northbridge chip.h specifies how many processor sockets, how many channels, and how many DIMM slots are supported by the northbridge. Steppe Eagle does not permit multisocket systems and has only one memory controller channel. Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6678 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30AMD Steppe Eagle: New integrated southbridge (Avalon)Bruce Griffith
00730F01 contains the Avalon southbridge and a Platform Security Processor (PSP). Supporting the PSP requires specific binaries to be included in the ROM. The fletcher utility is used to sign PSP binaries. The IMC access routines are not accessible for newer AMD parts that use pre-compiled AGESA. Change the Hudson code such that the IMC code is not compiled if IMC is not selected in Kconfig. Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled. The newer AMD mainboards will initially be released without ACPI resume support (S3) due to the use of AGESA internals in the existing Hudson routines. The Makefile change allows newer mainboards to avoid the API issues. Change Kconfig such that the FWM flag is always set for PSP-enabled parts. This has the side effect of forcing the generation of the FWM directory in the absence of GEC, IMC, and xHCI. Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6677 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30AMD Steppe Eagle: Add binary PI vendorcode filesBruce Griffith
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. The AGESA dispatcher is built using its own rules rather than generic library generation rules in coreboot/Makefile and coreboot/Makefile.inc. The AGESA source files are initially copied from whereever they live into coreboot/build/agesa. They are compiled from there. The binary PI directory has a mandatory structure that places the AGESA BLOB into the same directory as the support headers. These will nominally be placed in the 3rdparty directory in coreboot.org. The copy commands that were added to the the vendorcode Makefile.inc ensure that only one thread will operate on each source file by using a macro to generate the copy targets. After the change, each copy target will operate on exactly one source file. Due to API issues, coreboot has no way to control the IMC to set up fan control. Set a Kconfig flag that removes the ability to install an IMC BLOB into CBFS. Change-Id: I050b72a19086aaeba6cb65ce165297b10e3cfc45 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6595 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30lenovo/x220: New portVladimir Serbinenko
Change-Id: Ic213948e4d31457dda9b9f2d5a4f92cd34d1e57d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6757 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30sandybridge: Add native sandybridgeVladimir Serbinenko
Change-Id: I1b51310b4387e588c4828563620b0e2770598503 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6753 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30AMD Steppe Eagle: Add 32-bit Fletcher's Checksum computationBruce Griffith
The AMD Platform Security Processor (PSP) requires a Fletcher's Checksum at the end of the PSP directory. This code implements a Fletcher's Checksum by reading bytes from stdin and writes the bytes back to stdout with a checksum inserted into the byte stream at the appropriate offset. This utility is used on PSP binaries during coreboot build. Include a runtime debug option such that the command: fletcher --print <file.bin >file_with_cksum.bin will print out the computed checksum value for debugging. The compile-time debug option is retained that allows -DDEBUG to be added to the compilation line. This option has the same effect as "--print". Change-Id: I506a479d8204ca4f8267d53aa152ac4b473dbc75 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6676 Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-29smbios: Define and use enclosure types.Vladimir Serbinenko
Change-Id: Ib5b92120cbe2ca41c9813e8caeb03161f4d3954c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6786 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-29samus: Add ACPI MADT interrupt override for GPIO IRQ 14Duncan Laurie
This interrupt needs to be specified in the MADT before it can be used by the kernel driver. Change-Id: Ic920a792a203cb06cd4529815680584a21532106 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6778 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29samus: Add coreboot boardDuncan Laurie
Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-29tegra124: add custom uartGabe Black
tegra124: Add a test function which spams exclamation points on the UART. This function spews characters on the console and, until we have a working console, is an easy way to see whether the system boots to a particular point. For some reason waiting for transmitter to be empty hangs, but transmitting characters still works. Old-Change-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171030 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e0059181958cfe8afec2f3a7ea732e81f5d55e5d) tegra124: Re-enable waiting for the transmitter to empty in the test function. The compiler was emitting code compatible with armv7-a, but the bootblock was running on a core which uses armv4t. By coincidence, it was emitting an instruction which is unavailable on armv4t when checking the value of the UART's LSR register. Now that the bootblock is compiled with more appropriate flags, this code can be re-introduced. Old-Change-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170997 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2a0adceb5029c8ee633d17c82dbb11e48d30349d) tegra124: Seperate out the non-UART specific hardcoded init in the bootblock. The hardcoded init in the test function in the bootblock is actually useful generally because it doesn't belong in the UART driver itself but is necessary for the UART to work. Until we have real implementations for the pinmux, etc., we can use that code to get the UART and console going. Old-Change-Id: I2efe0b571d8b022eb2a2e5569620558540b28373 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171334 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ae7d4d890be1936cc86dc15adeb33f3b46a51ae5) tegra124: Implement and enable serial console support for tegra124. The driver is very similar to the 8250 driver, except it isn't in two parts, and it also spaces its registers 4 bytes apart instead of having them directly adjacent to each other. Also, eliminate the UART test function in the bootblock. It's no longer needed since the actual console output serves the same purpose. Right now the clock divisor is fixed for now, and we'll want to actually figure out what value to use at some point. Old-Change-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171337 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 86f5e2875b18901b349283cfbcd4f8cc88b7a019) Squashed 4 commits related to uart support for tegra124. Modified the new uart.c to look like the uart.c for exynos5420. Change-Id: I490cba014a43d58c30c48ca9ddcae2b00095b7a6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6764 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-29exynos: Fix the name of the chip_operations structures.Gabe Black
The exynos directories had been moved from src/cpu to src/soc, but the name of the chip_operations structure wasn't updated properly. That meant that the SOCs never installed their memory resources and the ram stage would fail to load the payload. Change-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172400 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9100d475ebcc4dae23184583a6cc0162577e70d1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6781 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29arm: libpayload: Make cache invalidation take pointers instead of integersJulius Werner
This minor refactoring patch changes the signature of all limited cache invalidation functions in coreboot and libpayload from unsigned long to void * for the address argument, since that's really what you have in 95% of the cases and I think it's ugly to have casting boilerplate all over the place. Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167338 (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6623 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28soc/intel/baytrail/Kconfig: Remove empty line at top filePaul Menzel
Change-Id: I932e4566ec6313a7f2dbd58784bde71bca12abd7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6671 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28qemu: log acpi table sizeGerd Hoffmann
Change-Id: Ib2d7a3d9bda94f80886da96c2b766d29fc15a834 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/6772 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28qemu: fix cirrus buildGerd Hoffmann
commit 9518b56 (intel/gma: Clarify code and use dedicated init for Google Peppy) changed "struct edid" and thereby broke the build. Adapt drivers/emulation/qemu/bochs.c to the changes to fix this. Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y. Change-Id: I2d3cecde21d495e9b99ff8d2f741f8a462c75a4d Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/6771 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28qemu: fix bochs buildGerd Hoffmann
commit 9518b56 (intel/gma: Clarify code and use dedicated init for Google Peppy) changed "struct edid" and thereby broke the build. Adapt drivers/emulation/qemu/bochs.c to the changes to fix this. Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y. Change-Id: Ic295c6d31284555e1463af5bca673231b8722d54 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/6769 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLEGabe Black
While the 8250 compatible serial port driver is primarily useful on x86 systems because it works with the legacy x86 com ports, some devices which aren't x86 based have 8250 compatible UARTs as well. This change renames the CONFIG_X86_SERIAL_CONSOLE option to the more general and direct CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86 systems can enable the driver, although it will default to on on x86 and off otherwise. Also, the default IO port address that's added to the sysinfo structure on x86 and which is intended to be overwritten by a value in the coreboot tables is not used on ARM. That variable is adjusted so that it's more clear it's a default value, and made dependent on x86 since that's the only place its value is actually used. Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170834 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6655 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-28tegra124: Add a custom bootblock implementation.Gabe Black
This implementation is the same as the general one except that it removes all the things that don't work on an ARMv4. Change-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171019 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1436288d3b025af27a8d28ba94b589940ead504) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28ARM: Make it possible to use a custom bootblock implementation.Gabe Black
Tegra needs to use a custom bootblock implementation because it starts on a coprocessor which uses ARMv4. It doesn't have the same control registers, caches, etc., and the regular bootblock gets exceptions and dies. Change-Id: Id197db2939bc840ad64244d6e2017fc5c89e0cbd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171018 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a66393fdd6fe68757e394b8a611e610f1938771d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-28Peppy/Haswell: move more support functions from mainboard to the intel i915 ↵Ronald G. Minnich
driver Move (and rename to make it clearer) the function that computes display parameters from the dpcd and edid. Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171366 Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6768 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-28libpayload: usb: Allow direct instantiation of MMIO host controllersJulius Werner
The existing USB_MEMORY mechanism to instantiate non-PCI host controllers is clunky and inflexible... most importantly, it doesn't allow multiple host controllers of the same kind. This patch replaces it with a function that allows payloads to directly instantiate as many host controllers of whatever type they need. Change-Id: Ic21d2016a4ef92c67fa420bdc0f0d8a6508b69e5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169454 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit b6e95c39dd91f654f0a345f17b3196f56adf4891) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-27libpayload: Add ARM defconfigPatrick Georgi
make junit.xml tries to build it, but fails (ARM port doesn't seem to be ready?) Useful test case to demonstrate a failing libpayload build. Change-Id: Iba4fe551b48f631e6a3bd90eb07930fc70761332 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4552 Tested-by: build bot (Jenkins) Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-27rmodtool: correct final memory size calculationAaron Durbin
Apparently when I originally wrote this I confused myself to no end. The code/data of an rmodule has a set memory size which is associated with the .payload section. The relocation entries may increase the overall footprint of the memory size if the rmodule has no bss but a lot of relocations. Therefore, just compare relocation entries size plus the file size of the .payload section with the memory size of the paylod section. The .empty section is added only when we have not met the final target size. Change-Id: I5521dff048ae64a9b6e3c8f84a390eba37c7d0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6767 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-26armv7: Move Exynos from 'cpu' to 'soc'.Hung-Te Lin
The Exynos family and most ARM products are SoC, not just CPU. We used to put ARM code in src/cpu to avoid polluting the code base for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs (including intel/baytrail) in coreboot. Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c Reviewed-on: https://chromium-review.googlesource.com/170891 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6739 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-26util/inteltool: fix typoIdwer Vollering
Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/6766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-26Peppy, Haswell: refactor and create set_translation_table function in ↵Ronald G. Minnich
haswell/gma.c The code to set the graphics translation table has been in the mainboards, but should be in the northbridge support code. Move the function, give it a better name, and enable support for > 4 GiB while we're at it, in the remote possibility that we get some 8 GiB haswell boards. Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171160 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit d5a429498147c479eb51477927e146de809effce) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6741 Tested-by: build bot (Jenkins)
2014-08-25xcompile: always use -march=i686Aaron Durbin
When compiling coreboot for x86 on gcc the compiler is free to pick whatever defaults it is using at the time of gcc's compile/configuration when no -march is specified. Not properly specifying -march then opens up the use of SSE instructions for compilation units it should not be used such as the SMM module as this module doesn't save/restore SSE registers. Change-Id: I64d4a6c5fa9fadb4b35bc7097458e992a094dcba Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172640 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit d49358f7959bb52c3e7ff67d37c21a1b294adf72) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6716 Tested-by: build bot (Jenkins)
2014-08-25intel/gma: Clarify code and use dedicated init for Google PeppyRonald G. Minnich
Peppy had some issues with FUI. We decided it was time to create peppy-specific gma.c and i915io.c files. Using yabel and the i915tool, we generated a replay attack, then interpolated against the slippy i915io.c to get something working. Also, in preparation for moving code out of the mainboard gma.c to generic driver code, we got rid of some hardcodes in the mainboard gma.c that have no business being there. The worst were the computation of gmch_[m,n] and it turns out that we had some long-standing bugs related to confusion about 'bpp'. I've killed the word bpp everywhere I could because there are at least 3 things that correspond to bpp. We now have framebuffer, pipe, and panel bpp. The names are long because I want to avoid all the mistakes we've all been making in the last year :-) Sadly, that means a lot of changes not just peppy-related, but they are simple and in a good cause. The test pattern generation is driven by a global variable in mainboard/peppy/gma.c. I've found in the past that it's very useful to have a function like this available, as one can activate it while using a jtag debugger: halt at the right place in ramstage, set the variable to 1, continue. It's not enough code to worry about always including. The last hard-codes for M and N registers are gone, and the function to set from generic intel_dp.c code works. To avoid screen trash on a dev mode boot, which we liked but nobody else did :-), we now take the time to put a pleasing background color that sort of doubles as a power LED. Rough timing is ramstage start is at 2.2, and dev setup is done at 3.3. These new platforms are depressingly slow to boot. Rom init alone is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash prompt. These CPUs are at least 10x faster and take much longer to get going. Future work, once we get this through, is to move more functions to the intel driver, and combine the mainboard i915io.c into the mainboard gma.c. That separation only existed because i915io.c was generated by a tool, and it had lots of ugliness. Most ugliness is gone. Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/170013 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> (cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d) snow: Fix a typo in devicetree.cb that was breaking the snow build. A typo in a recent change broke the snow build. Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171014 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 154876c126a6690930141df178485658533096d2) Squashed a fix into the initial patch and updated nehalem/gma.c to have a non-static gtt_poll. Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6657 Tested-by: build bot (Jenkins)
2014-08-25sandybridge: Show spew raminit messages only with raminit debugVladimir Serbinenko
Change-Id: Ifbc59c28c8d8bd844801da9cb869c5dfbda09168 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6754 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-25AMD Steppe Eagle: Add northbridge HT link ID to pci_ids.hBruce Griffith
Add a #define for the HT northbridge link ID into the "known PCI device IDs" table. Change-Id: If0a32b2af5df6c20e0fb5af200c06d80fab3637a Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6680 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25UART 8250: Unconditionally provide register constants and use UART8250 prefix.Gabe Black
The register indexes and bitfield masks were guarded by the UART8250 config options, but it might be (is) necessary to use them in a driver that is UART8250 like without actually using the 8250 driver itself. To avoid any name collision with other drivers, also change the constant prefix from UART_ to UART8250_. Change-Id: Ie606d9e0329132961c3004688176204a829569dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171336 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6715 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-25delay: Have mdelay() / delay() available in romstage, tooStefan Reinauer
Some drivers (like the I2C TPM driver) call mdelay instead of udelay. While it's a shame that these chips are so slow, the overhead of having those functions available in romstage is minimal. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I1fa888fc5ca4489def16ac92e2f8260ccc26d792 Reviewed-on: https://chromium-review.googlesource.com/167542 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7083b6b843d803bd4ddbd8a5aaf9c5c05bad2044) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6531 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-25lenovo/t520: update KconfigNicolas Reinecke
override default ivy VGA_BIOS_ID add model & part number Remove ARCH_X86 as is in, fd33781 Move ARCH_* from board/Kconfig to cpu or soc Kconfig. Change-Id: I61dc6434de7af2d8672f784df87a8b9d3f0fb068 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6759 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25lenovo/t520: fix PCIe interrupt and function disable configNicolas Reinecke
Change-Id: I33e71c0a246583885368dc3d3af761c190b2fb5c Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6758 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-25lenovo/t5x0: replace invalid config DRAM_GATE_GPIONicolas Reinecke
Change-Id: I3b13bddfc127353e0c13d8d2ae7918d5c3deb72c Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6760 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-25lenovo/x230: Add subsystem ids.Vladimir Serbinenko
Change-Id: I917a89da50d8efe998c368ba46206f2a1c580fd0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6756 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25lenovo/t530: Be safe by disabling blink gpio hw with a writeoutEdward O'Callaghan
This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6436 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-25sandybridge: Native gfx init.Vladimir Serbinenko
Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-24lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h headerEdward O'Callaghan
Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6435 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-24lenovo/t530/romstage.c: Trivial - move include to topEdward O'Callaghan
Change-Id: I6b80ad0da39e93072e28b48c40e1c71602133e7b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6750 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-24lenovo/t520: replace dumped GPIO values with gpio.hNicolas Reinecke
GPIO pin wireing information from schematic Change-Id: I2d8dca151b6fbc15e0184ea07596039570843cda Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6740 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: fix devicetreeNicolas Reinecke
SATA Port documentation PCIe unused ports and documentation T520 have no keyboard backlight Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6743 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: fix usb config & documentationNicolas Reinecke
Change-Id: I71398ab2d7ef5b9256795861dd2bebbb0cf32d5f Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6742 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-23ec/lenovo/h8/acpi/systemstatus.asl: Fix typo in o*n* in commentPaul Menzel
Change-Id: I655536f64faaa7e1600d4fec62ba80730e2cc45a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6674 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: Remove empty smi.hNicolas Reinecke
Change-Id: I60fa19b72f91f16db5f354aeec631f661e3494d3 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6736 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: Fix ExpressCard hotplugNicolas Reinecke
Thinkpad T520 ExpressCard Slot PCIe lanes are connected to port 4. Tested with Serial Port Card. Information read from schematic / lspci Change-Id: I459943d427578d135f9aed1aa66da269ddfeee87 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6735 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23superio/smsc/sch4037: Cleanup and fix .c inclusionEdward O'Callaghan
Clean up both ram and rom stage support and fix board to match. Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6509 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-23superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c includeEdward O'Callaghan
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6463 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-22ARM: Overhaul the ARM Makefile.Gabe Black
The ARM Makefile was copied from x86 and then modified, and as a result it was carrying a lot of baggage. On top of that, the extra complication made it inflexible, and we need a lot of flexiblity in order to support the fact that the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main CPUs. Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171017 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-22elfheaders: fix 64-bit ELF writingAaron Durbin
The sh_flags for a 64-bit section header entry are 64-bit in size. Correct this. Change-Id: I2fa79d9a0fb46cc1dfa97c172357bbd2394843e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6737 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-22Remove dead video.aslVladimir Serbinenko
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22lenovo/{x230,t530}: Remove empty smi.hVladimir Serbinenko
Change-Id: I26fa6508f50faff7f1c1724884b5ffa30463b896 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6728 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22lenovo/x230: Remove empty mainboard.aslVladimir Serbinenko
Change-Id: Ic877d6285ce3983268b16ddb5b4e15743f5adf86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6727 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22lenovo/x200: Remove empty mainboard.aslVladimir Serbinenko
Change-Id: I560d693d0d72ca8dcd099eff6b0c40716fb0c0b0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6726 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22lenovo/x200: Move video ASL code to northbridge.Vladimir Serbinenko
Change-Id: I58760500252e78da947685c18201b6d446368333 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6729 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22lenovo/x201: Remove empty mainboard.aslVladimir Serbinenko
Change-Id: I37d48279b1b022c4573bd09d3db6bf536d5dab9a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6724 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22apple/macbook21: Remove useless seabios configVladimir Serbinenko
Change-Id: If771a84f25710e1fb2228816e3ca0139e2f95aa7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6732 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22lenovo/t530/mainboard.c: Add EC info to SMBIOSEdward O'Callaghan
As is in: 91175bb lenovo/x201 & x230: Add EC info to SMBIOS This is needed for the Linux driver for the Lenovo's to properly attach. Change-Id: Ib910b25f392d9d3d6362b6909ce9fd4eeae9a096 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 05:40:48 +0000