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2015-04-04samus: Set codec PDM clock output to 3MHzBen Zhang
Currently the rt5677 codec outputs 6MHz PDM clock which is out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS pin is pulled down to PGND with a 47k resistor, so the expected PDM clock is 64*FS (~3MHz) according to its datasheet. The corresponding kernel patch that adds the PDM clock config option is https://chromium-review.googlesource.com/#/c/230303/ BUG=chrome-os-partner:33303 BRANCH=samus TEST=flash coreboot with this patch and see PDM CLK went from 6MHz to 3MHz on samus with a scope. Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648 Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230344 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: fix typo in pei_dataDuncan Laurie
This was copied and pasted more than it should have been... BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5008f2992d8ab3b952042415af6d7844788e14fc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bff4570dffa413c4fc4dfd8c49920f6b951e944a Original-Change-Id: I2af9a30f3df733af147e8759f78a9802d2296c0f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Add USB3 PHY tuning fields to PEI DATADuncan Laurie
These are board specific adjustments that can be made for each USB3 port. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change touchscreen bootloader mode i2c addressDuncan Laurie
This value apparently changed to 0x27 in the hardware but was never adjusted in firmware. BUG=chrome-os-partner:33790 BRANCH=samus TEST=build and boot on samus Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GSPI0 interfaceDuncan Laurie
This will be connected to the coded for firmware upload. BUG=chrome-os-partner:33495 BRANCH=samus TEST=build and boot on samus, check that GSPI driver is loaded Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5 Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228835 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9273 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen
BRANCH=master BUG=chrome-os-partner:33113 TEST=Build a image and test on Rambi. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I37add87e6fd3e7ad4eee09b8e0b312a2a89c7948 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 59b4c94be46b4397de7cb32726da9fa216e75a4c Original-Change-Id: I22c8f9730cc0e1ecc991f2dd7f2a1e7c548a1789 Original-Reviewed-on: https://chromium-review.googlesource.com/226654 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GPIO9 as touchpad wakeDuncan Laurie
With EVT2 systems GPIO9 is now used for touchpad wake. BUG=chrome-os-partner:32232 BRANCH=samus TEST=suspend/resume by touchpad on samus, with kernel workaround to disable setting of T19 in atmel driver mxt_suspend() 51 | 2014-11-03 12:41:34 | ACPI Enter | S3 52 | 2014-11-03 12:41:37 | ACPI Wake | S3 53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9 Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7 Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227157 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Update thermal max for broadwellDuncan Laurie
Broadwell Tj_max is 105C, update accordingly. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus Change-Id: I001e17287ebbcbfdd909428e149a95878734dab9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fb1de7a9e1d84f592b785a1b495e4aaf434f23a2 Original-Change-Id: If6a3fd682f4ee9b8010982870a61b76e33010fd4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Assign GPIO2 to HP_AMP_SHDN_LBen Zhang
BUG=chrome-os-partner:29649 BRANCH=samus TEST=Audio playback to headphone works Change-Id: I35efa3b97abbba50cbee4c25acfaeb155fc1238f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e2c0ede19c6b700c8d0bf01ff9d3a54984c5d784 Original-Change-Id: Ib51aace52026688dc8972047e5d934c80138ff80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221294 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9269 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Make codec interrupt active highBen Zhang
The codec interrupt needs to be active high because multiple interrupt sources share this line: 1) Headphone plug detect 2) Mic present 3) Hotword detect These interrupt sources are OR-ed together. BUG=chrome-os-partner:29649 BRANCH=samus TEST=Jack detection works on samus Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980 Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220588 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510 Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380 Original-TEST=Build a BIOS image and check the value is applied correctly. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43 Original-Reviewed-on: https://chromium-review.googlesource.com/220475 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3 Reviewed-on: http://review.coreboot.org/9267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform data for jack detectBen Zhang
GPIO IRQ support has been added in upstream rt5677 driver, with new jack detect platform config options. BUG=chrome-os-partner:29649 BRANCH=samus TEST=headphone and mic detect works on Samus Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502 Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224513 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9266 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change GPIO controller label to INT3437:00Duncan Laurie
This matches the label exported by the GPIO controller in the kernel and allows more speicific matches if there are other devices that also export GPIOs. BUG=chrome-os-partner:33098 BRANCH=samus TEST=crossystem wpsw_cur returns 1 Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14 Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224136 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable update screen for software syncDuncan Laurie
Since the PD software sync is slow enable support for displaying a screen telling the user that something is happening. BUG=chrome-os-partner:32379 BRANCH=samus TEST=manual testing: 1) in normal mode, with EC/PD in RW, ensure that they are rebooted to RO and the VGA Option ROM is loaded and the wait screen is displayed, and then the system is rebooted at the end and the VGA Option ROM is not loaded. 2) same as #1 with EC/PD in RO already, same result 3) same as #1 with system in developer mode, same result except there is no reboot at the end of software sync 4) same as #1 with system in developer mode and EC/PD in RO, ensure that there is no extra reboot at the beginning or end of software sync. Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2 Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223850 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add smbios_mainboard_version to define board versionDuncan Laurie
Instead of having this in mosys just have coreboot report the board version in SMBIOS tables. BUG=chrome-os-partner:32359 BRANCH=samus TEST=build and boot on samus, check /sys/class/dmi/id/product_version Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89 Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Fix building with USE=quiet-cbDuncan Laurie
This function needs to be available in different LOGLEVELs. BUG=chrome-os-partner:28234 BRANCH=samus TEST=USE=quiet-cb emerge-samus coreboot Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221540 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9262 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform info in ACPIDuncan Laurie
This is the specific codec setup platform data for samus. BUG=chrome-os-partner:29649 BRANCH=samus TEST=emerge-samus coreboot Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221539 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Drop (empty) google/snow mainboard directoryStefan Reinauer
Snow was renamed to daisy a long time ago. The only reason, it seems, the directory was still there, was a stray board_info.txt file that probably went in shortly after the rename. Change-Id: Iba08665e8486fcfeb214fcd05206a5f5683aea82 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9302 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04arm64: make secmon link with the manual templateAaron Durbin
Secmon needs a special build rule because of the objcopy -B operation required to include it in ramstage. Utilize the manual template so builds continue to work with upcoming build chnages. Note: secmon is actually missing symbols still so those still need to be addressed. That looks to be as if --gc-sections isn't be honored, but I'm actually thinking the symbols are just erroneously carried over as the references for these symbols don't show up in the symbol table: U coreboot_build U coreboot_extra_version U coreboot_version U default_baudrate U lb_add_console U lb_add_serial U uart_baudrate_divisor Change-Id: I41c75e93536b73c4304ef3a87dc39d448d1f00d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04armv4: Add verstage to armv4Furquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I7735a2148da5330f220bd9a87b09e9fe3e37ffd1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5e43dfe1aab813f45f1123b0e2432cdab5738d87) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If3d89ab79bae6d8f1b6f2d89b7693a79dca02476 Reviewed-on: http://review.coreboot.org/9252 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-04armv7: Add config option guard for verstage classFurquan Shaikh
Add files to verstage class depending upon value of CONFIG_ARCH_VERSTAGE_ARM_V7. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I60fb8390abd9d378e38511d4f4ac323b43450232 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221321 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4889cb73b0579155c083bb5fa2895b4d52ab0a56) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iea788ed72344343b2e7a3d91cd7f27ce20f4f177 Reviewed-on: http://review.coreboot.org/9251 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-04tegra124: use known-good drive for fast-train onlyNeil Chen
A higher drive setting is used for fast link training, once the link training succeeds, a known-good drive setting will be used for the main stream transactions. For full link training sequence, the sink devices may ask for a preferred drive setting, thus this drive setting should be used for the main stream transactions too. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219544 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6 Reviewed-on: http://review.coreboot.org/9248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04tegra124: add support for full DP link trainingNeil Chen
The original dp driver supports only fast link training and a special drive setting is used for the link training sequence. This might not be accepted by all panels. The better way is to go through full link training sequence to negotiate for a best drive setting. With the change, dp driver will try fast link training first, this is same as before. If it fails in fast link training, will try full link training. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219543 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 24966517d41252384af3c2784def36aebad42434) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c Reviewed-on: http://review.coreboot.org/9247 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-04rk3288: Replace SPI fifo_size with constantDavid Hendricks
rockchip_spi_slave has a fifo_size member which doesn't change. This just replaces the struct member with a #define. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9 Original-Reviewed-on: https://chromium-review.googlesource.com/220471 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit f76cce3b38ac37f4df8abf6eebb8f7c7b29da095) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3ab4eecfcce98aff3f6c9bd8f6c4e589784c60be Reviewed-on: http://review.coreboot.org/9246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04rk3288: Pass SPI bus speed in as parameter to init functionDavid Hendricks
This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c Reviewed-on: http://review.coreboot.org/9245 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04build system: Introduce manual file typePatrick Georgi
It's used for files with custom build rules, eg. the objcopy stuff surrounding smm and sipi_vector. Change-Id: Ie9ab4c9c6008ca42f82f768c5f33f90c7f5f4db5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9287 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04build system: Allow defining generic rulesPatrick Georgi
Provide a mechanism to define rules that apply for a given filetype (.c, .asl, ...) across all classes (ramstage, ...) Change-Id: If45c526d294e0374c32efef01f0213c6b78b1e43 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9286 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04build system: create proper dependency filesPatrick Georgi
Tell gcc what to use as target part of the generated rule. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Ie4814143337abb3cf1e9e8db7e96201a517a17b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9285 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04x86: rename ldscript_failover.ld to failover.ldPatrick Georgi
The ldscript_ prefix is redundant. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I0f005c0c2abe2fdd6911a2c579cb7ec49ae5c0b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9284 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-03tegra132: implement platform_prog_run()Aaron Durbin
The tegra132 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting romstage it runs ramstage from its faster armv8 core. Instead of hard coding the stage loading operations use run_ramstage(). Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8848 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03tegra124: implement platform_prog_run()Aaron Durbin
The tegra124 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting bootblock it runs romstage from its faster armv7 core. Instead of hard coding the stage loading operations use run_romstage(). Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8847 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03rmodule: use struct prog while loading rmodulesAaron Durbin
The rmod_stage_load structure contained the same fields as struct prog. In order to more closely integrate with the rest of program loading use struct prog. Change-Id: Ib7f45d0b3573e6d518864deacc4002802b11aa9c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9143 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03program loading: unify on struct progAaron Durbin
Instead of having different structures for loading ramstage and payload align to using struct prog. This also removes arch_payload_run() in favor of the prog_run() interface. Change-Id: I31483096094eacc713a7433811cd69cc5621c43e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8849 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03program loading: add prog_run() functionAaron Durbin
The prog_run() function abstracts away what is required for running a given program. Within it, there are 2 calls: 1. platform_prog_run() and 2. arch_prog_run(). The platform_prog_run() allows for a chipset to intercept a program that will be run. This allows for CPU switching as currently needed in t124 and t132. Change-Id: I22a5dd5bfb1018e7e46475e47ac993a0941e2a8c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8846 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03program loading: introduce struct progAaron Durbin
The struct prog serves as way to consolidate program loading. This abstraction can be used to perform more complicated execution paths such as running a program on a separate CPU after it has been loaded. Currently t124 and t132 need to do that in the boot path. Follow on patches will allow the platform to decide how to execute a particular program. Note: the vboot path is largely untouched because it's already broken in the coreboot.org tree. After getting all the necessary patches pushed then vboot will be fixed. Change-Id: Ic6e6fe28c5660fb41edee5fd8661eaf58222f883 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8839 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-02pinky: Move some init to mainboard bootblockDavid Hendricks
This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 Reviewed-on: http://review.coreboot.org/9243 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-04-02rk3288/pinky: Move uart address to mainboard KconfigDavid Hendricks
Since the UART which is used for the serial console may change from board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's Kconfig into Pinky's Kconfig. BUG=none BRANCH=none TEST=built and booted on pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34 Original-Reviewed-on: https://chromium-review.googlesource.com/221438 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9 Reviewed-on: http://review.coreboot.org/9242 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02rk3288: remove duplicated #define `PERI_ACLK_DIV_SHIFT`Aaron Durbin
I'm not sure how the build didn't fail before. In either case remove the duplication. Change-Id: I764774f2b8a5839512af3f054b844a1a86efdb45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9244 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02Nyans: replace cpu_reset with hard_resetDaisuke Nojiri
The existing cpu_reset does board-wide reset, thus, should be renamed. BUG=none BRANCH=none TEST=Built firmware for Nyans. Ran faft on Blaze. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9 Original-Reviewed-on: https://chromium-review.googlesource.com/212982 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f Reviewed-on: http://review.coreboot.org/9179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-02Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 Reviewed-on: http://review.coreboot.org/9223 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02pistachio: add gpio type definitionVadim Bendebury
This is necessary to support generic gpio interface in src/lib. This file will be later populated with more GPIO definitions. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I3fa93f1b3b1ce99d921bbfb378b3f7ae4eb652c2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 26f564ee10a770d57cb4af0a8ab5a264aaf1a7cd Original-Change-Id: I68c9c3a28fcc747575436b502cb25b31afed8700 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226181 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02Clean up architecture-specific KconfigsJulius Werner
It's an unfortunate side effect of our different-archs-per-stage mechanism that all src/arch/*/Kconfig files are always parsed with no if blocks to exclude them if they're not relevant. This makes it very easy to accidentally rely on a Kconfig default set by a totally different and not applying architecture. This patch moves a few Kconfigs from ARM and X86 that leaked out like this into a common Kconfig file for clarity. It also gives ARM64 its own BOOTBLOCK_CUSTOM mechanism so that it doesn't leech off the ARM one (currently not used by any board). In the future, we should maybe prefix all options in the arch/*/Kconfig files with the architecture name (such as X86_BOOTBLOCK_NORMAL and ARM_LPAE are already doing), to make it more apparent when they are used in the wrong place. BUG=None TEST=None (tested together with dependent changes) Change-Id: I3e8bb3dfbb2c4edada621ce16d130bd7387d4eb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5528aa9252cdf711af3c160da387c6a7bebe9e76 Original-Change-Id: Ieb2d79bae6c6800be0f93ca3489b658008b1dfae Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219171 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9235 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02build system: extend src-to-obj for non-.c/.S filesPatrick Georgi
It also creates file names in the build directory and with the stage sliced in, but keeps the extension for anything not .c or .S. Also some handling for non-.c/.S files was adapted to match. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: If8f89a7daffcf51f430b64c3293d2a817ae5120f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9175 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-04-02urara: Fix CBFS header definitionsVadim Bendebury
Urara CBFS header configuration is broken. CBFS header needs to be right above the bootblock, and the CBFS data - 0x100 bytes above, to allow room for proper CBFS wrapper structures. Ideally only the header offset should be specified (and even that could be derived from the bootblock size). But this is a more generic problem to be addressed with different architectures' image layout requirements in mind. BRANCH=none BUG=chrome-os-partner:31438 TEST=coreboot image passes the integrity check now (it was failing before because CBGS header was overlaying the bootblock) $ FEATURES=noclean emerge-urara coreboot $ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \ /build/urara/firmware/coreboot.rom.serial $ cbfstool /build/urara/firmware/coreboot.rom.serial print coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100 alignment: 64 bytes, architecture: mips Name Offset Type Size fallback/romstage 0x4100 stage 7100 fallback/ramstage 0x5d00 stage 18995 config 0xa780 raw 2452 (empty) 0xb140 null 1003096 Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67 Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227523 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02urara: Configure UART line control to 8N1Ionela Voinescu
8bit, 1 stop bit, no parity BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed expected console output. BRANCH=none Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226551 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9185 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02mips: do not place branch instructions in branch delay slotVadim Bendebury
A branch instruction in a branch delay slot confuses the execution pipeline and causes an exception. bootblock.S was written 'by hand', has a branch instruction in branch delay slot and includes '.set noreorder' directive, which causes it to crash when trying to branch to main(). Adding a nop instruction fixes the problem. Also adding a nop after the last branch in the file just in case main() returns and the object linked next starts with a branch. BUG=chrome-os-partner:31438 TEST=Running on the simulator can reach main() now Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221421 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9183 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-04-02coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhzjinkun.hong
Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02rockchip: support pwm regulatorhuang lin
BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9240 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02rockchip: support i2c clock settinghuang lin
BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02pinky: Force delay for EC SPI transfersDavid Hendricks
This gives the EC some time to wake-up between asserting /CS and starting a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer on Pinky Original-Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220243 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Commit-Queue: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Change-Id: I103542517d3ebd7da4f0394b3ae4f68f58403b1e (cherry picked from commit bdb67fe489b7cbea7a26492fa0536ca452434052) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9238 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02veyron_pinky: Add rev2 support, clean up mainboard.cJulius Werner
This patch adds support for the board changes in rev2 (board_id = 0001). It also moves the existing mainboard.c code around a bit to group it by component. BUG=chrome-os-partner:32139 TEST=Booted on rev1. Confirmed SD card still works. Confirmed power button was still as broken as before. Original-Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220251 (cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8d3479aa314f8c6f1591c1b69b0a3827234fc730 Reviewed-on: http://review.coreboot.org/9237 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02veyron: select rw romstage using vboot2Daisuke Nojiri
this change makes veyron pinky to select a rw romstage using vboot2. BUG=None TEST=Booted Veyron Pinky. Verified firmware selection in the log. BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> CQ-DEPEND=CL:219100 Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f Original-Reviewed-on: https://chromium-review.googlesource.com/219103 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475 Reviewed-on: http://review.coreboot.org/9234 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02southbridge/amd/pi: Add initialization of 8254 and 8259Dave Frodin
This moves the initialization of the 8254 and 8259 out of the (unmerged) lamar mainboard romstage.c file and into the southbridge code as it is done in the other AMD southbridges. Change-Id: I73b375754ee4a9bf15981f2cd31056d7e04db23e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/9182 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-04-02broadwell: Disable ADSP power gating feature by defaultDuncan Laurie
Disable ADSP D3 and SRAM power gating features by default, and make the devicetree.cb flags into enable flags instead of disable. BUG=chrome-os-partner:31588 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89 Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9218 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add wakeup delay after SPI /CS assertionDavid Hendricks
Some ECs may require a few microseconds to ramp up their clock after being awaken by /CS assertion. This adds a Kconfig variable that can be overridden at the mainboard-level which will force a delay between asserting /CS and beginning a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585 Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220242 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-on: http://review.coreboot.org/9217 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-04-02samus: Fix codec interrupt and add GPIO definesDuncan Laurie
The codec interrupt needs to come from codec GPIO1, so use the HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The This means codec interrupt is GPIO46 which is PIRQO and should be interrupt 30. Also add GPIO defines for the GPIOs attached to the codec itself. These are defined by index, and I used the same "jack detect" and "mic present" indices that were used in baytrail. The codec interrupt to the host is added at index 2 and the hostword detect interrupt to the host is added at index 3. These can be changed as we work through the implementation in the kernel driver. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Id9cb083ddf9df161be314da4148740ed9f4d0fe6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3958efb28813c664a8a4219f78bdd0fcfe75c706 Original-Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220326 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Fix logging of EC wake eventsDuncan Laurie
The EC behavior for reading events from the ACPI interface was broken with this commit: d899fda lpc: ACPI query-next-event drops masked events https://chromium-review.googlesource.com/194935 This is causing no EC wake events to be logged. To make sure they are logged once again set the wake mask before querying for events. Also remove the check for port80 event logging since this is no longer used as we now store the port80 code in CMOS and this is unnecessary commands to do for the resume path. BUG=chrome-os-partner:32462 BRANCH=samus,auron TEST=build and boot on samus, check for EC wake events for keyboard and lid in the event log. Change-Id: Ib46fc00006ff0e5777941fc3ab1d81607359c4cb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b4dccc03bdded8411cc1429521579ea006ec58a7 Original-Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Clean up touch wake sourcesDuncan Laurie
Move _PRW to the ACPI devices for the touchpad and touchscreen. Add a _DSW method, but disable it by default for now until a spurious wake issue can be resolved. BUG=chrome-os-partner:32232 BRANCH=samus TEST=build and boot on samus, ensure trackpad does not spuriously wake the system. Change-Id: I3160248ef6dfeccdec765553643d9b8de2bb2ed1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 85d14842aefdb29c750009c0092f055587172dac Original-Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220325 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9214 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Add event log entry for GPIO27Duncan Laurie
Add event log entry if GPIO27 is used to wake the system. This GPIO is treated separately from other GPE and it is one of the only events that can wake from Deep Sx. BUG=chrome-os-partner:31549 BRANCH=samus TEST=samus: suspend/resume and wake from keypress, check for GPIO27 event in event log. Change-Id: If699640701b0afcd0843c2a99546ee6bb9d09361 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0f1cccfd00552dafbaa91acc362b5e35474c3a95 Original-Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220323 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02arm: Prevent compilation of old, experimental SMP supportJulius Werner
The ARM SMP feature was added a long time ago and has never really been used by anyone since. We are still always compiling cpu_info() even though we don't use it, and it makes some dangerous assumptions about stack alignment that are not guaranteed anywhere. I'm planning to change the way the stack boundaries are defined. Rather than trying to work that into this unsafe, unused and hard to test feature, I think we should just seal it off with police tape and make sure that if anyone ever tries to use it again (which currently seems unlikely), they get forced to do their due diligence on making sure it works as intended. BUG=None TEST=Compiled Veyron_Pinky. Change-Id: Id25545cab88f29200c7672ef02c7804f0ac26399 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 5b517fc46b030a6e50ef2f5e4d4a449b98ce16c6 Original-Change-Id: I8a60bd30e8b27a22bb3da68ca84daea99424dee9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219680 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9222 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Reg_Script: add END tag to array "smbus_init_script"Ryan Lin
Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script. BUG=chromium:416651 TEST=test on Auron. Change-Id: Ieeaf6c705aa673acc9bb2635e103c4148bc8742f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 172c5fc259a2f6d09daccb1fe53fe0aa7c5601e1 Original-Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220934 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Fix and clean up GPIOs and EC info/eventsDuncan Laurie
- Define specific GPIOs in gpio.h instaed of smihandler.c - Add battery status event to SCI list - Remove old proto board version defines and SPD index usage - Do not disable cmd_pwr training now that it works on EVT board BUG=chrome-os-partner:32196,chrome-os-partner:29117 BRANCH=samus TEST=build and boot on samus Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220321 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add battery status event and re-enable _BIXDuncan Laurie
Add a new host event to send a notify(0x80) to the battery when the EC indicates that battery status has changed. The kernel has fixed the bug with _BIX method so it can be enabled now. BUG=chrome-os-partner:32196 BRANCH=samus TEST=build and boot on samus Change-Id: I1b8068df7abf1c8ebdc3a89602896b863accb7f3 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a779fc7f32729adb60d8bc220325444ebc20e0d2 Original-Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220320 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Synchronize for power management with FRCKenji Chen
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build an image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRCKenji Chen
OBFF: Disable it by clearing bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommended setting. BUG=None TEST=Build an image and check the setting are applied correctly on Samus. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Revise programming flow for write-once registersKenji Chen
Extended PCIe Capability and Advanced Error Report locates at offset 0x100 is W/O, and the subsequent write following the 1st write to the register takes no effect. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9 Original-BUG=chrome-os-partner:31424. Original-TEST=Build a image and check the programming value is correct on Original-Samus. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db Original-Reviewed-on: https://chromium-review.googlesource.com/219985 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844 Reviewed-on: http://review.coreboot.org/9209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Configure IOSF Port and Grant CountKenji Chen
Synchronize the code with FRC. Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreboot image and run on Samus to confirm the setting is properly applied. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02vpd: retrieve mac addresses and pass them to bootloaderVadim Bendebury
Chrome OS devices firmware usually includes an area called VPD (Vital Product Data). VPD is a blob of a certain structure, in particular containing freely defined variable size fields. A field is a tuple of the field name and field contents. MAC addresses of the interfaces are stored in VPD as well. Field names are in the form of 'ethernet_macN', where N is the zero based interface number. This patch retrieves the MAC address(es) from the VPD and populates them in the coreboot table so that they become available to the bootloader. BUG=chrome-os-partner:32152, chromium:417117 TEST=with this and other patches in place the storm device tree shows up with MAC addresses properly initialized. Change-Id: I955207b3a644cde100cc4b48e51a2ab9a3cb1ba0 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1972b9e97b57cc8503c5e4dc496706970ed2ffbe Original-Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219443 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Samus: Synchronization with FRC to enable PCIe Relaxed Order.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324 Original-BUG=None Original-TEST=Modify settings, build and update the image to Samus and Original-check the settings are applied to Registers. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Original-Reviewed-on: https://chromium-review.googlesource.com/219073 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31 Reviewed-on: http://review.coreboot.org/9206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Ensure PD controller is in RO mode for recoveryDuncan Laurie
In order to not break FAFT, and to have a quicker recovery mode boot, reboot the PD controller into RO image in romstage. This is done before the EC since rebooting the EC into RO will also reboot the host. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot samus EVT into recovery with 'dut-control power_state:rec' and ensure that the PD controller is rebooted to RO in romstage. Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add support for v3 commands on LPCDuncan Laurie
In order to talk to the PD controller with a passthru command coreboot needs to be able to use v3 commands. The command version is automatically detected based on the advertized flags from the EC. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot on samus EVT Change-Id: I032eb185d80d5b68c82609910045e21d4521afcc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4f664b22645f0def87a73e9255297b3edccf436e Original-Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add commands to check PD image typeDuncan Laurie
Coreboot needs to be able to reboot the PD controller into RO image in recovery mode early in the boot process in order to avoid a lengthy recovery mode boot if it is only done at vboot software sync time. In order to do this a new device index field is added to the command structure which must be initaalized to zero for all EC transactions. This early init and image check code is only used in romstage so include it in the __PRE_RAM__ block. BUG=chrome-os-partner:30079 BRANCH=none TEST=build and boot on samus EVT in recovery mode and see that the PD is rebooted to RO mode early in the boot. Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1 Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Update ec_commands.h from EC repositoryDuncan Laurie
This latest version includes PD passthru support. BUG=chrome-os-partner:30079 BRANCH=None TEST=build and boot on samus Change-Id: Ie718b73a6b125a863ae28e63769dd54edc267f0b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fbca0743a4b45828a466d05afc3a2e94d2e3da2e Original-Change-Id: I79d160219564155008f6231fec35808d1fbd6f04 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218901 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9202 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan
Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands for these processors. Pre-conversion materials are compatible with USB PLL VCO current increase. Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL VCO current. BUG=chrome-os-partner:31199 TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register has new value. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0 Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211337 Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d) Original-Reviewed-on: https://chromium-review.googlesource.com/205970 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217772 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6 Reviewed-on: http://review.coreboot.org/9200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Update PCIe configuration to follow BWGKane Chen
According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeos: Add WiFi calibration CBMEM entry pointer to coreboot tableVadim Bendebury
This patch adds plumbing necessary to ensure that the CBMEM WiFi calibration blobs entry, if present, is referenced if the coreboot table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none - the entry is not yet in the CBMEM Change-Id: I072f2368b628440b6fe84f310eebc1ab945f809e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d0330280369753a6520196425e6dfc7d7bd226a3 Original-Change-Id: I04d52934ad1c5466d0d124b32df5ab17c0f59686 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225270 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9232 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Clear pending GPE events before entering sleep stateDuncan Laurie
In the case of an EC wake event that is pending but not cleared it is possible for the EC wake pin (i.e. GPIO27) to be asserted after the kernel triggers the sleep SMI but before the system goes to sleep. If this happens then the GPE will be reported as a wake source when the system wakes up again. BUG=chrome-os-partner:33218 BRANCH=samus,auron TEST=build and boot on samus, use the keyboard to enter suspend with suspend_stress_test and ensure that only the RTC is listed as a wake source upon resume. Change-Id: Id900132bb81e4cf50885a652ed00a142d951ea4d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 50396ab6a3a3efb3b3dea4f1c2a8f8804fed943e Original-Change-Id: I319dc22e21126a3086415f8f8b2b35eaec66fd50 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225540 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Baytrail: Change PCIe root disable algorithmKenji Chen
Disable Root Port0 only when there is no PCIe device present on any root port. BUG=None TEST=Boot Rambi with PCIe installed/non-installed on RP0 to confirm the RP0 is correctly enabled/disabled. However, I still need someone to help check if RP0(no device) is still enabled if there is device on other RPs since since I have no devices having slots from RP1/2/3. Change-Id: Iae552975250ed6f309c423b847621b8994172891 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217791 Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Baytrail: add _PRT to each PCIe root port deviceTed Kuo
Report PCI routing table of all PCIe root ports for legacy interrupt. Some PCIe devices using legacy interrupt can't work if PCI routing table isn't defined. It's necessary and defined in BWG Chapter 28.1.3. BUG=chrome-os-partner:31943 TEST=compiled and tested BRANCH=NONE Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I2c684edfd1fc624bed471783584250cd9f5e66f5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9040d564a32607327057a84b9aab14e66cd5b45 Original-Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b Original-Reviewed-on: https://chromium-review.googlesource.com/218422 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Ted Kuo <tedkuo@ami.com.tw> Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Reviewed-on: http://review.coreboot.org/9201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Samus: fix unused GPIO pinKenji Chen
Mark GPIO42 as unused according to Samus schematics BUG=None TEST=Make the chnage; Pass the build process; Need someone having the board perform the verification. Change-Id: Ib53a3ae062d414a2c98ec0756e759760d179e3fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4e0f8f3276c575ff60fbda709de5d3cfe31a5900 Original-Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217344 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02ipq806x: provide soc specific CBMEM_CONSOLE_PRERAM_BASEVadim Bendebury
For now storm bootblock runs with DRAM fully initialized, this patch puts the early console between bootblock and rom phase. BUG=chrome-os-partner:31734 TEST=verified that preram_cbmem_console is set: $ grep preram_cbmem_console cbfs/fallback/bootblock.map 40618000 A preram_cbmem_console Change-Id: I2d63f5fde0d3794062068289c648d8bcda11a9a3 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6bdadad3787d6a4a2d4828b0f300455fedca2b8d Original-Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217291 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02smbios: add a family id in smbios type1 familyKane Chen
mosys will use this field to identify system BRANCH=none BUG=chromium:359155 TEST=build ok, use dmidecode to check whether data is written correctly Change-Id: I461215c012b6ad712b3f813a3928e90a23bf54f1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7adbdab761cd7b4bda0a43e7b1c4070de26f150a Original-Change-Id: Icfbd4c61fc49a9cb3d3ecd2b622339957963150c Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217400 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9230 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02vboot: add vbnv flash driverDaisuke Nojiri
this adds a driver for vboot to read and write nvdata in spi flash. it's assumed that flash contents are erased to 1-bits and write operations can only change 1-bits to 0-bits. when all nvram space is used, the driver will erase the whole block and start the next write from the beginning. BUG=chrome-os-partner:32774 BRANCH=ToT TEST=Built for cosmos. Change-Id: I40858f847151aa0770e1101e905476d270550f60 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 09713828b7b0cabd13a08de3f34e32bc4dbef4a4 Original-Change-Id: Ia9049f342b21fa4c289cb7b9254ab89ec1ef1699 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226525 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9229 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02broadwell: Add reporting of broadwell MCH revisionDuncan Laurie
Since the E0 and F0 stepping parts have the same CPUID it is necessary to use the MCH PCI device revision to determine what the actual stepping is. Add this decode table so the early output gives proper identification of the installed CPU type. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus with E0 and F0 parts Change-Id: Idce1e289cd958c77febc87395f27570247512a87 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a5346141e45b105a35a7641f60b29e02ab2bdfa3 Original-Change-Id: I1bc127badd75ecc34d3d2dbae5d272bd4d9f9082 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223158 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9228 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Change CPUID 306D4 to report "E0 or F0"Duncan Laurie
The F0 stepping has the same CPUID as E0 stepping so report it as either stepping to avoid confusion. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I99a83855b4393d736724836b709702417483b5d2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 55ed3bc880c31c0ca5c8a21c335722af05eb57f7 Original-Change-Id: Ia4955f346ceb9be92e06ecea5b7a8fe2db84cabc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: me: Fix typo and add missing phase stateDuncan Laurie
Fix the typo of sate to state and add uKernel phase to just output the current state byte. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5f341ee6c58487aeb927cab0641742cb4071a6b7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de6149508c50d0770fedfbe352e9149abea87b4c Original-Change-Id: I520a4cc75faffa5feeb6113ffd7b07a48c4e6f28 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222677 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02pinky: Enable EC_SOFTWARE_SYNCDavid Hendricks
CQ-DEPEND=CL:218766 BUG=none BRANCH=none TEST=built and booted on Pinky Change-Id: Ib3eed77553433e9f8c70af8b148729e628c95747 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 56b3e8c02a4e45653a5369ce47dcbce0c18f7194 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Icbee95350949bd9bfa4490a8a4b6bbf09beb4170 Original-Reviewed-on: https://chromium-review.googlesource.com/221019 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9224 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02mainboard/asus/kfsn4-dre: Set maximum installable memory to 64GBTimothy Pearson
Change-Id: I480d6bfe29c77119892fcb1fbb9779fd7e3529c3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9139 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-02northbridge/amd/amdfam10: Generate SMBIOS tables for RAMTimothy Pearson
TEST: Booted ASUS KFSN4-DRE and verified SMBIOS contents via dmidecode utility. Change-Id: Id656f2f6cf5a4ecafa03e150ad91f69107a4fe88 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-01mainboard/supermicro/h8qme_fam10: Fix indentations and spellingTimothy Pearson
Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9177 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01x86: set smbios rom size based on CONFIG_ROM_SIZEAaron Durbin
Instead of relying on the CBFS header's romsize field use the CONFIG_ROM_SIZE Kconfig variable. That value is what is used to create the rom file as it is. Therefore, just remove the dependency. Change-Id: If855d7378df20080061e27e4988e96aee233d1e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9130 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-01mainboards/amdfam10: Copy DIMM information to cbmem after romstageTimothy Pearson
src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info() function. Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-01mainboards: fix spd generationAaron Durbin
echo is evaluated by a shell builtin producing non-binary spd data of the form '-e -n \<byte>'. Correct this by using printf builtin which does the equivalent and is more cross platform friendly. Boards changed: gizmosphere/gizmo gizmosphere/gizmo2 google/bolt google/falco google/link google/peppy google/rambi google/samus google/slippy pcengines/apu1 Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9196 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-01cbfs: more accurate size check for simple buffer mappingDaisuke Nojiri
currently, if the cache size is, for example, 4096 byte, mapping 4096 byte data fails due to the overly strict check. this change allows cbfs_simple_buffer_map to use all the cache space to the last byte. BUG=None TEST=Booted Nyan Blaze. BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I0797b5010afd7316fdec605784e8f48e2d62c37f Original-Reviewed-on: https://chromium-review.googlesource.com/218883 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b0b31da336fa2f87fe73f063782d6243f8262d10) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I15e11e574cd14484fe83c9c3674bb5c2d14422f6 Reviewed-on: http://review.coreboot.org/9178 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01northbridge/amd/amdfam10: Collect DIMM information for ramstage useTimothy Pearson
1.) Allow MCT information structures to be copied to cbmem. 2.) Retrieve DIMM vendor, model, and serial information. 3.) Allow maximum installable memory to be set via devicetree. Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9137 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-01northbridge/amd/amdmct: Pack MCT and DCT info structsTimothy Pearson
This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9158 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi
And this path is already included properly elsewhere. Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9174 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01chromeos: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi
Change-Id: I39841c5358c53e6d2325d1304fd6cdfadb7f7ac4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9173 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01build system: make CONFIG_* symbols disappear from objectsPatrick Georgi
We don't actually want to see them in the binaries. Change-Id: I37b53ef7dcbe05d81a8322d528c9aae102115134 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9180 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 15:21:25 +0000