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2019-03-04device/pnp: Add header files for PNP opsKyösti Mälkki
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04Fix indirect include for endianessKyösti Mälkki
The function (preprocessor macro) we need is defined in <endian.h> not <swab.h>. Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-04arch/io.h: Fix PCI and PNP simple typedefsKyösti Mälkki
Provide clean separation for PCI and PNP headers, followup will also move PNP outside <arch/io.h>. Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-04Fix <io.h> includesKyösti Mälkki
These resolved to <device/oprom/include/io.h> which included <arch/io.h> that we really wanted. Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31693 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04mb/google/sarien: Enable MAC address passthru supportDuncan Laurie
Enable the support for providing a MAC address for a dock to use based on the VPD values set in the platform. BUG=b:123925776 TEST=tested on sarien by setting VPD values and observing the string returned by the AMAC() method: > vpd -i RO_VPD -s "ethernet_mac0"="AA:AA:AA:AA:AA:AA" > vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB" 1) Test with no policy set, returns "dock_mac" ACPI Debug: "VPD region RW did not verify" ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB" ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB" ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#" 2) Test with policy set to "builtin", returns nothing > vpd -i RW_VPD -s "dock_passthru"="builtin" ACPI Debug: "Found VPD KEY dock_passthru = builtin" [AMAC returns Zero] 3) Test with policy set to "ethernet_mac0" > vpd -i RW_VPD -s "dock_passthru"="ethernet_mac0" ACPI Debug: "Found VPD KEY dock_passthru = ethernet_mac0" ACPI Debug: "Found VPD KEY ethernet_mac0 = AA:AA:AA:AA:AA:AA" ACPI Debug: "MAC address returned from VPD: AA:AA:AA:AA:AA:AA" ACPI Debug: "AMAC = _AUXMAC_#AAAAAAAAAAAA#" 4) Test with policy set to "dock_mac" > vpd -i RW_VPD -s "dock_passthru"="dock_mac" ACPI Debug: "Found VPD KEY dock_passthru = dock_mac" ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB" ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB" ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#" Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-04vendorcode/google/chromeos: Support MAC address passthru policyDuncan Laurie
This change adds support for providing a MAC address that can be used by the OS network drivers to change the MAC address that a NIC uses. The Realtek r8152 driver in the Linux kernel supports a MAC address passthru feature which can result in the dock ethernet port using the same MAC address that is assigned to the internal NIC. This is done by calling an ACPI method at \_SB.AMAC() which returns a formatted string containing the MAC address for the dock to use. The Linux kernel implementation can be found at drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read() This is implemented specifically for Chrome OS as it relies on VPD to determine the MAC address to supply. The policy which controls where the dock MAC address comes from is written into RW_VPD property "dock_passthru": "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac" "ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0" "builtin": existing dock MAC address (return nothing) The MAC address in VPD is the standard format AA:BB:CC:DD:EE:FF and it must be converted into the string format expected by the OS which involves some string manipulation which ACPI is not great at handling. BUG=b:123925776 TEST=this was tested on a sarien board by setting the VPD keys to their expected values and observing if the AMAC() method returns the expected string. Change-Id: I3335e5d924155431e299844e2aaace62168294e0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-04vendorcode/google/chromeos: Add support for reading VPD in ACPIDuncan Laurie
This ACPI device presents an interface that allows other ACPI devices or methods to read VPD strings. The VPDF() method is provided the VPD partition to look in, and the name of the VPD key to find and it will return the VPD string if it exists. For example: VPD.VPDF ("RO", "serial_number") BUG=b:123925776 TEST=this was tested on a sarien platform by adding ACPI code that searches for a VPD key and returns the value it finds, and then setting that VPD string from the OS with the Chrome OS 'vpd' utility to ensure the ACPI method returns the correct value. Change-Id: I4668f66d7f7f364ac8c3b064d406b24135abb0f6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-04vendorcode/google/chromeos: Save VPD region into GNVSDuncan Laurie
Store the memory address of VPD region start and length for the memory mapped RO_VPD and RW_VPD into GNVS so they can be used by ACPI code. BUG=b:123925776 TEST=boot on sarien and verify VPD start/length in GNVS Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-04soc/intel/cannonlake: Move common definitions to a header fileRizwan Qureshi
Move common definitions for PCH H and LP to a common header. Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31621 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04soc/intel/cnl/acpi: add ish ACPI deviceJett Rink
Create the ISH ACPI device so we can hang fields off of a _DSD table. Since this is also a PCI device that has run time probing, we can always emit the ACPI device and let the device tree turn the device on or off. BRANCH=none BUG=b:122722008 TEST=verify that _DSD table gets publish under ISH device in kernel ACPI tables. Also verified that device is still turned off if device tree for ISH is off. Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/31681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04soc/intel/cannonlake: Fix DSDT compile remarksLijian Zhao
The following remarks show up during cannonlake based platform coreboot build: dsdt.asl 55: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 136: Offset (0xa8), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Address those two remarks in coreboot. BUG=N/A TEST=Build coreboot and check build log to see no more remark. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Reviewed-on: https://review.coreboot.org/c/31666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2019-03-04sb/intel/i82801gx: Remove unnecessary/redundant ACPI offset operatorElyes HAOUAS
Using ACPICA version 20180927 or greater, IASL detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset". Offsets refer to the current offset are unnecessary. example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-04nb/intel/i945: Remove redundant use of ACPI offset operatorElyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: Ie1f2a2ace335af7984209c9e286b9f85e5342a7e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31671 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04payloads/tianocore: remove single branch checkout parameterMatt DeVillier
using '--single-branch' when cloning the tianocore repo prevents the use of other branches/commits outside of the checked-out coreboot_fb branch, so remove it. Test: build with TIANOCORE_REVISION selected and revision set to origin/master, verify checkout succeeds Change-Id: If8c93aa87957ba2ff9ab7a58e84d2a25b48ec346 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-04fmap: Add FMAP_AREA_PRESERVEHung-Te Lin
When updating firmware, we may need to preserve some sections like VPD, calibration data, ... etc. The logic can be hard-coded in updater as a list of known names, but a better solution is to have that directly declared inside FMAP area flags. To do that, the first step is to apply the changes in flash map (http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now defined and will be set in future with new syntax in FMD parser. BUG=chromium:936768 TEST=make; boots an x86 image. Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-04Revert "mb/google/poppy/variants/atlas: Update DPTF parameters"Puthikorn Voravootivat
This reverts commit 5e90ef8c356099e42612bc97976c67092d0810ff. Reason for revert: The 1s interval causes early throttle in usage spike. (log in b/123895423#comment3) BUG=b:113101335 BRANCH=None TEST=learning from Nocturne Change-Id: Id6467b51eb937b89b4c08641f36266544c8fa176 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-03-04src/soc/intel/braswell/cpu.c: Set up local APICFrans Hendriks
Local APIC was not configured. Add setup_lapic() to configure the APIC. BUG=N/A TEST= Ubuntu 4.15.0 reports correct local APIC information on Intel CherryHill CRB Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-03-04{src/include},{soc/intel): Configure HDA codecsFrans Hendriks
HDA support did not configure the codecs correclty. Use Intel common block support to configure the codecs. To use common Intel HDA support file hda.c file has been removed and Braswell HDA device ID is added to list of supported PCI devices in intel/common/block/hda/hda.c. CONFIG_SOC_INTEL_COMMON_BLOCK and CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled to include hda.c in build. When codec table is available at board level SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled and a codec table must be supplied. BUG=N/A TEST=Facebook FBG-1701 ALC298 configuration Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
Since ACPI v2.c, this field is access_size. Currently, coreboot is using ACPI v3,so we can drop '.resv' field. Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-04sb/intel/common: Fix SMBus block commandsKyösti Mälkki
Fix regression after commit c38d543 sb/intel/common: SMBus complete_command() When evaluating HSTSTS register, BYTE_DONE bit must be excluded from transaction completion and error criteria. Change-Id: I49cc43d1fa58250988cc41b2ca747b9f1d7586d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03rmodule: Don't emit reloc for R_X86_64_PC64Patrick Rudolph
Relocations for PC relative instructions must not emitted. As PC64 are unlikely with current code, it never was an issue. Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31469 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03device/pci: Organize MakefileKyösti Mälkki
Use a single group for all CONFIG_PCI=y sources. Change-Id: I426f4398c01dfbf03b9dd2db8c7a964512c86d5e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31680 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03device/pci_ops: Drop parameter from pci_bus_default_ops()Kyösti Mälkki
A default is a build-time static value, fallback. Return value does not depend of input parameter. Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31679 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03device/pci_ops: Drop unused parameterKyösti Mälkki
Drop the bus parameter, we do not use it. It would still be possible to do per-bus selection by evaluating the bus number, but currently we do not have need for that either. Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-03device/pci_ops: Avoid name collisionsKyösti Mälkki
Having different signatures for the PCI config accessors prevents them from having the same name in different stages. For now, work around this using __SIMPLE_DEVICE__. Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-03sb/intel/common/firmware: Don't touch descriptor regionMario Scheithauer
This patch makes the way to protect flash regions selectable. If you don't want to use ifdtool for modification of flash descriptor, enable the new option. Otherwise, the previous config settings for all mainboards will be retained. Change-Id: I46ec6339008edcc78fe76682eed5714f85354937 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-03arch/x86/acpi: Clean up commentsElyes HAOUAS
As we are running ACPI v3.0, references to older than v3.0 are removed. Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-03cpu/intel/model_1067x: Don't try to apply MCU a second timeNico Huber
Applying microcode updates a second time seems to be only necessary on newer platforms (Nehalem+) for "uncore" updates. Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Masanori Ogino <masanori.ogino@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-03cpu/intel/model_1067x: Implement microcode loadingNico Huber
We load it once for the BSP in advance and let the MP init handle it for the APs. The BSP load could also be done earlier, e.g. before CAR setup, to align with other platforms. TEST=Booted ThinkPad X200s and checked log: Microcode is loaded correctly on the BSP before SMM setup, and reported to be up to date on all cores after. Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-02superio/ite/common: add option for enabling 5 FANsKrystian Hebel
Some ITEs have more than 3 independent FAN controller outputs. As the initial implementation assumed only 3 outputs some registers are not consequently numbered. This change adds macros for accessing those registers. Additionally some chips have SmartGuardian always enabled, without the option for turning it off. For these chips bits that were responsible for ON/OFF control are either reserved or have different meaning. Another Kconfig option is added to disable ON/OFF functionality on platforms that do not support it. Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/31616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-02superio/ite/common/env_ctrl.c: fix IS_ENABLED argumentKrystian Hebel
There was CONFIG_ prefix missing in SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG option, this patch fixes it. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I52919671569175141560cb73e42344aa1725c112 Reviewed-on: https://review.coreboot.org/c/31674 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-02mb/google/sarien: Remove DRIVERS_PS2_KEYBOARDDuncan Laurie
In order to prevent keyboard keys pressed at boot from causing issues in the payload remove the PS2 keyboard driver so it does not get initialized until it is needed in libpayload. This was enabled initially because the keyboard controller on this platform does not come up in translated mode, so unless coreboot called keyboard_init() the keyboard would never work properly in the kernel because it would come up as an "AT Raw" device instead of an "AT Translated" device. Instead of initializing the keyboard in coreboot a workaround is added to the payload to put the keyboard into translated mode. BUG=b:126633269 TEST=boot on sarien while pressing keys and ensure libpayload and/or the kernel does not have any issues initializing the keyboard. Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-02libpayload: i8042: Only test PS/2 AUX port when enabledDuncan Laurie
If a PS/2 AUX device is not present then the AUX test command during i8042_probe() will time out and add ~500ms to the boot time. In order to avoid this only test the PS/2 AUX port if CONFIG_LP_PC_MOUSE is enabled. BUG=b:126633269 TEST=boot on device without AUX port and check that this command does not get executed, saving ~500ms at boot. Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-02libpayload: keyboard: Add option to ignore failures during initDuncan Laurie
If keys are pressed at boot some keyboard controllers will not properly respond with an ACK to commands, which results in the keyboard_init function aborting before it adds the keyboard to the input device list. This same keyboard controller will manage to properly return keyboard data when keys are pressed later, so it is possible for it to be functional in the payload even if it does not respond properly to every command during initialization. In order to allow payloads to use the keyboard when this happens a new Kconfig option is added to ignore the keyboard ACK response and always add the keyboard to the input device list. This option is disabled by default and must be enabled by the specific boards that need it. BUG=b:126633269 TEST=boot on device with this controller and press keys during boot and see that the keyboard is still functional in the payload. Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01soc/intel/skylake: Unify serial IRQ optionsNico Huber
We had two ways to configure the serial IRQ mode. One time in the devicetree for FSP and one time through Kconfig for coreboot. We'll use `enum serirq_mode` from soc/intel/common/ as a devicetree option instead. As the default is `quiet mode` here and that is the most common mode, this saves us a lot of lines. In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting settings in devicetree and Kconfig. We'll maintain the `continuous` selection, although it might be that coreboot overrode this earlier on the kblrvps. Note: A lot of Google boards have serial IRQ enabled, while the pin seems to be unconnected? Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-01payloads/tianocore: Add option for custom bootsplashMatt DeVillier
Add Kconfig options to use custom bootsplash file, dependent on using MrChromebox's stable branch, with help info conveying required file format. Adjust Makefile to copy the custom bootsplash and overwrite the default Logo.bmp file, handling both absolute and relative paths, and restore the original logo file after building so as to keep the working directory clean. Test: build with and without custom bootsplash, ensure correct bootsplash displayed Change-Id: I164f46777169801cff56633fd920bc81b7c8129a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-01src/arch/x86/acpi.c: Update ACPI table's revision numbersElyes HAOUAS
Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-01ACPI: Rename FADT model and set it to zeroElyes HAOUAS
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using greater version than ACPI 1.0. Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29986 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01drivers/intel/fsp2_0: Add more EFI return status into FSP2.0 driverSubrata Banik
This patch adds few more required EFI return status into FSP2.0 drivers so that coreboot code can make use of those. Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-01mb/siemens/mc_bdx1: Enable TPM2 on LPCWerner Zeh
This mainboard has a TPM located on the LPC bus. Enable the driver for it so that it is initialized and the ACPI table entry is generated. Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01util/cbmem: Improve utility descriptionKyösti Mälkki
Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01mb/google/sarien: ALC3204 HDA verb table pin config changeJoyce Toh
On Sarien, change pin config of 0x19 (headset mic) and 0x21(headset headphone) to change jack location so that naming does not use "Front" in the name."Front Headphone" --> "Headphone" so it matches naming on Arcada. BUG=b:126334749 TEST= verify with 'evtest' command that jack name is "HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone" Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Signed-off-by: Joyce Toh <joyce.toh@intel.com> Reviewed-on: https://review.coreboot.org/c/31624 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28src/mb/sifive/hifive-unleashed: replace fdt in maskromXiang Wang
The fdt in the maskrom cannot be used to start linux. The correct fdt is dumped by replacing the bbl of the original firmware and used in coreboot. Correct the mac address in fdt by reading otp Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/31047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-02-28src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory areaFrans Hendriks
Calculation of memory reserved by FSP is incorrect. Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area BUG=N/A TEST=Intel CherryHill CRB Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28soc/intel/cannonlake: Add CometLake SoC supportSubrata Banik
This patch adds SOC_INTEL_COMETLAKE Kconfig option. Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31282 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28mb/google/poppy/variants/atlas: Update DPTF parametersPuthikorn Voravootivat
Preliminary dptf change for Atlas - Throttle charger using all temp sensors (not just ambient) - Throttle charger with higher priority than CPU - Update throttle temperature using data from surface thermistor in thermal chamber test BUG=b:113101335 BRANCH=None TEST=based on preliminary data from thermal chamber test Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-02-28mb/google/poppy/variants/atlas: Add tdp_pl1_override valuePuthikorn Voravootivat
Use 7w PL1 with DPTF throttle to enable better performance for atlas. BUG=b:113101335 BRANCH=None TEST=Recommend setting from thermal team. Build coreboot on atlas Change-Id: Idcf44f213259634a507a013b31b410ed322e9479 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31627 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28src/soc/intel/braswell/southcluster.c: Config ISA DMA controllerFrans Hendriks
ISA dma controller is not configured. Add call isa_dma_init(). BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28soc/intel/braswell: Correct configuration of interruptsFrans Hendriks
The level/edge mode of PIRQ is not configured and i8259 PIC not initialized. Add calls to: - i8259_configure_irq_trigger() - setup_i8259() - write_pci_config_irqs() to correct the configuration of interrupts. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28src/soc/intel/braswell/acpi/irqlinks.asl: Allow IRQ10 and 11 for all LNKxFrans Hendriks
IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates. These interrupt numbers are added to all LNKx. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29287 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/x86/mtrr/mtrr.c:Avoid static scan false positiveRichard Spiegel
Static scan does not know the contents of the fixed MTRR descriptor, so it has no way to eval the result for variable num_ranges. If num_ranges is less or equal to 0, the for loop will not be entered, and the values of fixed_msrs will not be set. Asserting that num_ranges is greater than 0 ensures the loop enters at least once. BUG=b:112253891 TEST=build grunt Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28libpayload: cbfs: Check decompressed size when loading filesYou-Cheng Syu
After loading compressed files in CBFS, we should check the decompressed size is equal to the expected size. This might help us detect file content corruption or compressor/decompressor bugs. BUG=none BRANCH=none TEST=manually (we can still boot into kernel on Kukui, and verify that loading files from CBFS still works by seeing ChromiumOS firmware screen). Change-Id: Ia756cc5477670dd0d1d8aa59d4160ab4233c6795 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/31564 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28libpayload: cbfs: Require input size and output size for cbfs_decompressYou-Cheng Syu
Currently, cbfs_decompress() calls ulzma() and ulz4f() for LZMA/LZ4 decompression. These two functions don't accept input/output size as parameters. We can make cbfs_decompress more robust by calling ulzman() and ulz4fn() instead. This could prevent us from overflowing destination buffer. BUG=none BRANCH=none TEST=boot into kernel on Kukui with COMPRESSED_PAYLOAD_LZMA / COMPRESSED_PAYLOAD_LZ4. Change-Id: Ibe617825bd000ed618791d8e3c5f65bbbd5f7e33 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/31606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-02-28cpu/intel: Remove socket_BGA1284Nico Huber
Unused since the removal of `fsp_sandybridge`. Change-Id: Iea31e341c3df680ed48db4f8734d9d0bde120be3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31646 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel: Rename socket_mPGA478MN to socket_pNico Huber
These marketing names are much easier to distinguish. My mnemonic: Socket M => up to Merom, Socket P => up to Penryn. Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31645 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel: Remove models 69x and 6dxNico Huber
These came for the Socket 479 which is not supported anymore. Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31644 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel/socket_m: Remove models 69x and 6dxNico Huber
These sneaked in and were never supported by this socket (nor expected in the notebooks that have it). Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28cpu/intel: Rename socket_mFCPGA478 to socket_mNico Huber
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN, the successor of the socket that was meant. The official name of this socket is mPGA478MT. But "Socket M" is much easier to distinguish. Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28cpu/intel: Remove `socket_mPGA478`Nico Huber
Doesn't look like it could be used. Change-Id: I8074df12d062bd15f2388b367b3698c9d3b7b5b6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28mb/google/hatch: Add GPIO programming for GPP_C0 to GPP_C7Maulik V Vaghela
coreboot did not program all GPIOs from C0 to C7 correctly which are SMBUS GPIO. Some of the GPIOs are left in default mode which is native function but we need to configure as GPIO mode and provide proper configuration as per schematic. After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not getting idle due to GPIO configuration and CSME was not getting power gated due to SMBUS. BUG=b:123702553 BRANCH=none TEST=Check on hatch board. CSME was not getting power gated for s0ix. After applying this patch CSME is power gated now Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-28soc/intel/cannonlake: Disable ACPI mode on BS_DEV_INIT exitFurquan Shaikh
Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it more aligned with the behavior on other Intel SoCs. However, as the PMC device is hidden, it never gets enumerated and so init function does not get called for it. This change moves the call to disable ACPI mode to exit of BS_DEV_INIT instead. BUG=b:126016602 TEST=Verified that: 1. pmc_set_acpi_mode is actually getting called. 2. EC panic event gets logged to eventlog correctly. Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31633 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28google/kukui: Add RTC initializationRan Bi
Initialize RTC at ROM stage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9d9c68755e8a6ac65dd794211e6ccf06e5057567 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-28mediatek/mt8183: Add RTC supportRan Bi
This patch implements RTC initialization. 1. initialization dcxo 2. rtc clock using dcxo 32k 3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN 4. rtc register initialization 5. refactor the driver common part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-28vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for CometlakeMaulik V Vaghela
Adding header files for FSP for cometlake platform version 1034 Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-28mb/intel/saddlebrook: Fix 2nd DIMM slotKyösti Mälkki
Assumed broken during review and rebase. The SPD at address 0x52 will appear at index 1. Change-Id: I213853d2b981294554d8d1b254da476905a41c13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-28intel/spi: Switch to native PCI config accessorsKyösti Mälkki
Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-28intel/spi: Fix use of __SIMPLE_DEVICE__Kyösti Mälkki
Fix cases of using ENV_SMM where __SIMPLE_DEVICE__ should be used instead. Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-02-28soc/intel/cannonlake: Add PCH series check for CML LP PCHMaulik V Vaghela
TEST=Verify PM_STS1 value is is not 0xFF. Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31434 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device IDSubrata Banik
This patch adds CML-U 2+2 SA DID into systemagent.c and report platform. Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31638 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28soc/intel/skylake: Remove redundant PM emulation timer macrosSubrata Banik
This patch removes duplicate pm timer emulation macros from soc directory and makes use from common code msr.h Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31610 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27util/abuild: Set fatal asserts when running scanbuildMartin Roth
Because coreboot's asserts aren't fatal by default, scan-build finds problems in code that is actually protected by an assert. This change fixes that and allows us to add asserts to protect against other failures. Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/31650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27flapjack: use sku_id 0 for un-provisioned boardYH Lin
Instead of using 2, 0 is now used for non-CBI provisioned board or corrupted CBI board to confrom to the sku encoding. BUG=b:123676982 BRANCH=kukui TEST=test with un-provisioned board to verify the sku_id. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce Reviewed-on: https://review.coreboot.org/c/31623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27console: Split loglevel for fast and slowKyösti Mälkki
For fast CBMEM console use minimum BIOS_DEBUG level. For other consoles, Kconfig and/or nvram settings apply. Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27console: Refactor printk() varargs prototypesKyösti Mälkki
Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27ec/google/chromeec: fix the error status passingYH Lin
Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error -- fixing cbi_get_uint32() and cbi_get_string() so they follow the same convention. BUG=b:123676982 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Reviewed-on: https://review.coreboot.org/c/31585 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27rtc: Fix rtc_calc_weekdayTim Wawrzynczak
This function appeared previously unused (called only from rtc_display, also unused), but it returned an incorrect weekday. Change the algorithm to use Zeller's Rule, a well-known algorithm for calculuating weekdays. Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/31557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27mb/google/hatch: Initialize GPIO_PCH_WP early in bootRizwan Qureshi
Initialize GPIO_PCH_WP early in boot. Update cros_gpios[] array with GPIO_PCH_WP information. Also, Configure recovery mode GPIO as virtual since hatch does not have one. BUG=b:125943273 Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/hatch: Select SD_PWR_EN Active high configRizwan Qureshi
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same. BUG=b:123350329 Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
SD controller in CNL-PCH provides a ability to configure the behavior of SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD "SdCardPowerEnableActiveHigh" to control the same. However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC card connector is always powered and may impact system power. This is because SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not inserted. Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and force the TX buffer to low in _PS3. And restore the pad mode to native function in _PS0. Hence add a Kconfig option to update the UPD, which the board can select based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround gets applied based on this config. BUG=b:123350329 Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31445 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers. BUG=b:123350329 Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/hatch: update SD card detect GPIORizwan Qureshi
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO, expose that GPIO for kernel to configure card detect IRQ. BUG=b:123350329 Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/cyan: fix RAM training on edgar variantMatt DeVillier
Adapted from Chromium commit 5351dc0d [Edgar: To set the RX ODT limit and dram geometry with RAMID detection] Several cyan variants require memory init parameters be passed to FSP for handling of specific Micron modules; without these, RAM init will fail when loading training data from the MRC cache, and boot will halt. This was missed when I upstreamed edgar along with the other cyan variants, so add the required memory init parameters for edgar as per its source Chromium branch. Test: build/boot on edgar board with affected Micron memory modules, verify boot successful with populated MRC cache. Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31615 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGEPatrick Rudolph
To support measured boot, drop VBOOT_RETURN_FROM_VERSTAGE. The SoC has enough CAR space to support a separate verstage. Tested on OpenCellular Elgon. Change-Id: I18022000f6f05df89d3037896ef627070bfcca06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31568 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_initFurquan Shaikh
PMC initialization on Cannon Lake happens earlier in the boot sequence than other SoCs because FSP-Silicon init hides PMC from PCI bus. As ACPI disabling was done as part of PMC init, it was being called earlier than what other SoCs do. This resulted in a different order of events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it ended up clearing EC events (which happens as part of ACPI disabling in SMM) before logging any events of interest that happen during mainboard initialization. This change moves the call to disable ACPI to pmc_soc_init just like other SoCs to keep the order of events more aligned. BUG=b:126016602 TEST=Verified that EC panic event gets logged to eventlog correctly. Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26ACPI: Fix error on asl_compiler_revision formatElyes HAOUAS
dmesg report wrong asl compiler version as this value wasn't in hexadecimal: FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 01341407) DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215) This error was introduced on change-Id: I91b54b43c8b Tested on 945G-M4 board, dmesg now report the right value: FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 20190215) DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215) Change-Id: I5494bb1e7af17eba0c2da8a0c2eb9e40ffd8d065 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31612 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26Add missing u8 eos[2] declaration to struct smbios_type38Lukasz Siudut
Each smbios entry should be followed with two null bytes. In other structures it's done by adding `u8 eos[2]` extra bytes at the end, it was omitted in type38 (IPMI) though. This change fixes this - tables decodes nicely: ``` IPMI Device Information Interface Type: KCS (Keyboard Control Style) Specification Version: 2.0 I2C Slave Address: 0x10 NV Storage Device: Not Present Base Address: 0x0000000000000CA2 (I/O) Register Spacing: 32-bit Boundaries ``` Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: I8efea9612448f48e23e7b2226aea2a9f3bc21824 Reviewed-on: https://review.coreboot.org/c/31482 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26soc/amd: Remove defined but unwritten functionsRichard Spiegel
There are functions defined on headers with no code written for. They probably existed earlier, were removed and forgot in the headers. Remove functions from headers if there's no actual code written for. BUG=b:123564495 TEST=Build grunt. Change-Id: Ia6a12e22a0944351c455dc2c3b534f09a258bd7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-26mb/gigabyte/ga-h61m-s2pv: fix cosmetic thingsAngel Pons
Remove unneeded options, note where usbdebug is, reorder devicetree and clean up dsdt. Tested, board still boots. Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26ACPI: Fill asl_compiler_revision field left emptyElyes HAOUAS
Change-Id: I1075e872e5cb1990bd330b88bb03322ab9338e86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26ec/google/chromeec: Clarify return value of google_chromeec_commandDaisuke Nojiri
This patch clarifies the definition of google_chromeec_command. Currently absence of the definition isn't causing any problem because wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an interface which returns only negative error codes. However, there is a chance that a new wrapper API will be addedl which check 'ret < 0' to catch errors, assuming other interfaces behave the same. Or existing wrapper APIs will be broken as soon as they're compiled for another interface. BUG=chromium:935038 TEST=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f Reviewed-on: https://review.coreboot.org/c/31613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26flapjack: get sku_id from ec (cbi)YH Lin
On flapjack, retrieve the board information via CBI interface. Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id used prior to the readiness of cbi. BUG=b:123676982 BRANCH=kukui TEST=provisioned cbi info and verify the sku_id. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Reviewed-on: https://review.coreboot.org/c/31586 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26soc/cavium/cn81xx: Enable RNG for DRAM initPatrick Rudolph
The Cavium DRAM init might use the RNG for pattern generation. Initialize it before running DRAM init. Tested on OpenCellular Elgon. The RNG generates non identical numbers. Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-26mediatek/mt8183: Modify I2C source clockQii Wang
This patch change i2c source clock to TOPCKGEN. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569 Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC. Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26acpi: Sort the reported APIC-IDs in the MADT tableWerner Zeh
coreboot performs MP-Init in a parallel way. That leads to the fact that the order, in which the CPUs are woken up, can vary from boot to boot. The creation of the MADT table just parses the devicetree and takes the CPUs reported there as it is for creating the single local APIC entries. Therefore, the OS will see different order of CPUs. There are CPUs out there (like Apollo Lake for example) which have shared caches on core-level and if the order is random this can end up in assigning cores to different tasks or even OSes (in a virtual environment) which uses the same cache. This in turn will produce performance penalties across these distributed tasks/OSes. Though there is a way to discover the core- and cache-topology it will in the end be necessary to take the APIC-ID into account. To simplify it, one can achieve the same output by sorting the APIC-IDs in an ascending order. This will lead to the fact that CPUs that share a given cache will be reported right next to each other in the MADT. Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26commonlib: Add Bubble sort algorithmWerner Zeh
Add an implementation for Bubble sort. For now, only integers can be sorted in an ascending or descending order. It can be later simply extended to cover other datasets like strings if needed. The reasons for choosing bubble sort are: * it is a simple algorithm * bubble sort is stable, i.e. it does not exchange entries which are not needed to be sorted as they are already in order Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>