summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-06-15arch/x86/Kconfig: hide the "Bootblock behaviour" option on non-romccArthur Heymans
Selecting which cbfs prefix to load is only implemented with the romcc bootblock. Change-Id: I09523b94605f00ab15b5f0ea3986ac08e3a6afc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-15arch/x86/Kconfig: Hide the prefix option on all but BOOTBLOCK_NORMALArthur Heymans
Change-Id: Icf5e8fa18bea1cdfb85b8a4999d8fccea94d16b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-15Makefile.inc: Add -Wlogical-op warning optionElyes HAOUAS
Change-Id: Ie0491817a3a69c9f8e6f0f0d3cb755c642819df9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33385 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-15vendorcode/agesa/*/Proc/IDS/Library/IdsLib.c: Fix logical 'or' testsElyes HAOUAS
"if (_pcidata != 0xFFFFFFFF || _pcidata != 0)", is always true. The right test should be && not ||. Error found using -Wlogical-op warning option. Change-Id: I537fa4867499e1e6e5f662086fabc99b91aa0c70 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-15vendorcode/agesa: Fix check for valid PhyLaneElyes HAOUAS
Found using GCC with flag -Wlogical-op Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33362 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-15nb/amd/amdmct/mct: Simplify conditionalJacob Garber
These if statements can be combined to merge the two branches of the conditional and remove the duplicate pDCTstat->Speed == 3 check. Change-Id: I41aa19b4b7ed7b1a0e4f83f72e66869760e677dd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229583 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-15mainboard/google/hatch: Scrub Helios GPIOsTim Wawrzynczak
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate. BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with) Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-15mb/google/octopus/variants/bloog: Set tcc offset for bloogTony Huang
Change tcc offset from 0 to 10 degree celsius for bloog. BUG=b:135225497 BRANCH=octopus TEST=Build and verify test result by thermal team. Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-06-14mb/google/poppy/var/nami: Ensure SPD index is non-zeroJacob Garber
Memory id's are 1-indexed for DDR4, so we need to check that the SPD index is non-zero before converting it to the 0-indexed value in the bitmap. Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1387028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-14device/cpu_device.c: Use 'unsigned int' instead of 'unsigned'Elyes HAOUAS
Change-Id: I9f96d8c8e6cf2715e62ab3715da83740db8cce40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Vlado Cibic
2019-06-14libpayload/i8042/keyboard: Log errors during initializationFurquan Shaikh
Add error messages for all failed commands in keyboard_init(). Change-Id: Ie42ccbc4d850912c83e00376b27f192d5b652057 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14nb/i945: Drop CHANNEL_XOR_RANDOMIZATION selectionElyes HAOUAS
CHANNEL_XOR_RANDOMIZATION is configurable for no reason. Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-14drivers/fsp1_0: select CACHE_MRC_SETTINGS if MRC_CACHE_FMAPMatt DeVillier
Rather than force the user to create the RW_MRC_CACHE FMAP region, simply select CACHE_MRC_SETTINGS so it's done automatically for them. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-14hatch: Fix pen eject wake polarityTim Wawrzynczak
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing devices to wake up on pen insertion instead of removal. Changed to EV_ACT_DEASSERTED. BUG=b:134547896 BRANCH=none TEST=Verified in OS, device only wakes up on pen removal Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14mainboard/google/hatch: Update Helios device treeTim Wawrzynczak
Update Helios device tree override to match schematics. BUG=b:133182138 BRANCH=none TEST=Compiles Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33050 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14util/superiotool/nuvoton.c: add NCT5539D register dumpPavel Sayekat
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015). Tested on ASUS-H110M-E/M.2 mainboard (Kabylake i3-7100 CPU). Change-Id: Ib55068035ca574b22d0fea81e1a291f7cf0329d3 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-13mb/google/hatch/variants/helios: Use LPDDR3 memoryPaul Fagerburg
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays for mapping SoC DQS pins to LPDDR3 pins. BRANCH=none BUG=b:133455595 TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage` Ensure the firmware builds without error. Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13ec/google/wilco: Read back from EC RAM after S0ix entryDuncan Laurie
We are seeing an EC interrupt after setting the EC RAM offset that indicates that the EC should transition to S0ix mode and this is preventing the kernel from going into S0ix on the first try. As a workaround if we read back from the EC RAM while still in the _DSM handler it seems to prevent this problem. BUG=b:130644677 BRANCH=sarien TEST=ensure s0ix entry works on the first try with sarien Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455 Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13mb/google/sarien: Disable unused GPIOsDuncan Laurie
These 4 GPIOs are being disconnected in the next board so use the board ID to configure these pins as not connected to ensure they do not cause leakage. Also remove the ACPI _PTS S5 code that was configuring the GPIOs. This does mean they will cause small leakage in S5 on existing boards, but it will not affect the new boards. BUG=b:132393441 TEST=boot on sarien with fake board ID and ensure that coreboot configures these pads as expected. Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2019-06-13lint/clang-format: set to 96 chars per linePatrick Georgi
coreboot has decided to go with 96 characters per line. Original Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651 Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-13nb/amd/amdfam10: die() on out of bounds readsJacob Garber
These two functions try to access arrays of lengths 32 and 64 at indices of at most 259 and 71 (respectively). Something here is seriously wrong. This code was introduced in 2007, and aside from cosmetic changes, has had no modifications since then. I don't know what this code is supposed to do, and asking around on IRC, no one else did either. Until someone has the interest and time to work on it, let's at least add a die() to prevent the out of bounds access and alert the user that something is wrong. Change-Id: I5fc15a50a9f0e97add31e3a40da82a15f7427358 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 12296{79-82} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-13Documentation/soc/amd: Add Family 17hMarshall Dawson
Begin a directory for AMD soc devices and add an explanation of how Family 17h works. Newer AMD systems use a unique paradign for initializing the x86 processors. Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Add multilevel PSP directory tableMarshall Dawson
Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Align PSP NVRAMMarshall Dawson
Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Add argument for soft fuse overrideMarshall Dawson
Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-13util/superiotool: clarify usage of MISC and NANA definesFelix Held
Change-Id: I0b3c5c810bfb05eaec13511391ecd55d7b9eb4e8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enabledSubrata Banik
Change-Id: I416c74ea83ee68370bbeb53834054bcb18e631e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-13stage_cache: Make empty inline function if CONFIG_NO_STAGE_CACHE enableSubrata Banik
This patch removes CONFIG_NO_STAGE_CACHE check from caller function and add empty inline function incase CONFIG_NO_STAGE_CACHE is enable. Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-13mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disableSubrata Banik
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config. Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-13soc/intel/{cml, whl}: Add option to skip HECI disable in SMMSubrata Banik
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13soc/intel/icelake: Replace PCI device LPC to ESPI as per EDSSubrata Banik
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2019-06-13libpayload: Add USB support to mistral configPatrick Georgi
Change-Id: I2ef42f7d607eec6166d762ad71c0d9540906589d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com>
2019-06-12vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12mb/google/octopus: make new targets have DRAM part in CBI by defaultAaron Durbin
All new targets utilizing octopus mainboard support default to always using DRAM_PART_NUM_IN_CBI. This allows easier addition of new targets. BUG=b:132668378 BRANCH=octopus Change-Id: Idb136aa960260abe1657b16ded02a7dfb63c6849 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33370 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12qcom: Add i2c driverPrudhvi Yarlagadda
Add i2c driver in coreboot. Change-Id: I3d39d0325718fc5dd60da42eb2b87dcc4429bfc2 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-12vboot: recovery path should finalize work contextJoel Kitching
Recovery path should finalize work context, and trim vboot_working_data buffer_size. Otherwise, depthcharge ingests the full 12 KB workbuf in recovery path. BUG=chromium:972528, b:134893812 TEST=Build with vboot_reference CL:1584488. Check that USB disks are properly verified in recovery path. BRANCH=none Change-Id: Icf2600d2eb5d846a26aec35a153946dd2f7f128c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-12mb/google/hatch: Disable dynamic clock gating for cr50's GPIOSubrata Banik
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:130764684 b:130338605 BRANCH=None TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width, observe that even with sub-microsecond pulses no IRQs are missed. Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12Revert "mb/google/poppy/variants/atlas: enable NVMe"caveh jalali
This reverts commit 41979d862a972375d6800afdf2b8b52d408fd220. Reason for revert: NVMe is no longer supported. BUG=b:134752066 Change-Id: I95f2e5f5efe2417700d458f0efd3c793fd8ce8c3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33307 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-11mainboard/google/kahlee: Reduce VRAM to 16MBMartin Roth
It was determined through testing that 16MB of reserved VRAM is sufficient. Additional RAM for the graphics driver is allocated out of system memory. BUG=b:123579702 TEST=Boot Grunt, watch VRAM usage with graphics driver logging. Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-11console: Allow using vprintk() with disabled consoleJacob Garber
The prototype of vprintk() is currently declared unconditionally, which prevents it from being used in situations where the console is disabled. The code will compile correctly, but not link, since the definition in console.c isn't being provided. This adds a shim around the declaration so that, like printk(), a call to vprintk() in this situation will expand to a no-op function instead. Change-Id: Ib4a9aa96a5b9dbb9b937ff45854bf6a407938b37 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-11console: Make die() and friends variadicJacob Garber
die() currently only accepts a fixed message string, which is rather inconvenient when there is extra information that would be helpful to print in the error message. This currently requires an extra call to printk(), which is somewhat awkward: printk(BIOS_EMERG, "Bad table, opcode %d at %d", id, i); die(""); // what do I say here? die() already has a printk() inside it to print the error message, so let's just make it variadic to combine the two. die("Bad table, opcode %d at %d", id, i); // much better Forwarding variadic arguments from one function to another is rather tricky, so die_with_post_code() is redefined as a variadic macro instead. Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
2019-06-11Rampayload: Able to build coreboot without ramstageSubrata Banik
This patch removes all possible dependencies in order to build platform with CONFIG_RAMPAYLOAD enable(without ramstage). A. Create coreboot separate stage kconfigs This patch creates seperate stage configs as below 1. HAVE_BOOTBLOCK 2. HAVE_VERSTAGE 3. HAVE_ROMSTAGE 4. HAVE_POSTCAR 5. HAVE_RAMSTAGE B. Also ensures below kconfigs are aligned with correct stage configs 1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if CONFIG_HAVE_RAMSTAGE is selected. 2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set 3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE || CONFIG_HAVE_ROMSTAGE is selected. C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE On x86 platform: Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1 >> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32 Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0 >> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_ This patch fixes Case 2 usecase where platform doesn't select CONFIG_HAVE_RAMSTAGE. Also add option to create sipi_vector.manual based on $(TARGET_STAGE) variable. $(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE $(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-06-11soc/amd/common: Add errors for invalid AcpiMmio accessMarshall Dawson
Add a method for the soc/amd/<product> to indicate what AcpiMmio ranges are supported. Induce a build error if soc or mainboard code is added which attempts to use an unsupported block. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=boot grunt, force build errors by removing blocks in iomap.h BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-06-10mb/google/sarien/variants/arcada: Update thermal configuration for DPTFMike Hsieh
Update dptf for arcada DVT2. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I302b7cd4c7e0579acb5482800241b5229cfc49f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-06-10mb/google/poppy/variants/nami: remove redundant breakEric Lai
Break never comes after return, remove it. BUG=N/A BRANCH=firmware-nami-10775.108.B TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I005918d6a04cd21df496dea0f2cb1ed6108675af Reviewed-on: https://review.coreboot.org/c/coreboot/+/33299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10sdm845: qspi: Add Dual SPI supportJulius Werner
This patch adds support for the Dual SPI feature (SDR 2-bit in Qualcomm terminology) to the QSPI controller. Change-Id: I7aed2ccd9627f5de5dd760b418f74d56d2c031d3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33284 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-10spi_flash: Add Dual SPI supportJulius Werner
This patch adds support to read SPI flash in Dual SPI mode, where both MISO and MOSI lines are used for output mode (specifically Fast Read Dual Output (0x3b) where the command is still sent normally, not Fast Read Dual I/O (0xbb) whose additional benefit should be extremely marginal for our use cases but which would be more complicated to implement). This feature needs to be supported by both the flash chip and the controller, so we add a new dual_spi flag (and a new flags field to hold it) to the spi_flash structure and a new optional xfer_dual() function pointer to the spi_ctrlr structure. When both are provided, Dual SPI mode is used automatically, otherwise things work as before. This patch only adds the dual_spi flag exemplary to all Winbond and Gigadevice chips, other vendors need to be added as needed. Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10spi_flash: Make .read() callback optionalJulius Werner
All SPI flash chip drivers currently in coreboot use the generic read functions (spi_flash_cmd_read_fast()/_slow()) as their read callback. The only use case for specialized read callbacks we have left is with specialized flash controllers like Intel fast_spi (which sort of impersonate the flash chip driver by implementing their own probe function). This patch unifies the behavior for all normal flash drivers by making the read callback optional and letting them all fall back to a default read implementation that handles normal fast/slow reading. Most of the drivers used to install the respective callback after checking CONFIG_SPI_FLASH_NO_FAST_READ, but some hardcoded either slow or fast writes. I have found no indications for why this is and spot-checked datasheets for affected vendors to make sure they all support both commands, so I assume this is just some old inaccuracy rather than important differences that need preserving. (Please yell if you disagree.) Also take the opportunity to refactor some of the common spi_flash.c code a bit because I felt there are too many nested functions that don't really do enough on their own, and centralizing stuff a bit should make it easier to follow the code flow. (Some of this is in preparation for the next patch.) Change-Id: I2096a3ce619767b41b1b0c0c2b8e95b2bd90a419 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-06-10spi_flash: gigadevice: Adopt Winbond chip info structureJulius Werner
This patch changes the Gigadevice SPI flash driver to adopt the same structure packing improvements for the hardcoded parameters of individual chips that was implemented for Winbond last year. This cuts the size of the hardcoded info nearly in half and should save us a few hundred bytes in every stage. Change-Id: I9910dcb9b649f51b317f3f8fcba49e5e893f67d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10cbfs_spi: Enable speed logging by default for BIOS_DEBUGJulius Werner
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get in the way (just adding one line per stage, essentially) and should have no notable overhead. Let's enable it by default for the BIOS_DEBUG log level rather than having to recompile to get it. Also fix an issue with building this code on MIPS due to lack of 64-bit division primitives. (This means MIPS and arm32 board may display incorrect results when reading more than 4MB in a single transfer, which sounds very unlikely.) Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10mainboard/hp/z220_sff_workstation: remove unused header fileFelix Held
Change-Id: I4c780afaccd604a1bf4da67eea713f809744ddb2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-09acpigen: Add support for IndexFieldPatrick Rudolph
Add support for generating IndexField, which is similar to Field. Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09autoport: Generate a libgfxinit template when IGD is detectedIru Cai
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-09mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM sizeKacper Słomiński
Signed-off-by: Kacper Słomiński <kacper.slominski72@gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/30980 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09Documentation: Add display panel specificsDaniel Maslowski
Change-Id: If1a393578556d51499c700b68187034830d19215 Signed-off-by: Daniel Maslowski <daniel.maslowski@img.ly> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-09mb/google/hatch: Add 16G 2666 LPDDR3 SPDShelley Chen
One variant is asking for support for 16G 2666 LPDDR3, so adding generic SPD for that. BUG=b:133455595 BRANCH=None TEST=None as this is not being used yet Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-09mb/google/hatch: Add 8G 3200 SPDShelley Chen
One variant is asking for support for 8G 3200 DDR4, so adding generic SPD for that. BUG=b:132920013 BRANCH=None TEST=None as this is not being used yet Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory initAamir Bohra
Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32522 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/google/dragonegg: Pass FSP-M UPD as per dragonegg requirementSubrata Banik
TEST=Able to boot dragonegg board with LPDDR4 memory. Change-Id: Idbe0aa79879f2b1a754dd1f6718ad4ba1173e760 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31956 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirementAamir Bohra
1. Gfx stolen memory requirement for ICL GFX 2. Enable PeiGraphicsPeim support Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09vendorcode/intel/../icelake: Update ICL FSP header BIOS version 3092Subrata Banik
After building from here : https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/icl/+/refs/tags/upstream/BIOS_Version_3092 Change-Id: I8924dbf4a8d6a303540ced1c9c48586d26d6beaa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-06-09soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLINGSubrata Banik
Skip GT specific programming in coreboot to support early parts without GT enable. Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08Kconfig: Guard RAMPAYLOADNico Huber
The RAMPAYLOAD symbol added by 7e893a02c0 (Kconfig: Create RAMPAYLOAD kconfig) is shown unconditionally for all x86 systems. It generally creates a lot of confusion to prompt for something that isn't imple- mented or not working. So guard it with another Kconfig that can be selected by platforms that actually support it. Change-Id: I6d158382d1000b8b40ca1368e2efff0c39884f15 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33263 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08mb/lenovo/t430: Fix Dual GraphicsPatrick Rudolph
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix disabling iGPU in 'Dual Graphics' on Lenovo T430. * Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select DRIVERS_LENOVO_HYBRID_GRAPHICS. Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-08nb/intel/sandybridge: Drop iommu.c and rename functionsPatrick Rudolph
* Move the contents of iommu.c to early_init.c. * Name the functions like done in intel/soc/common. * Move PAMx register setup to own function Preparations for integration in soc/intel/common/* Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32068 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/acpi: Remove Return for PS0/3Christian Walter
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements. Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/bootblock: Add SPT C236 to PCH TableChristian Walter
Add Skylake C236 to the PCH Table. The one which was already in there is actually the CM236 and not the C236. This can be checked in datasheet: 100-series-chipset-datasheet-vol-1 p. 25. Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-08northbridge/gm45: document that raminit doesn't support mirrored ranksFelix Held
Change-Id: I8a66a1355974f6771c5e4bae0dc60da2447122d1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-07sb/amd/sb700: Fix misleading formattingMarshall Dawson
Change-Id: I65872d6f1d71d050c8589d3616340648cf95048b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-07ifdtool: Enable GbE/PDR/EC region access only if they existDuncan Laurie
Instead of assuming GbE/PDR/EC regions may exist or not, check if there is a valid region defined in the descriptor and set the region access permissions based on that. The net effect change is to enable the use of the PDR region on the sarien platform, which also uses the GbE and EC regions. This results in the following example changes: mb/google/sarien (GbE, PDR, EC) . DESC BIOS ME GbE PDR EC -BIOS r rw rw r ------------------------------- +BIOS r rw rw rw r mb/google/eve: (no GbE, no PDR, no EC) . DESC BIOS ME GbE PDR EC -BIOS r rw rw r -ME r rw r -GbE r rw -EC r rw ------------------------------- +BIOS r rw +ME r rw +GbE +EC BUG=b:134703987 Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07ec/google/wilco: Add UCSI supportDuncan Laurie
This change adds support for the UCSI specification in order to provide information about the Type-C port and an interface to perform power and data role swap. This change is split across the DSDT and SSDT, with the shared memory and operation region declared in the SSDT after being allocated in CBMEM. The OS will fill in the registers in the system memory region and then call the _DSM method wtih a read or write argument. The DSM method will copy the required registers to/from the system memory and the EC and perform the write or read action. Responses from the EC will generate a new SCI with event code 0x79 which will notify this UCSI ACPI device and the OS driver will take action to read status from the EC. BUG=b:131083691 Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07cbmem: Add ID for UCSIDuncan Laurie
The USB Type-C Connector System Software Interface (UCSI) defines a required memory oregion for the OS UCSI driver to use to communicate with the BIOS and EC. This provides a CBMEM ID that can be used by drivers to allocate this shared memory region for the UCSI driver to use. BUG=b:131083691 Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07soc/intel/cannonlake: Add _DSM method for SD controllerV Sowmya
The SD controller seems to take some time after restarting the clock at 1.8V before it actually switches from 3.3V to 1.8V. Add a _DSM method that simply sleeps when switching between 3.3V and 1.8V. Otherwise, the kernel times out too quickly waiting for the card to acknowledge the 1.8V switch. The card itself is waiting until it sees the clk signal being driven at 1.8V. BUG=b:125441242 TEST=Boot Hatch with SD card and CR2 removed, observe voltage switch succeeds. Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Signef-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07soc/intel: Add some missing MCH PCIe IDsKeno Fischer
These are documented in the Intel Datasheet entitled "6th Generation Intel® Processor Datasheet for S-Platforms" "6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2) Without them, coreboot fails to properly inform the payload of the amount of available memory. Signed-off-by: Keno Fischer <keno@juliacomputing.com> Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-06mb/google: Add GPU panel settings for SKL/KBL boardsNico Huber
The values are generated from the respective VBTs. Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/intel/skl/graphics: Implement panel setupNico Huber
Logs from Linux' i915 suggest that not even the FSP/GOP takes proper care of this. The sequence is mostly the same as on older platforms, with a slightly different configuration of the backlight PWM. We light the panel up with 50% PWM duty cycle. This often results in an already rather high perceived brightness, but shouldn't be too blinding. Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-06soc/amd/common: Make biosram functions more readableMarshall Dawson
Modify the 16 and 32 bit BIOS RAM access functions that had been originally moved from stoneyridge. This was suggested in the review of 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: I5b491da6f263cbab2b549301e16a7e19896f2428 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32932 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Update AcpiMmio commentsMarshall Dawson
Document the AcpiMmio individual blocks better. This is in response to a request in gerrit for 69486cac7: Create AcpiMmio functionality from stoneyridge Correct comments that were inadvertently left in place from older patches. Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06qcs405: Enable VBOOT_MIGRATE_WORKING_DATANitheesh Sekar
Enable VBOOT MIGRATE_WORKING_DATA so that the data required by depthcharge is copied into the coreboot tables and made available to depthcharge after BOOT_IMEM is cleansed. Change-Id: I0317b73d24b07553672695998589f86677e0be64 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-06qcs405: Add PRESERVE flag for RO_VPDNitheesh Sekar
Add PRESERVE flag to preserve the VPD data. Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33020 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Fix consistency in AcpiMmio argumentsMarshall Dawson
Change all arguments named "offset" to "reg" to match the others. These should have gone into change 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32930 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Clean up prototypes for AcpiMmioMarshall Dawson
Reorder the biosram prototypes to match the rest of the file. Remove prototypes for asf 32-bit functions that have not been implemented. Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32929 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/amd/stoneyridge: Move alink source to commonMarshall Dawson
Relocate the alink access functions out of stoneyridge where they were dead code. This source maintains the ability to access all register spaces, however more modern APUs define only ABCFG in the BKDGs. BUG=b:131682806 Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Add ALink-AHB Bridge to iomap.hMarshall Dawson
Add the address and replace the hardcoded value in the ASL code. Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32662 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move sata to commonMarshall Dawson
Relocate generic sata support from stoneyridge to common/block. BUG=b:131682806 Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32661 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Split sata functionalityMarshall Dawson
Separate chipset-specific source from sata_init(), and modify it to better match coreboot conventions. A subsequent patch will move the generic portion to soc/amd/common. The support for enabling port multipliers appears to have been first added for Kabini. Although missing from the documentation, the ability to affect the HBA Capabilities Register seems to remain for Stoney Ridge. Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Remove sb_util.cMarshall Dawson
Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk(). Relocate the remaining functions to get/save UMA information to southbridge.c. Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06nb/intel/pineview/raminit.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I4faf698e904c461803e867d212c31958119cc0ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Relocate acpi_get_sleep_type()Marshall Dawson
Move the function into common code. Convert it to use the memory- mapped access type. Convert vboot_platform_is_resuming() to call it instead of duplicating the source. BUG=b:131682806 Change-Id: I245bebb8dc2d331cdd56acfb245a004536b792ab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move IOMMU support to commonMarshall Dawson
BUG=b:131682806 Change-Id: Icb02180645c9e7e6dc973438c777228b031b3f54 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32657 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move hda.c to commonMarshall Dawson
BUG=b:131682806 Change-Id: I1aa869584fd6743101c07a6a508abff6426df18d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32656 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Relocate MMIO access of ACPI registersMarshall Dawson
The AcpiMmio block allowing direct access to the ACPI registers has remained consistent across AMD models. Move the support from soc//stoneyridge to soc//common. BUG=b:131682806 Change-Id: I0e017a71f8efb4b614986cb327de398644599853 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Rework block/acpiMarshall Dawson
The halt.c file relies on the ACPI register block in the AcpiMmio range. This register block is consistent across AMD device generations, so to prepare for moving additional stoneyridge support to this directory by changing the file name and add a Kconfig symbol to control the build. BUG=b:131682806 Change-Id: I2f7442dd78bced7f69b0416a8cd751291f82151f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32654 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move LPC support to commonMarshall Dawson
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Rework SPI base address get/setMarshall Dawson
A subsequent patch will move the soc//stoneyridge LPC functionality to a common directory. Prepare by reworking the SPI BAR configuration function in southbridge.h. The SPI BAR is not a typical PCI BAR, and is at D14F3xA0. Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move GPIO support to commonMarshall Dawson
The banked GPIO functionality in the AcpiMmio block has been consistent since the Mullins product. Move the basic support into a common directory. Each product's pin availability, MUXes, and other details must remain specific to the product. The relocated source also drops the weak configure_gevent_smi() that reports SMI is not available. The stoneyridge port relies on SMI to do its initialization, similar to modern soc/intel devices. This is the plan for future soc/amd ports, so make a missing function a build error instead of a runtime warning. BUG=b:131682806 Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-06Makefile.inc: Compile smm files independent ARCH_RAMSTAGE_X86_32/64Subrata Banik
This patch makes smm related files compile independent of ramstage getting compiled. If user selects RAMPAYLOAD to boot without ramstage, there will be need for smm code to get compiled independently. Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06Revert "libpayload: Reset PS/2 keyboard"Nico Huber
Documentation is scarce on the matter, however the related coreboot code suggests that after the ACK, the keyboard also sends the result of the self test (passed/failed). It looks like this result is never consumed here, probably resulting in further confusion for later com- mands. Let's revert this for now (if it's not too late for the 4.10 release) and break things later again. IMHO, due to the fact that there are dozens of different keyboard controller and keyboard implementations and no accurate specification followed, such changes should be tested on a lot of hardware before merge. This reverts commit a99ed13e3397bc536012120aab8cadb827913863. This reverts commit 7ae606f57f0b3d450ae748141b0e2367041b27d3. Change-Id: I4d4304d5d8a01e013feac61016c59bcaeea81140 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Kepplinger <martink@posteo.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-06sb/intel/ibexpeak: Copy the sandybridge bootblock.c fileArthur Heymans
This allows to port C_ENVIRONMENT_BOOTBLOCK to sandybridge separately from nehalem. Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>