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2014-08-22lenovo/t530/mainboard.c: Add EC info to SMBIOSEdward O'Callaghan
As is in: 91175bb lenovo/x201 & x230: Add EC info to SMBIOS This is needed for the Linux driver for the Lenovo's to properly attach. Change-Id: Ib910b25f392d9d3d6362b6909ce9fd4eeae9a096 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-21Merge LCD on nehalemVladimir Serbinenko
Change-Id: I09852ea56495da17e7607064d74d98f2296f34b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6721 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21Merge LCD on sandy/ivyVladimir Serbinenko
Change-Id: Ibf66d46f47fe465cc805f85de818a77327cd7258 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6722 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Support text mode gfx initVladimir Serbinenko
Change-Id: I952fdb113e2696785695b416d9292b7107099994 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6723 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945/gma: don't map the page tableVladimir Serbinenko
Change-Id: I20fb5323cde1f83a3d3adc98251b2f31de25ed24 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Remove GTT avoidance offset.Vladimir Serbinenko
Not needed anymore with GTT at the end of range. Change-Id: I57b02c7d605d3c43ac92bd744bb6472e3c3471e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6717 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-21arm: Get rid of the INTERMEDIATE variable used on exynos.Gabe Black
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for Exynos SOCs, but we can do that directly without having a special hook. Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170921 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-20intel/i945/gma: Place GTT below top of memoryPaul Menzel
Since commit 17fec8a0 [1] drm/i915: Use Graphics Base of Stolen Memory on all gen3+ present in the Linux kernel since version 3.12, 3D does not work anymore [2]. Comparing the graphics registers, in this case that means output of `intel_reg_dumper`, the vendor Video BIOS is setting the register PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init sets it to `0x3f800001`. Currently native graphis init sets the GTT right above the base address of stolen memory. The Video BIOS sets it below the top of memory. The Linux Intel driver expects it to be below top of memory, so do it this way, by setting the address to TOM minus the size of the GTT, which is hardcoded to 256 KiB. As `PGETBL_CTL` is zero by default, reading its value in the beginning is not necessary and is only confusing. Make it clear that the code calculates the value. There is still a PTE error reported during boot, but 3D works with Linux 3.12+ and no user visible problems are shown. [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038 [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1_graphics_core_0.pdf Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/5927 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-19libpayload: usb: Fix several minor USB stack bugsJulius Werner
This patch fixes the following minor bugs in the USB stack: 1. Ensure that all dynamically allocated device structures are cleaned on detachment, and that the device address is correctly released again. 2. Make sure MSC and HID drivers notice missing endpoints and actually detach the device in that case (to prevent it from being used). 3. Make sure XHCI-specific set_address() cleans up all data structures on failure. 4. Fix broken Slot ID range check that prevented XHCI devices from being correctly cleaned up. Change-Id: I7b2b9c8cd6c5e93cb19abcf01425bcd85d2e1f22 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170665 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 9671472263ddd0c30400ae3b6da780a18cd21ded) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6701 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19tegra124: Implement the tegra i2c driver.Gabe Black
This uses the packet mode of the controller since that allows transfering more data at a time. Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172402 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4444cd626a55c8c2486cda6ac9cfece4e53dd0d3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6703 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.Gabe Black
The pins on tegra are controlled by three different units, the pinmux, the pin group controls, and the GPIO banks. Each of these units controls some aspect of the pins, and they layer together and interact in interesting ways. By default, the GPIOs are configured to pass through the special purpose IO that the pinmux is configured to and so can be ignored unless a GPIO is needed. The pinmux controls which special purpose signal passes through, along with pull ups, downs, and whether the output is tristated. The pingroup controls change the parameters of a group of pins which all have to do with a related function unit. The enum which holds constants related to the pinmux is relatively involved and may not be entirely complete or correct due to slightly inconsistent, incomplete, or missing documentation related to the pinmux. Considerable effort has been made to make it as accurate as possible. It includes a constant which is the index into the pinmux control registers for that pin, what each of the functions supported by that pin are, and which GPIO it corresponds to. The GPIO constant is named after the GPIO and is the pinmux register index for the pin for that GPIO. That way, when you need to turn on a GPIO, you can use that constant along with the pinmux manipulating functions to enable its tristate and pull up/down mode in addition to setting up the GPIO controls. Also, while in general I prefer not to use macros or the preprocessor when writing C code, in this case the set of constants in the enums was too large and cumbersome to manage without them. Since they're being used to construct a table in a straightforward way, hopefully their negative aspects will be minimized. In addition to the low level functions in each driver, the GPIO code also includes some high level functions to set up input or output GPIOs since that will probably be a very common thing to want to do. Old-Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171806 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a) tegra124: Add base address for the pinmux and pingroup registers. There weren't any constants for the pinmux or pingroup registers in the address map header. Old-Change-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 79b61016bfd702b0ea5221658305d8bd359f4f62) Squashed two related commits. Change-Id: Ifeb6085128bd53f0ef5f82c930eda66a2b59499b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6702 Tested-by: build bot (Jenkins)
2014-08-19tegra124: Pick addresses to load the rom and ram stages.Gabe Black
If these aren't set, the rom and ram stages will attempt to load at address zero which doesn't work. Change-Id: I0b9b37d6363e6b208248d8a1af6ebee4db602486 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/173540 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 6ac5cea39d423bfcf5bbd53c2cc6228ab89f08b2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6704 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19asrock/imb-a180/board_info.txt: add flash fieldsStefan Tauner
Change-Id: Ie686d20811f33c620156c149315807343dde7784 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/6700 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-19macbook21: Support wake on LIDVladimir Serbinenko
Change-Id: Ifa1045abc761bef05977a8020cf6f18db042ad58 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6699 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x20[01]: Don't undock on disconnecting of power from dock stationVladimir Serbinenko
Change-Id: Id55bf259d5af187ba718de7e367395adcfc567b4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6707 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x201: Fix dock recognitionVladimir Serbinenko
Change-Id: I8b210786f660e2b2bae0d9ddd594386fd107cbe4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6706 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x201: Unpower USB on undockingVladimir Serbinenko
Change-Id: I9b496e8ff92ee575d0b780eab0cb45ea05506d30 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6708 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-19lenovo/x200: Dock supportVladimir Serbinenko
Change-Id: I4e25630ae82e8030a9d6bfccb60844c301b1d635 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6705 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18trustzone: Pull trustzone init out of cpu.c and do it in romstage.Gabe Black
Trustzone needs to be initialized/disabled both on boot and on wake, so it needs to be done before ramstage which doesn't run on wake. cpu.c isn't compiled into romstage and fixing that causes other problems, so the trustzone functions were split out. Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169817 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18tegra: Change how tegra124 and tegra include files from each other.Gabe Black
A problem with including the tegra124 directory directly in the include path is that it makes all headers in that directory first level headers available everywhere including places that have nothing to do with the SOC, even headers which were only intended for local use by tegra124 code. This change modifies things a bit to be more like the way the arch headers are chosen. In the tegra124 directory, there's an include directory which has an soc subdirectory in it. That include directory is added to the include path, making it possible to have headers private to the tegra124. When files specific to whatever tegra is being built for are needed, you can include <soc/foo.h> and get the version specific to that particular soc. Also, the soc.h header file was overhauled to use enums instead of defines, to consistently name things as far as their prefix (the less cryptic TEGRA instead of NV_PA) and suffixes like "BASE", and to get rid of values which were specific to U-Boot which we don't need. Since the only thing in the file were address constants, I also renamed the file addressmap.h. It would be included as: <soc/addressmap.h> which I think is easy to remember, does what you'd think it does from the name, and won't conflict with other header files just minding their own business in some other directory. Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172080 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6659 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18libpayload: usbmsc: Remove DETACHED state from MSC device structureJulius Werner
The USB MSC device structure contains a "ready" state that can be either "ready", "not ready" or "detached". The last one can only be assigned when the device is completely unresponsive and gets forcefully logically detached via usb_detach_device(). This call (at least in the current version) also calls all destructors and frees the complete usbdev_t structure (including the MSC specific part), which unfortunately makes storing the "detached" state in that very structure a little pointless. This patch reduces the "ready" value to a simple boolean and makes sure that all detachment cases immediately return from the MSC driver, carefully avoiding any use-after-free opportunities. Change-Id: Iff1c0849f9ce7c95d399bb9a1a0a94469951194d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170667 (cherry picked from commit fd4529f37fdd1c93a8b902488ffeef7001b1a05a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6654 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-18exynos5420: Don't map low addresses that lead nowhereJulius Werner
I just spent half a day (including the time to implement a stack dumper) to figure out that I am reading from a NULL pointer. A problem this simple should be more easy to catch. Let's mark the address range below SRAM as uncached so that the MMU can yell at you right away for being the bad programmer you are when you access a NULL pointer. Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170112 Reviewed-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6650 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18arm/exynos: Allow releasing UART retention for resume.Hung-Te Lin
The UART / serial console is put in retention state by kernel during suspend / resume path, which caused Coreboot not able to print any messages during resume. Sending values to the padret_uart_opt inside PMU may release UART, but that may also cause unexpected output when kernel is back. However, it's still very helpful when we are debugging suspend/resume inside Coreboot. To get UART message on resume, call wakeup_enable_uart() in boot block or romstage (before console_init). Change-Id: Ib5759cb402c6e018d9dba14fad8b61f6a1b1a265 Reviewed-on: https://chromium-review.googlesource.com/170440 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 547fbbfe2eeb6da4e161f36be2caf8099f9eac9b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6649 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5: Implement support for USB 3.0 DRD PHYs/controllersJulius Werner
This patch adds support for the DesignWare3 USB 3.0 DRD controller and PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the Google Snow and Pit boards to turn these controllers on where applicable. Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169452 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6642 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18console: conditionally include console in bootblockStefan Reinauer
Right now some console specific objects are included in the bootblock even if CONFIG_BOOTBLOCK_CONSOLE is disabled while others are not. Make all of them conditional and also fix a preprocessor misuse in bootblock_simple.c and a stray (useless) die() in the Exynos wakeup code that made inclusion of those files necessary. Change-Id: Ia7f9d17654466f199b0e13afbdc9e14c9706530f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168772 Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 855da1f07b52898c7edcaffe5baabe9d485bbd83) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6637 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-18macbook11: New mainboard (macbook21 clone)Vladimir Serbinenko
Tested by marcus. Change-Id: Ifce2018ef49619b36fb07e5345d70c358a0397e4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6698 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18azalia: Move shared variable to separate fileVladimir Serbinenko
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-18board-info: Output errors to stdout like make lint-stable expectsVladimir Serbinenko
Change-Id: I7eb2283808cde86c79d6b770a176daee57a7f9f2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6696 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/intel/mohonpeak: code cleanupMartin Roth
Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" - Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth
This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth
Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18cpu/intel/fsp_model_406dx: code cleanupMartin Roth
Code cleanup requested in commit 09670265 - "cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)" - add guard statements to chip.h - remove excessive includes - whitespace cleanup - add an IS_ENABLED Change-Id: Iaa85bd66953df015f083b23f6fd32949bcfd17bc Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6599 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18apple/macbook21: Fix audio.Vladimir Serbinenko
Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5324 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-17Revert "macbook21: Add CST entries"Vladimir Serbinenko
Some of C-states still cause hang. Revert C-states patch. This reverts commit fe661612d8e94d41dc0129533bb02f7c4faaf11a. Change-Id: I7534dac5d27b853d7b93947c38bf3742797fdcc2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6694 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-08-17gm45: Declare BIOS memory as RAM.Vladimir Serbinenko
So it's in line with other boards and those addresses are cached for faster access. Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6689 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17macbook21: Add CST entriesVladimir Serbinenko
Change-Id: I9e8628d879a193e2f6ba561ee17f24ae94435e1a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6693 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17apple/macbook21: EC handling ACPI implementation.Vladimir Serbinenko
Now battery indicator and lid work. Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5323 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-17A new port apple/macbook21.Mono
Current problems: - Complete lack of EC support (no battery indicator, no temperature, ...) - No audio support Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Axel Holewa <mono@posteo.de> Reviewed-on: http://review.coreboot.org/5321 Tested-by: build bot (Jenkins)
2014-08-17i945: Replace video gfx init.Vladimir Serbinenko
Old init was a replay not even meant to have been committed. This one really computes values and does its job. Tested on Macbook2,1 (1280x800) and X60 (1024x768). Change-Id: I61b6946c095fe06e20ae9a0db54696d0568225dd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5320 Reviewed-by: Francis Rowe <info@gluglug.org.uk> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16lint-stable: Check that modified boards contain meaningful board_info.txt.Vladimir Serbinenko
Change-Id: Idd3ff029e16b4b963f13d341dabdc1949c4e9275 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6670 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16AMD Family 14: Fix permissions on one northbridge fileBruce Griffith
fam14_callouts.h should not have the execute bit set. Change-Id: Iab44d04f2c9669e28d2d5028b0a11e565cc7bb07 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6675 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Decrease MTRR usageVladimir Serbinenko
Change-Id: I4c790b0eaf2af94286e6691281fcad3d14659a99 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6687 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Make UMA size configurable.Vladimir Serbinenko
Change-Id: I27b2ec70b9c77f3caf9d52788f46f5dc16045d1b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6686 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16lenovo/x200: Remove leftover roda rk9 devices.Vladimir Serbinenko
Change-Id: Ief3baa985cf83059255e64a8ab78cad9f8571199 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6688 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16gm45: Recognize 48MiB gfx UMA.Vladimir Serbinenko
Change-Id: I33e6b357ea044d6ec00b119e84cbada7bf58317f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6685 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16intel/gm45: native gfx init.Vladimir Serbinenko
Tested on lenovo X200 in both text and gfx mode. Change-Id: I273971d0f34ca3529959d4228e9516775459b806 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6682 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16exynos5xx0: rename local "main" variablePatrick Georgi
Change-Id: I9a454c88c65e4e70d351f1ec781e75ba400ceb29 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6664 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16bootstate: don't use header in romstage codePatrick Georgi
Change-Id: I0c2943bb0889552dc384d8efb5226cd6982a4d81 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6663 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-16libpayload: add march flag for armv7Isaac Christensen
The cache functions for armv7 require 'march=armv7-a' to use the 'isb' and 'dsb' instructions. Change-Id: I3b7ad8fc7da8c3167b38fd1a325090fe49e4ca42 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6668 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-16libpayload: change cb_range to lb_rangeIsaac Christensen
Patch 'coreboot_tables: reduce redundant data structures' (1f5487a) added a new lb_range structure to coreboot and libpayload but the original chromium patch added cb_range to libpayload instead. A followup patch 'arm: libpayload: Add cache coherent DMA memory definition and management' (b8fad3d) used the incorrect cb_range structure but this wasn't caught since the current verification build doesn't build libpayload for arm. Change-Id: I7cedc66a4794bf4daa214f54be6e917f96418ff6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6665 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-15tegra124: fix Kconfig ARCH settingsIsaac Christensen
The initial commit for tegra124 (396b072) was not updated for the new ARCH settings. Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6658 Tested-by: build bot (Jenkins)
2014-08-15Move baytrail-specific config to baytrail.Vladimir Serbinenko
Stop polluting first screen of all boards. Change-Id: I1ab88075722f7f0d63550010e7c645281603c9c3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14libpayload: dma_malloc: Prevent warm reboot problems and add debuggingJulius Werner
Since the DMA memory is allocated by Coreboot (outside of the payload's linker script), it won't get zeroed upon loading like the heap. Therefore, a warm reboot that doesn't reset memory may leave stale malloc cookies lying around and misinterpret them as memory that is still in use on the next boot. After several boots this may fill up the whole DMA memory and lead to OOM conditions. Therefore, this patch explicitly wipes the first cookie in init_dma_memory() to prevent that from happening. It also expands the existing memory allocator debugging code to cover the DMA parts, which was very helpful in identifying this particular problem. Change-Id: I6e2083c286ff8ec865b22dd922c39c456944b451 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169455 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8e5e1784638563b865553125cd5dab1d36a5d2cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6645 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14libpayload: xhci: Make XHCI stack usable on ARMJulius Werner
This patch updates the libpayload XHCI stack to run on ARM CPUs (tested with the DWC3 controller on an Exynos5420). Firstly, it adds support for 64-byte Slot/Endpoint Context sizes. Since the existing context handling code represented the whole device context as a C struct (whose size has to be known at compile time), it was necessary to refactor the input and device context structures to consist of pointers to the actual contexts instead. Secondly, it moves all data structures that the xHC accesses through DMA to cache-coherent memory. With a similar rationale as in the ARM patches for EHCI, using explicit cache maintenance functions to correctly handle the actual transfer buffers in all cases is presumably impossible. Instead this patch also chooses to create a DMA bounce buffer in the XHCI stack where transfer buffers which are not already cache-coherent will be copied to/from. Change-Id: I14e82fffb43b4d52d687b65415f2e33920e088de Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169453 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 1fa9964063cce6cbd87ba68334806dde8aa2354c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14armv7: mark EABI compatibility symbols as usedStefan Reinauer
These symbols are not used anywhere in our C code, so when using GCC's link time optimization feature they will be dropped even though they're needed by libgcc. Hence we need to mark them as used so GCC does not stumble and fall over its own guts. Change-Id: Ib2e9ea2610b57ab8244d5b699dd56025a4f08a01 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168773 (cherry picked from commit 416ffc880bcf4122b5430fbd9d9547c83886af2f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14libpayload: Make EHCI driver cache-awareJulius Werner
This patch makes the EHCI driver work on ARM platforms which usually do not support automatic cache snooping. It uses the new DMA memory mechanism (which needs to be correctly set up in the Coreboot mainboard code) to allocate all EHCI-internal communication structures in cache-coherent memory, and cleans/invalidates the externally supplied transfer buffers in Bulk and Control functions with explicit calls as necessary. Old-Change-Id: Ie8a62545d905b7a4fdd2a56b9405774be69779e5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167339 (cherry picked from commit 322338934add36a5372ffe7d2a45e61a4fdd4a54) libpayload: ehci: Cache management is hard, let's go copying... It turns out that my previous commit to make the EHCI stack cache aware on ARM devices wasn't quite correct, and the problem is actually much trickier than I thought. After having some fun with more weird transfer problems that appear/disappear based on stack alignment, this is my current worst-case threat model that any cache managing implementation would need to handle correctly: Some upper layer calls ehci_bulk() with a transfer buffer on its stack. Due to stack alignment, it happens to start just at the top of a cache line, so up to 64 - 4 bytes of ehci_bulk's stack will share that line. ehci_bulk() calls dcache_clean() and initializes the USB transfer. Between that point and the call to dcache_invalidate() at the end of ehci_bulk(), any access to the stack variables in that cache line (even a speculative prefetch) will refetch the line into the cache. Afterwards any other access to a random memory location that just happens to get aliased to the same cache line may evict it again, causing the processor to write out stale data to the transfer buffer and possibly overwrite data that has already been received over USB. In short, any dcache_clean/dcache_invalidate-based implementation that preserves correctness while allowing any arbitrary (non cache-aligned) memory location as a transfer buffer is presumed to be impossible. Instead, this patch causes all transfer data to be copied to/from a cache-coherent bounce buffer. It will still transfer directly if the supplied buffer is already cache-coherent, which can be used by callers to optimize their transfers (and is true by default on x86). Old-Change-Id: I112908410bdbc8ca028d44f2f5d388c529f8057f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169231 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 702dc50f1d56fe206442079fa443437f4336daed) Squashed the initial commit and a follow up fix. Change-Id: Idf7e5aa855b4f0221f82fa380a76049f273e4c88 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14libpayload: Add in a missing "static".Gabe Black
The readwrite_chunk was private to the usb mass storage driver, but wasn't marked as static which was upsetting the compiler. Change-Id: I0ef5c5f96a29f793dd43ff672a939902bad13c45 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169816 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8140e6145b3d072b7f12a924418570022207c065) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6648 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14payloads/external/SeaBIOS: move build directoryIdwer Vollering
Move SeaBIOS' build directory out of build/ This allows the user to delete build/ in the top dir and keep the built binary in payloads/external/SeaBIOS/seabios/out/ Change-Id: Ia7d515cd7e349beebcd9b62c9d956137acb73c82 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/6460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-14libpayload: Reduce media init timeout to 5 seconds.Shawn Nematbakhsh
Currently, we wait for up to 30 seconds for a device to become ready to respond to a TEST_UNIT_READY command. In practice, all media devices become ready much sooner. But, certain devices do not function with libpayload's USB driver, and always timeout. To provide a better user experience when booting with such devices, reduce the timeout to 5 seconds. Change-Id: Icceab99fa266cdf441847627087eaa5de9b88ecc Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169209 (cherry picked from commit 9e55204e92adca0476d273565683f211d6803e7a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6647 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14libpayload: Increase accuracy of timeout period for media init.Shawn Nematbakhsh
When bringing up media, we claim to wait for up to 30 seconds for a device to respond to our TEST_UNIT_READY command. Actually, we can wait far longer because we do not take into account execution delay. To improve timeout accuracy, make use of gettimeofday(), which calculates time based upon a CPU counter. This improves the user experience slightly when certain non-working USB devices are used. Change-Id: Id9605ecfc0a522d7a0b039fd8eac541232605082 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169208 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 1d3d535db83ff478c512e37f37015b43927b3efc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14Exynos: de-duplicate mct timer initializationStefan Reinauer
timer initialization is the first thing happening in the Exynos CPU's bootblock code. Hence we don't need to keep track of it in several places, and we don't need to do it over and over again (e.g. in each stage) Change-Id: I7bd9a0b7930fc9c37faabd62e3eecc3e5614a879 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168994 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5a95bc2bcab5a92c5e6c144005861bf731f59de3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14pit: snow: Fix snow, fix up pit write protect.Gabe Black
A recent change to support early firmware selection on ARM broke snow and was incompletely implemented on pit. This change fixes snow by applying the remaining part of the change that had been applied to pit, and also hooks up real values in the get_write_protect_state function. Change-Id: Ifef7ad1bf399f79353daec3dd46973f2b2022e37 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169120 Reviewed-by: David Hendrix <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 841773e048cd9cfbb64782059c24e29c467f17c8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-14lenovo/x200: Fix black screen on quick boot.Vladimir Serbinenko
Otherwise without USB when coreboot boots too quickly EC is confused and thinks that LID is closed and so powers off the backlight until user flaps the lid. Change-Id: I14dfaa62582de83fd4c9f9518e9436b3a3035366 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6651 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-08-14gm45: Set D0F0_SKPD on normal boot pathVladimir Serbinenko
Otherwise we get a warning on normal boot. Change-Id: Ida1e1d23e258438251d4ec2417f93ad14c3b9f7d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6652 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-14gm45: Set acpi_slp_type only once.Vladimir Serbinenko
It doesn't harm to set several times but it pollutes the log. Change-Id: I7aad7f0229a7d9d071ba844a1cfa123dffc4cacf Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6653 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-08-14libpayload: usbmsc: Split transfers into 64KB chunksDuncan Laurie
Add a new function to split transfer requests into chunks of 64KB in order to be as compatible as possible with devices that choke when sent large transfer requests. Change-Id: Id11990bd149af14af5535de4af47bda21d1ab51e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169170 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 4c413b007aa23da830877127dd556c4c38b43042) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6636 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14ARMv7/Exynos: Fix memory location assumptionsStefan Reinauer
This patch cleans out a lot of unused variables in the ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE which is similar to CONFIG_RAMBASE on x86. This gets rid of the hard coded assumption that on ARM coreboot is always executed at the lowest DRAM address. But in fact, this might not be true because we might want coreboot to live at the end of RAM, or in SRAM Change-Id: I03e992645f9eb730e39a521aa21f702959311f74 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168645 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14exynos5: Refactor crazy old U-Boot base address macros awayJulius Werner
All this samsung_get_base_address_of_device_with_a_really_long_name() boilerplate makes my eyes bleed... I think there are so much cleaner ways to do this. Unfortunately changing this ends up touching nearly every Exynos5 file, but I hope you agree that it's worth it (and the sooner we get it over with, the better... I can't bring myself to make another device fit into that ugly scheme). This also removes the redundant EXYNOS5 base address definitions from the 5420 directory when there are EXYNOS5420 ones, to avoid complete confusion. The new scheme tries to use EXYNOS5 for base addresses and exynos5 for types that are common between the two processors, and EXYNOS5420/exynos5420 for things that have changes (although I probably didn't catch all differences). Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167579 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13exynos5420: Enable relocatable module supportStefan Reinauer
Since we're now supporting ARMv7 relocations, we can enable rmodule support on Exynos 5420. This does not automatically enable relocatable ramstage. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ic3af1eabb3b816944587a46409224f778d941b8a Reviewed-on: https://chromium-review.googlesource.com/167403 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7b5afef4ee87fc3245ec887dfda873c529d8d04d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6629 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13Tegra,Tegra124: proposed layout for file hierarchy with exampleRonald G. Minnich
This change shows the source structure for nvidia Tegra and Tegra124 SOC. The problem we are trying to solve is that there is a large amount of common code in the form of .c and .h files across many different Tegra SOCs. The solution is to provide common code in a single directory, but not to compile in the common code directory; rather, we compile in a directory for a given SOC. Different SOCs will sometimes need different bits of code from the common directory. Tegra common code lives in tegra/, but there is no makefile there: if a Tegra common file is needed in a SOC, it is referenced via a Makefile in a specific Tegra SOC. Another issue is includes. Include files in the common directory might be accessed by a piece of code in an SOC directory. More problematically, code in the common directory might require a file in an SOC directory. We don't want to put the SOC name in an #include path, e.g. in a C file in tegra/ is very undesirable, since we might be compiling for a tegra114. On some systems this is solved by a pre-pass which creates a set of symbolic links; on others with nested #ifdef in the common code which include different .h files depending on CPP variables. In previous years, both LinuxBIOS and coreboot have tried these solutions and found them inconvenient and error-prone. We choose to solve it by requiring explicit naming of part of the path of files that are in the common directory. This requirement, coupled with two -I directives in the Makefile.inc, allows common and SOC C code to incorporate both common and SOC .h files. .c and .h files -- SOC or common -- name include files in the common directory with the prefix tegra/, e.g. SOC files will be included from the SOC directory if they have no prefix: The full patch of clock.h will depend on what SOC is being compiled, which is desirable. In this way, a common file can pick up a specific SOC file without creating symlinks or other such tricky magic. We show this usage with one file, soc/nvidia/tega124/clock.c. This compiles. The last question is where to put the prototype for the function defined in this file -- soc.h? Change-Id: Iecb635cec70f24a5b3e18caeda09d04a00d29409 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/171569 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 53e3bed868953f3da588ec90661d316a6482e27e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6621 Tested-by: build bot (Jenkins)
2014-08-13Falco: Patch to setup FUI (coreboot initializations) for falcoFurquan Shaikh
For now using the same gma.c and i915io.c files as for slippy Change-Id: Ieb09d0152d525aa090eeb86ebfa253d450d22820 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64373 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 3e119c7e22cb82677754413e56a125f4a372ad54) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-13Falco: Patch to enable correct port clock selection for dpFurquan Shaikh
This is required only for haswell since the register configs have changed. Also, created mainboard specific header file Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945 Signed-off-by: Furquan Shaikh <furquan@google.com> Conflicts: src/mainboard/google/slippy/gma.c src/mainboard/google/slippy/i915io.c Conflicts: src/mainboard/google/slippy/gma.c Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5 Reviewed-on: https://gerrit.chromium.org/gerrit/66853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6602 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-13Falco/Slippy: Patch to refactor haswell/gma.c and ↵Furquan Shaikh
mainboard/google/slippy/i915io.c A large portion of documented registers have been initialized using macros. Only a few undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant calls. However, some more work is required to correctly identify which calls are not required. All the io_writes are replaced by gtt_writes. Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66204 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6600 Tested-by: build bot (Jenkins)
2014-08-13lenovo/x200: New mainboard.Vladimir Serbinenko
Change-Id: I64e59648064d5875907b5057e2f9f72f2c5997b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6631 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-13lenovo/h8: Support uwb radio.Vladimir Serbinenko
It's the third minipcie slot in x200. Change-Id: Ibfa8d787698cd23b4abcffe5cff2d62039cf0f86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6641 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13gm45: Allow skiping voltage config.Vladimir Serbinenko
Change-Id: I81b9966212d09d4d2561b3adc20d6d8a8a200f4b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6630 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-13ARMv7: drop dead code from Makefile.incStefan Reinauer
This commented out code is a left over from x86. Change-Id: Ice806000c73d5a068962914d067d4de7b3d75f45 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168961 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 9d700cf35d2283a088e704c0ebd34e6f58f54993) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6639 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-13util/inteltool: Typo in dump output for 'GP_IO_SEL3'Edward O'Callaghan
The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header is incorrectly reported as 'GPIO_SEL3'. Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6459 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13southbridge/amd/cimx/sb800: Uninitialized variables in config funcEdward O'Callaghan
Both 'SbSpiSpeedSupport' and 'UsbRxMode' are uninitiated upon return from a 'sb800_cimx_config()' call. Change-Id: I32237ff97fafc3e69627d427e54268dcb039e12c Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-13chromeos: On ARM platforms VBNV lives in the ECStefan Reinauer
This patch renames the x86 way of doing things to explicitly mention CMOS (which is not available on our ARM platforms) and adds an implementation to get VBNV through the Chrome EC. We might want to refine this further in the future to allow VBNV in the EC even on x86 platforms. Will be fixed when that appears. Also, not all ARM platforms running ChromeOS might use the Google EC in the future, in which case this code will need additional work. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901 Reviewed-on: https://chromium-review.googlesource.com/167540 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6616 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13arm: libpayload: Add cache coherent DMA memory definition and managementJulius Werner
This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12libpayload: usbhub: Don't clear PSC unless it was setJulius Werner
The current USB hub code always clears the port status change after checking it, regardless of whether it was set in the first place. Since this check runs on every poll, it might create a race condition where the port status changes right between the GET_PORT_STATUS and the CLEAR_FEATURE(C_PORT_CONNECT), thus clearing the statrus change flag before it was ever read. Let's add one extra if() to avoid that possible headache. Change-Id: Idd46c2199dc6c240bd9ef068fbe70cccc88bac42 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168098 (cherry picked from commit f7f6f008f701ab3e4a4f785032d8024d676e11cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6617 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12tegra124: Implement the monotonic timer by reading the 1us timer register.Gabe Black
It turns out there's a register in tegra which automatically counts at 1us increments. It's primarily intended for hardware to use (I think to drive other timers) but we can read it ourselves since a 1us timer is exactly what we need to support the monotonic timer API. Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172044 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 161a39c53404ea0125221bbd54e54996967d6855) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6620 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-12tegra124: Add stack related config options to the Kconfig.Gabe Black
Otherwise the stack ends up down at 0 and has 0 bytes. Change-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171015 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3e69a477474697bcbc40762ec166e8a515d8b0c2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12tegra124: Add some make rules which will wrap the bootblock in the BCT.Gabe Black
These rules slip into the normal bootblock preperation process and use the cbootimage utility to wrap it in a BCT. Change-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170924 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cf4a9b0712c21b885bb59310671fb87e38abb665) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12gm45: Move S3 detection to enable stage.Vladimir Serbinenko
Also move it to NB to be in line with other. Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12i82801ix: Make RP04 optionally hotpluggable.Vladimir Serbinenko
Change-Id: I34a1ae4bff22db6ee55fa511de39bdfd5dd92c7e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Reserve RAM for ME if it's active.Vladimir Serbinenko
Change-Id: Icd2b075cec9461f9d6028a8c845f6900b6fe04c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6628 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12gm45: Allow coexistance with ME firmware.Vladimir Serbinenko
Change-Id: I08ca5eec94c70b43789122266d68af149772385c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.ChromeOS Developer
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12exynos5420: minor clean-up memory related stuffDavid Hendricks
This cleans up a few minor things (mostly #defines) of the memory code for exynos5420, pit, and kirby. Specifically: - CONCONTROL.empty is read-only, so don't try to set it and also get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define. - MEMBASECONFIG* overlaps members of the mem_timings struct and are mainboard-dependent anyway, so get rid of 'em. - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may have been deprecated. - Same with TIMING* #defines. - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17 Reviewed-on: https://chromium-review.googlesource.com/167500 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12exynos5420/pit: re-factor membaseconfig0/1 usageDavid Hendricks
membaseconfig0/1 are utterly dependent on the mainboard's particular DRAM setup. This defines their values in the mem_timings struct for pit. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0 Reviewed-on: https://chromium-review.googlesource.com/167488 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579) exynos5420: necessary updates for DRAM This updates DRAM usage for Exynos5420 so that we can actually use 3.5GB: - Memory chips used with Exynos5420 may have 16 row address lines. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2 Reviewed-on: https://chromium-review.googlesource.com/167489 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1) Squashed two related commits. Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420David Hendricks
This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte. Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now. This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See <http://crosbug.com/p/20577>. This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins)
2014-08-12nvramtool: plug some memory leaksPatrick Georgi
Change-Id: I8f672b872862d3448ccd2cf28fd3c05b0108ff8b Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6561 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12Exynos5420: ddr3: fine tuning the DDR3 timing valuesDavid Hendricks
Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12libpayload: ehci: Set explicit terminate bits in dummy_qh next pointers.Julius Werner
The EHCI host controllers in Samsung Exynos SoC seem to be a little more picky than Intel ones. When they reach the dummy_qh in the periodic frame list, they try to access the next qTD pointer even though it's NULL, and run into a HostSystemError. This patch explicitly sets the Terminate bit on those pointers to mark them invalid. Change-Id: I50fa79bbf1c5fab306d7885c01efd66b13e279b8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66884 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c575a5c958ce88732d28044352c89418bcd5ea86) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12Exynos5420: Remove code for enabling read levelingDavid Hendricks
This patch intends to remove all code which enables hardware read leveling. We need to disable h/w read leveling because new ASV table is merged in kernel (which is based on the new characterization condition) and new characterization environment has h/w read leveling disabled, so we should also disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly), improve LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. This was ported from: https://gerrit.chromium.org/gerrit/66070 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83 Reviewed-on: https://chromium-review.googlesource.com/66994 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6610 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12exynos5: Refactor board-specific parts out of USB PHY codeJulius Werner
This patch moves around some of the existing Exynos5 USB 2.0 PHY code to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS GPIOs (which are completely board-specific) into the mainboard code and makes sure to only initialize PHYs on the boards that actually need them. It also removes the USB 3.0 PLL hack that was needed on Snow from the Pit and Kirby boards (which do not have that PLL anymore). Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66887 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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