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The body contains a `#` and GNU make 4.3 disagrees with earlier versions
if it should be treated as a comment. Turn it into a `define` which has
clearer semantics regarding comments (interpretation is supposed to be
deferred until the variable is expanded).
Change-Id: I589542abbd14082c3ecc4a2456ebd809fb6911ea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38793
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Interpretation if # starts a comment inside a variable definition varies
between GNU make versions. Use a wildcard to match the first # and use
`sed` instead of `grep | cut` to avoid unbalanced quoting chars.
Tested with GNU make 4.2.1 and 4.3. Both produce the same output as
4.2.1 did before the patch.
Change-Id: Ib7c4d7323e112968d3f14ea0590b7dabc57c9c45
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Changes:
20200110: https://acpica.org/node/176
20191213: https://acpica.org/node/175
20191018: https://acpica.org/node/174
20190816: https://acpica.org/node/172
Change-Id: Ifaa0d1c79802872c1a822c1108d2a50bc60c8fd8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38347
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Add additional information on non-debian cli tools
* Improve spellings and descriptions to the best of my knowledge
Adding info about needed tools in other distribution's package
managers was requested at the coreboot beginner's workshop at 36C3.
Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237
Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Calculate the correct MMCONF size, which was only correct for
256MiB, but not for smaller values.
Tested on HP Z220:
Fixes "Not using MMCONF" warning in dmesg.
Change-Id: I986681126637c28f6442ab7c34acea5bb58ea3d2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
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* Use new ACPI syntax
* Return either 0 or 0xf for PCI root port. That will make the
device show up in Windows. This might help users and possibly
Windows drivers working with PCIe ports.
Change-Id: I1e76b735ab1472f6a4ea493c733cd6b2e6fca29e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Move ME firmware SKU types into common code.
2. Define ME_HFS3_FW_SKU_CUSTOM SKU.
TEST=Verified on hatch & soraka.
Change-Id: Iaa4cf8d5b41c1008da1e7aa63b5a6960bb9a727b
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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By updating the FSP submodule we now got all FSP headers from within
that repo. This commit changes the default paths to use these and
fixes some include paths to allow the usage of
vendorcode/intel/edk2/UDK2017 together with the official Intel
distribution.
We are also adding back the CHANNEL_PRESENT enum, that is
missing in the official headers.
This was tested on the Razer Blade Stealth (late 2019).
Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some of the common memory code that was being performed in
mainboard has moved into the soc to reduce redundant code.
This change adapts volteer to use Tiger Lake's new common code.
BUG=b:145642089, b:145238504, b:145564831
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, boot to kernel, "cat /proc/meminfo" and verify it reports
"MemTotal: 8038196 kB".
Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The Picasso no longer intends to implement a hybrid romstage,
opting instead for a more traditional bootblock/romstage/ramstage.
Update the documentation to reflect this. Clarify additional
details that have come to light since the last revision.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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When acpi_write_dbg2_pci_uart is called and no pci uart is available the
function prints "Device not found" as an error. This is not correct.
Change the error level to BIOS_DEBUG so coreboot reports the device is
not available but doesn't flag this as an error.
BUG=N/A
TEST=build
Change-Id: I14567bcfcf5a6ff427e418d15bc2675ae7a28f53
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=N/A
TEST=tested on facebook monolith
Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add function to return the fixed io decode ranges contained in register
0x80 of the LPC interface.
BUG=N/A
TEST=build
Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We haven't been able to update IASL in 8 months because of this
conflict. Ignoring it doesn't make things any worse than they are now.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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To be compliant with ACPI specification, device object requires either
a _HID or _ADR, but not both.
Change-Id: I45cf2b8d455aa4d288de1ac53cf9ae801f758a9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38351
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's really hard to power up this laptop with the lid closed so let's
make it open by default, as done on many other laptops.
Change-Id: I5bb2f716865c2bb569a4735f135842526043713c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Make sure MINIMAL_PCI_SCANNING has right dependency over PCI kconfig
symbol.
Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38801
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default
enable for all x86 systems) with another Kconfig that can be selected
by platform that actually planning to use it.
TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default.
Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Part of the design of vboot persistent context is that the workbuf gets
placed in CBMEM and stays there for depthcharge to use in kernel
verification. As such, the space allocated in CBMEM needs to be at least
VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE.
In the VBOOT_STARTS_IN_ROMSTAGE case, prior to this CL, vboot_get_context()
would get invoked for the first time after CBMEM comes up, and it would
only allocate VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE.
Initialize the workbuf directly in vboot_setup_cbmem() instead with the
correct VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE.
BUG=b:124141368, chromium:994060
TEST=make clean && make test-abuild
TEST=boot on GOOGLE_EVE with VBOOT_STARTS_IN_ROMSTAGE set
BRANCH=none
Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38778
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selecting STM on an arbitrary platform would likely result in a brick,
so let's hide the prompt by default.
Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <cedarhouse1@comcast.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37161
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the panel-power sequencer is not configured, libgfxinit falls back
to very conservative defaults (210ms before EDID is probed). This
results in a boot penalty of >100ms (depending on how long it takes
to probe other ports).
Values are taken from the VBTs already checked in. Untested.
Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The second digital display connector is unused, but strapped as if it
were used.
Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can
ignore these.
Based on schematics only, not tested.
Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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T500 and W500 (Coronado-5) use both digital display connectors. Both
with the DP AUX channel implemented, so add DP2 to the list.
Versions with a discrete GPU don't use external, digital connectors
but seem to have the straps correctly configured. So we hopefully
won't have to handle these specifically.
Based on schematics only, not tested.
Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The first digital display connector is unused, but strapped as if it
were on later revisions. The DP AUX channel of the second connector
is implemented, though, so add DP2 to the list.
Versions with a discrete GPU don't use external, digital connectors
but seem to have the straps correctly configured. So we hopefully
won't have to handle these specifically.
Based on schematics only, not tested.
Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Some board revisions have the straps for display port detection
wrongly configured. So with a single list covering all variants'
possible outputs, we make libgfxinit probe unimplemented ports
which may stall the GMBUS controller and delay the boot for some
hundred milliseconds.
This just copies the list to the various variants with different
display ports, so we can test the actual changes individually.
Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This has been implemented last year.
Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38533
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The attempt to install pfSense on hard disk on PC Engines apu2 board
ended up in a SATA driver error. The problem is related only to BSD
and didn't occur with Linux kernel. Changing SATA mode from IDE to
AHCI solved the problem.
Additionally AHCI is faster than IDE so it speeds up the installation.
Since AHCI works perfectly with SeaBIOS, Linux and BSD, make it a default
choice for all Hudson southbridges.
Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35891
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change tcc offset from 0 to 15 degree celsius for lick.
BUG=b:147198431
BRANCH=octopus
TEST=Build, and verify test result by thermal team.
Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com>
Change-Id: Ife6b02321145837e05c82f979998466b83317f86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the create_coreboot_variant.sh and kconfig.py to support the
zork baseboard. Full template files will be added in a later CL.
BUG=b:148161697, b:148281637
BRANCH=None
TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the
changes staged are correct.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add initial configuration for GSPI, I2C and UART ports and leave them in
disabled state.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the GPIO groups to be routed to the GPE0 block.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add compute and PCH Global device IDs with the concerned devices turned
off.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Move some of the common memory code that was being performed in
mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Created a new Google baseboard named volteer from scratch.
BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.
Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add new SPD files for drallion:
1. Hynix H5AN8G6NDJR-XNC
2. Samung K4AAG165WA-BCWE
3. Samung K4A8G165WC-BCWE
BUG=b:148642500
TEST=Compile successfully and check SPD info in cbmem log.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change GPP_C10 from pltrst to deep to meet the warmboot power sequence.
BUG=b:146935222
TEST=measure WWAN power sequence is meet spec
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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BUG=b:148410914
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable the dGPU on the Lenovo T440P. It uses the same code (roughly) of
the T430S. By default, it is set to be disabled however it can be
enabled via the nvram option enable_dual_graphics. Removed hybrid graphics
options too as they are not valid for the T440p. Tested on a T440P with
Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine
with Windows 10 1909 (machine check exception bluescreen).
Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I708385bca8edcd74b0d4c0a3ecc181b6ccd30c2b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38721
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both versions are correct, but especially for one liners indenting them
with four spaces instead of using ``` blocks helps readability of the
source file.
Change-Id: Ie2543c8c4cccefd74e966f784e651ed7dc3a9252
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38720
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since most of Bloog series SKUs need to disable DRRS support.
If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support,
return vbt_blooguard.bin for other SKUs to disable DRRS support.
Bipship follow blooguard to disable DRRS support.
BUG=b:148892903, b:147021309
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is bipship.
Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add the capability to update the Flash Descriptor directly instead
of raising a Segmentation Fault. In this way it will be possible to
add a Kconfig options to modify the ifd descriptor at build-time.
Change-Id: Id3db09291af2bd2e759c283e316afd5da1fb4ca7
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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send_heci_reset_req_message()
Below changes have been implemented in send_heci_reset_req_message():
1. Modify return values to align with other functions in the same file.
2. Add additional logging.
3. Replace macro definitions of reset types with ENUM.
4. Make changes to caller functions to sync with new return values.
5. Rename send_heci_reset_req_message() to cse_request_global_reset().
Test=Verified on hatch board.
Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Below changes are implemented:
1. Fix typos.
2. Rename 'padding' field of hmrfpo_get_status_resp struct to
'reserved' to match with ME BWG Guide.
3. Add documentation for HMRFPO Status.
TEST=Build and boot hatch
Change-Id: I4db9bdf7386c48e17ed0373cf334ccff358d1951
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Below changes are done:
1. Rename below functions to have consistent naming:
set_host_ready() -> cse_set_host_ready()
wait_cse_sec_override_mode() -> cse_wait_sec_override_mode()
send_hmrfpo_enable_msg() -> cse_hmrfpo_enable()
send_hmrfpo_get_status_msg() -> cse_hmrfpo_get_status()
2. Additional debug messages are added in cse_wait_sec_override_mode().
TEST=Build and Boot hatch board.
Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Below changes are implemented:
1. Move HFSTS1 register definition to SoC since HFSTS1 register definition
is specific to a SoC. Moving structure back to SoC specific to avoid
unnecessay SoC specific macros in the common code.
2. Define a set of APIs in common code since CSE operation modes and
working states are same across SoCs.
cse_is_hfs1_com_normal(void)
cse_is_hfs1_com_secover_mei_msg(void)
cse_is_hfs1_com_soft_temp_disable(void)
cse_is_hfs1_cws_normal(void)
3. Modify existing code to use callbacks to get data of me_hfs1 structure.
TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards.
Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Rather bail out than run into undefined behavior.
Change-Id: Ife26a0abed0ce6bcafe1e7cd8f499618631c4df4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: <cedarhouse1@comcast.net>
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Change-Id: Ic2ba1f9b744014f97d318671bf86468f4d6c6469
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Update the QUP DFSR cmd to clear the SW control and also update the perf
registers when M is set. While at it also update the d_2 values.
Tested: validated DFSR clock configuration and M/N/D values.
Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Developer/Reviewer, be aware of this patch from Mistral:
https://review.coreboot.org/c/coreboot/+/33425/18
Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add golang and libelf-dev so LinuxBoot can be built from the
coreboot-sdk docker container.
BUG=N/A
TEST=build
Change-Id: I7a156fc24a6040d73467e06c16139bf298a29740
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38751
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enabling an assertion in vb2_member_of() results in coreboot
linking vb2ex_abort() and vb2ex_printf() in ramstage.
Move these two functions from vboot_logic.c to vboot_lib.c,
which is should be enabled in all stages if CONFIG_VBOOT_LIB
is enabled. Note that CONFIG_VBOOT_LIB is implied by
CONFIG_VBOOT.
Relevant vboot_reference commit: CL:2037263.
BUG=b:124141368, chromium:1005700
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ica0103c5684b3d50ba7dc1b4c39559cb192efa81
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Wait for HPD DP unless HDMI is plugged.
Some Type-C monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Similar to that of b:72387533 however our DP&HDMI are beind a MST.
See commit d182b63347c744c on how this was done for mainboard/fizz.
BUG=b:147992492
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I19d40056e58f1737f87fd07d62b07a723a63d610
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using
PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board
to enable the dGPU.
Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The STM support aligns the smm_save_state_size. However, this creates
issue for some platforms because of this value being hard coded to
0x400
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: Ia584f7e9b86405a12eb6cbedc3a2615a8727f69e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38734
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA
1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly
utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which
is compatible with AGESA 1.0.0.4 version.
Cut out the changes introduced in CB:11225 exclusively for apu2 board.
TEST=boot PC Engines apu2 and launch Debian Linux
Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8
and disable Fast PKG C State Ramp (IA, GT, SA).
BRANCH=hatch
BUG=b:143501884
TEST=build and verify that noise reduce.
Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I5f053c1270bab71aeab3bb785c60417419736b44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This update is a combination of all four of the patches so that the
commit can be done without breaking parts of coreboot. This possible
breakage is because of the cross-dependencies between the original
separate patches would cause failure because of data structure changes.
security/intel/stm
This directory contains the functions that check and move the STM to the
MSEG, create its page tables, and create the BIOS resource list.
The STM page tables is a six page region located in the MSEG and are
pointed to by the CR3 Offset field in the MSEG header. The initial
page tables will identity map all memory between 0-4G. The STM starts
in IA32e mode, which requires page tables to exist at startup.
The BIOS resource list defines the resources that the SMI Handler is
allowed to access. This includes the SMM memory area where the SMI
handler resides and other resources such as I/O devices. The STM uses
the BIOS resource list to restrict the SMI handler's accesses.
The BIOS resource list is currently located in the same area as the
SMI handler. This location is shown in the comment section before
smm_load_module in smm_module_loader.c
Note: The files within security/intel/stm come directly from their
Tianocore counterparts. Unnecessary code has been removed and the
remaining code has been converted to meet coreboot coding requirements.
For more information see:
SMI Transfer Monitor (STM) User Guide, Intel Corp.,
August 2015, Rev 1.0, can be found at firmware.intel.com
include/cpu/x86:
Addtions to include/cpu/x86 for STM support.
cpu/x86:
STM Set up - The STM needs to be loaded into the MSEG during BIOS
initialization and the SMM Monitor Control MSR be set to indicate
that an STM is in the system.
cpu/x86/smm:
SMI module loader modifications needed to set up the
SMM descriptors used by the STM during its initialization
Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Add detailed instructions on how to unlock protected SPI ranges and
flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by
exploiting stock BIOS security issues.
Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst
to deep in order to met power off timing.
BUG=b:143733039
TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We set MPS to speed_to_default_mps(speed) initially
but later compare maxpacketsize with 8 to change mps.
So compare with speed_to_default_mps(speed) to determine
if we need to change settings here.
BUG=b:147783572
BRANCH=none
TEST=works with 12Mbps/8MPS USB device
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38556
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Enable PCIe port for dGPU
2. Change WLAN PCIe port from port 14 to port 7
BUG=b:147249494
TEST=Ensure dGPU and WLAN shows up with lspci.
Change-Id: Iea3292be7d8029c35847118228bbb773418632a1
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.
Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1
BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting.
They should be NF1.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This change adds support for allocating resources for PCI express hotplug
bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI
subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of
non-prefetchable memory, and 8 KiB of I/O space to any device with the
PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which
indicates hot-plugging capability. The resource allocation is configurable,
please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig.
In order to support the allocation of hotplugged PCI buses, a new field
is added to struct device called hotplug_buses. This is defaulted to
zero, but when set, it adds the hotplug_buses value to the subordinate
value of the PCI bridge. This allows devices to be plugged in and
unplugged after boot.
This code was tested on the System76 Darter Pro (darp6). Before this
change, there are not enough resources allocated to the Thunderbolt
PCI bridge to allow plugging in new devices after boot. This can be
worked around in the Linux kernel by passing a boot param such as:
pci=assign-busses,hpbussize=32,realloc
This change makes it possible to use Thunderbolt hotplugging without
kernel parameters, and attempts to match closely what our motherboard
manufacturer's firmware does by default.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The eltan verified_boot is using the vboot 2.1 data structures and code,
as well as the fwlib21 build target, they are all deprecated. Refer to
CB:37654 for more information.
The verified_boot code is updated to use the vb2 structures and code and
make sure only public functions are used.
BUG=N/A
TEST=build
Change-Id: I1e1a7bce6110fe35221a4d7a47c1eb7c7074c318
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This define is used to set up the STM SMM Descriptor table tr entry.
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: Iddb1f45444d03465a66a4ebb9fde5f206dc5b300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ClearControl Function which is needed for a follow-up patch.
Change-Id: Ia19185528fd821e420b0bdb424760c93b79523a4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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BUG=b:139481313
Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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With Audio DSP OSC qualification disabled from S0ix criteria.
S0ix is achieved before the DSP is suspended. When driver tries
to suspend DSP its already turned off.
BUG=b:139481313
Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate CPUID entry between KBL and CFL.
CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL
CPUID (0x806EA) for CFL-D0.
TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with
CPUID 0x806EA.
Change-Id: I078dd7860891896b512967dc8dec5dd94d069193
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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The current MP init timeout is hardcoded as 1s. To support
platform with many cpus, the timeout needs to be adjusted.
The number of cpus is calculated as:
number of sockets * number of cores per socket *
number of threads per core
How long the timeout should be set to, is heuristic.
It needs to be set long enough to ensure reboot stability,
but not unreasonable so that real failures can be detected
soon enough, especially for smaller systems.
This patch sets timeout to be minimum as 1 second, while each
cpu adds 0.1 second.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The SMBus support is identical between stoneyridge and picasso.
Unify on common support code.
Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Set HeciEnabled = 1 on puff device tree to turn on
Intel ME communication interface.
BUG=b:143232330
BRANCH=None
TEST=Build puff and boot up OS.
ran lspci and confirmed there is a HECI device.
00:16.0 Communication controller: Intel Corporation Device 02e0
Change-Id: I2debb885022ae31e395869d014a91824b5dd980c
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iac3ae21a381119bd0f24f68d4dd991817f2ff51f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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libpayload passes argc and argv to main(), and ignoring these arguments
causes a compile time error when using LTO.
Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 6ef33b99:
2019-11-22 Hung-Te Lin futility: updater: refactor: unify
getting temp files for firmware images
to commit id 0e97e25e:
2020-01-23 Julius Werner 2lib: Fix struct vb2_hash the way it was
meant to be
Change-Id: I539aba2f283804f67ff3ff4f98324b3d10b2bb54
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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According to the C standard, accessing the NULL pointer (memory at
address zero) is undefined behaviour, and so GCC is allowed to optimize
it out. Of course, accessing this memory location is sometimes
necessary, so this optimization can be disabled using
-fno-delete-null-pointer-checks. This is already done in coreboot, but
adding it to xcompile will also disable it for all the payloads. For
example, coreinfo compiled with LTO libpayload crashes when this flag
isn't set, presumably because the compiler is optimizing something out
that it shouldn't.
Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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acpi_device_scope() will return NULL if it is unable to find the path
of the parent device. Return early if this is the case to prevent a null
pointer dereference.
Change-Id: I3eff1c1e3477c75c7130b52898de7d59692ba412
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1409672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38669
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is found that keyboard backlight in T440p is enabled by clearing
bit 3 of EC RAM 0x01. This patch sets has_keyboard_backlight in
devicetree.cb and also corrects the CMOS configuration.
Change-Id: Ib4c2b1591d26e2bb33f9549e3933efe9a6e0b043
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Dennis Witzig <dennis@wtzg.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Configure xHCI, xDCI according to board design
BUG=none
BRANCH=none
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Asserting reset in RO instead of in RW has no impact on security or
performance, but it does limit improvements to this process later.
This fix removes reset line control from RO and makes these variants
consistent with other hatch variants.
This fix reinforces the concept from commit fcd8c9e99e
(hatch: Fix FPMCU pwr/rst gpio handling).
BUG=b:148457345
TEST=None
Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Configure GPP_H22 as output pin for BOMACO mode enabled.
BOMACO stands for "Bus Off Memory Alive Core Off".
BUG=b:146081272
TEST=emerge-mushu coreboot
Change-Id: Ic35e55771d76b7254bcb457fcb38f37433b9ad67
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38210
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set CPU ID and cores to EC then EC will adapt power table
according to the CPU ID and number of cores.
BUG=b:148126144
BRANCH=None
TEST=check EC can get correct CPU id and cores.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37944
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For the up-to-date list of Windows versions follow this link:
https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi
Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This GPIO dumping was implemented using the
Document Number: 341080-001
Intel® 495 Series Chipset Family On-Package Platform Controller Hub
Volume 1 of 2
datasheet. The GPIO community ports can be found in table 36-1, while
the community and pin descriptions are taken from
linux/pinctrl/intel/pinctrl-icelake.c .
This commit was tested on the late 2019 Razer Blade Stealth with 1065G7
and Chipset 495 PCH and the output manually compared against
linux/pinctrl-intel.
Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Newest clang compilers warn about "misleading indentation", and because
warnings-are-errors in our builds, that breaks the build.
The lzma code base is vendored in, so we might just have to update it,
but that's a bigger effort than just removing a couple of spaces (the
coding style of the file is horrible, but I will only change it as much
as the compilers ask for).
BUG=chromium:1039526
Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove EC_HOST_EVENT_MKBP from kohaku's EC_SCI_EVENTS mask, so that
MKBP events don't generate an SCI. The EC is also being changed to use
host events to wake up the system, and use the EC_INT_L line for MKBP
IRQ signalling. Otherwise, there would be two IRQs generated for MKBP
events.
BUG=b:144122000
BRANCH=firmware-hatch-12672.B
TEST=System shows ACPI interrupt as the wakeup IRQ, and the
MKBP host event is properly processed as well.
Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new functions to get (from the EC):
1) The number of USB-PD ports
2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS)
BUG=b:146506369
BRANCH=none
TEST=Instrumented calls to these and verified the data
Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The new host command provides these static capabilities of each USB-PD port:
1) Port number
2) Power role: source, sink, dual
3) Try-power role: none, sink, source
4) Data role: dfp, ufp, dual
5) Port location: these come from power_manager
BUG=b:146506369
BRANCH=none
TEST=compiles
Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The help output suggests clean-docker should be used to remove the
docker coreboot containers and images. The Makefile actually supports
the docker-clean target.
Corrected the help output to reflect the actual Makefile target.
BUG=N/A
TEST=build
Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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