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2021-02-06mb/intel/shadowmountain: Add bootblock and verstage codeV Sowmya
This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-02-06mb/google/zork: Adjust Dirinboz H1 I2C CLKKevin Chiu
Adjust H1 I2C CLK: 404kHz -> 391 kHz BUG=b:178656936 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-06mb/google/dedede/var/galtic: Configure I2C high and low timeFrankChu
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:179100924 TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and low time as 1680 ns. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-06intel: Define `RCBA_LENGTH` in Kconfig and use itAngel Pons
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06Documentation: Codify some guidelines for headers and chain-includingJulius Werner
There has been some repeated discussion about how header includes should be formatted, specifically on the topic of chain-including. The coding style currently doesn't say anything about the topic but clearly people have some basic assumptions. This patch tries to codify some common ground rules that are supposed to reflect the existing practice. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06mb/google/guybrush: First pass GPIO configuriation for GuybrushMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06mb/google/guybrush: Add stubs to configure GPIOsMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAYKyösti Mälkki
It was commented that the need for the delay was mainly related to external displays and only with VBIOS execution. Move the delay such that it is done only when we actually need to execute the VBIOS aka option rom. A delay is currently only defined for librem/purism_bdw in its Kconfig. As the description of the issue sounds like it would equally happen on other platforms when VBIOS is involved, promote the Kconfig visible option to global scope. Change-Id: I4503158576f35057373f003586bbf76af4d59b3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06soc/amd/stoneyridge: Create chipset_power_state in romstageKyösti Mälkki
Move chipset_power_state initialisation from early ramstage to romstage cbmem hook, like everyone else does. Change-Id: Ib9189a70996ac6cf4515a0d504eb687941a6b5e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06sb,soc/intel: Add wake source fields in GNVSKyösti Mälkki
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/amd/picasso: add UPD for RV2 USB3 phy setting adjustChris Wang
add UPD for RV2 USB3 phy setting adjust. Note: it only for RV2 silicon and not available for RV/PCO. Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/amd/cezanne/iomap: move MMIO range comment above MMIO rangesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib7e47e3ba29d171266792fc1ffa8f18e314dc770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50289 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/amd/cezanne/fch: add ACPI I/O port setupFelix Held
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from the reference code, but not the PPR. I've submitted a change request for the PPR, so this mismatch might go away in the future. The case for HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends up being identical to the function in soc/amd/picasso, I'll move it to the common AMD SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig optionFelix Held
This was the only I/O base address in Kconfig, no board changed it and if a board changed it, it needs to make sure that it won't overlap with other I/O resources, so just use the same value as constant in the define instead of the value from Kconfig. Also remove the PICASSO_ prefix from ACPI_IO_BASE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05mb/gigabyte/ga-h61m-series: Drop broken thermal.aslAngel Pons
Was copy-pasted from another board and causes ACPI errors on Linux. Change-Id: I9d62462fb7ddc788d08489bf82b110aeae6a1ffc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-05soc/amd/cezanne: populate some FSP-M UPDsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05soc/amd/common: Refactor single GPIO programmingKyösti Mälkki
Make it clearer all the GPIO bank register programming parameters originate from the same soc_amd_gpio entry. Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42691 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/amd/common: Separate single GPIO programmingKyösti Mälkki
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array. Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42807 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/mediatek/mt8192: Use LZ4 compression for MCUsYu-Ping Wu
For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot process. The loading (plus decompression) time of mcupm.bin and sspm.bin is consistently reduced by 8ms, respectively. BUG=b:177389446 TEST=emerge-asurada coreboot TEST=Hayato booted up BRANCH=none Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-05device/device.c: Print done at end of assign_resources()Frans Hendriks
First and last printk() log the same string. Add done at end of function. BUG = N/A TEST = Build and boot faceboot FBG1701 Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05device: correct code styleFrans Hendriks
Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition and loop bodies. - Use `__func__` to print the current function's name. - Reflow pointer dereferences to fit in a single line. - Adjust the `*` position in pointer variable declarations. - Drop unnecessary `else` statements. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speedTim Chu
Override SMBIOS type 4 max speed. This field should be maximum speed supported by the system. 3900MHz is expected for Cooper Lake. Tested=Execute "dmidecode -t 4" to check max speed is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05arch/x86/smbios: Correct SMBIOS type 4 max speedTim Chu
Now smbios type 4 max speed field will use the maximum speed of processor itself if CPUID value can be accessed. However, this field should be the maximum processor speed supported by the system. Here we use smbios_cpu_get_max_speed_mhz only to get correct value. Tested=Execute "dmidecode -t 4" to check max speed is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05mb/google/zork: update telemetry settings for WoomaxKane Chen
Improve performance and meet stardust test requirement. PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586) PcdSet32(PcdTelemetry_VddcrVddOffset, 0) PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674) PcdSet32(PcdTelemetry_VddcrSocOffset, 0) BUG=b:176156237 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/intel/skylake/acpi/irqlinks.asl: Fix typo in commentElyes HAOUAS
Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50269 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05payloads/libpayload/arch/arm64/mmu.c: Fix typo in commentElyes HAOUAS
Change-Id: Ieb10a881ef1d983f11318f0f6934491fd19fd0bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-05mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAMTim Wawrzynczak
BUG=b:178681161 TEST=abuild Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05mb/apple/macbookair4_2: Add ACPI support for ECEvgeny Zinoviev
Add ACPI support for battery, AC and lid. I don't have MacBook Air 4,2 to test, but: - I tested it on 5,2; - I found decompiled DSDT for 4,2 and compared registers and bits, they are the same as on 5,2. So it should work. Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05soc/intel/alderlake: Refactor PCIE port configEric Lai
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-05soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one writeAngel Pons
This is what Lynxpoint does. It is equivalent, but simpler. Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47045 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05ec/apple: Add ACPI code for Apple MacBooksEvgeny Zinoviev
- Move ACPI code for Apple MacBooks to a separate directory to avoid its duplication in mainboards - Add AC and lid implementations for newer generations - Rewrite old code using the new ASL syntax Tested on MBA 5,2, MBP 8,1 and MBP 10,1. Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05mb/google/dedede: Create kracko variantTony Huang
Create the kracko variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:178092096 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_KRACKO Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-04soc/amd/common/block/acpi/pm_state: add missing includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04soc/amd/picasso/fch: add missing iomap.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iea9666fe4f61fb503fee4060a90ec75e2d70c24f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04mb/google/zork/variants/vilboz: Enable BayHub lv2 driverJohn Su
Enable this driver along with power saving. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04drivers/generic/bayhub_lv2: Add driver for BayHub lv2John Su
Add a driver which puts the device into power-saving mode. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04vendorcode/intel/Makefile: Add x86_64 supportPatrick Rudolph
This allows to compile FSP related tools (like the FSP loader) in x86_64 mode, but it doesn't add support for properly running x86_32 FSP on x86_64. This is handled in a separate patch. Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`Angel Pons
This partially reverts: - Commit 77d3b655ed - Commit 487c1a24f5 - Commit 875c21f491 - Commit c4d1b47ad9 - Commit b96c358751 - Commit 9cbf26d18e It is intentional to use <device/pci_ops.h> whenever one needs to use PCI config access. The bootblock.c files needing I/O config do not need to be an exception to this. Change-Id: Ifba05717dad404a844618815c5347a05e07a3362 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04acpi: Add support for reporting CrashLog in BERT tableFrancois Toguo
Crash Data are collected and sent to the OS via the ACPI BERT. BUG=None TEST=Built, and BERT successfully generated in the crashLog flow. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04mb/google/volteer: update thermal table for EldridNick Chen
1. Add pl4 value 2. Change policies passive with sensor 0 and 1 3. Change granularity value with pl1 and pl2 BUG=b:178768749 TEST=make buildall Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mb/prodrive/hermes: Use some board settings from EEPROMAngel Pons
Cache the board settings in memory to avoid having to read them from the EEPROM multiple times. For now, configure the following settings: - DeepSx - USB power in S5 - Power state after G3 Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04mb/prodrive/hermes: Define board settings in EEPROMAngel Pons
Hermes has an EEPROM with firmware configuration data. Add definitions to read and verify the `board settings` from the EEPROM. Subsequent commits will hook up these EEPROM settings. Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04mb/google/kukui: kakadu: update the initial code for BOE LCDSunway
The latest initial code is from BOE, the vendor. BUG=b:179206650 BRANCH=kukui TEST=Run long time aging test and the BOE LCD shows normally. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04soc/amd/picasso: Fix copy-paste error in macro definitionsAngel Pons
The `_MASK` macros should be using the corresponding `_SHIFT` macros. Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674 Found-by: Coverity CID 1445928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-04mb/clevo/cml-u/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I048e906306bf77a941b5f731ade15292fa944390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04mb/amd/majolica: add fmd for use when building chromeosMathew King
BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0John Zhao
A minimum of 100ms delay is required before sending a configuration request to the downstream components. Since the kernel already adds 100ms, this change drops the extra 100ms delay in TBT PCIe root ports _PS0 method in order to improve resume time. BUG=b:177519081 TEST=Boot to kernel and validated various tests on Voxel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mb/emulation/qemu: Fix SMP bootPatrick Rudolph
Fix booting with SMP enabled, when specifying more CPUs than supported by the code. Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04src: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-04src: Remove unused <cbfs.h>Elyes HAOUAS
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h>Elyes HAOUAS
Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50196 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04soc/mediatek/mt8192/spm.c: Add missing <string.h>Elyes HAOUAS
Change-Id: I56a4e0fb42c881026f4ee1abe30f9b356af6a68f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50168 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04coreboot_table: Move VBOOT_VBNV supportKyösti Mälkki
The guard changes from (CHROMEOS && PC80_SYSTEM) to VBOOT_VBNV_CMOS here. Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-04vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.hSubrata Banik
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. BUG=b:178846328 Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mb/google: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: Ica8691e3dc4feecbeb11ba3f5868932f926965b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48785 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-04vc/google/chromeos: Drop <acpi/vpd.asl>Kyösti Mälkki
This was used as a means to read the MAC address and dynamically return it to the ethernet driver via ACPI. The kernel team ended up going another direction so this became obsolete. Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04coreboot_table: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48786 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04coreboot_table: Drop <vboot/misc.h> includeKyösti Mälkki
Could have been removed with commit 63b9700b2c already. Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50249 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04vc/../chromeos.asl: Drop CHROMEOS guardKyösti Mälkki
coreboot proper now has a single include for this file with the guard around it already. Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-04vendorcode/amd/fsp/cezanne: add UPD structs from FSP buildFelix Held
There will be incompatible changes during the further development of the coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct size to match the one in the FSP header. See CB:50241 for details. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242 Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registersFelix Held
Picasso has 32 configurable GPEs, not only 28. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04amd/common/block/acpi/pm_state: fix comparison in get_index_bitFelix Held
In the case of passing 32 as limit the code returned -1, but should have continued, since 32 is a valid value here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-03mb/google/volteer/variants/drobit: Configure USB2 port for Type-CHEADmasterWayne3_Wang
USB2 ports assigned to type-C connector need to be configured properly by the USB2_PORT_TYPE_C. and also modify the description of USB port. BUG=b:177480902 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the typeC port function is normal by manual. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang
According to Tigerlake TDP specifications (doc #575683, table 4-2), TGL supports different TDP levels depends on CPU segement/package, IA Cores and graphics configuration. For example, UP3 4-Core GT2 suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable TDP-Down_2=12W. This configurable value can be used to select suitable TDP level Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-03mb/google/volteer/var/voema: Enable EEPROM for OV2740David Wu
Add ACPI entries for AT24 NVM device. BUG=b:169551066 TEST=Build and run for basic camera functions. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jim Lai <jim.lai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03soc/amd: rename sb_init_acpi_ports to fch_init_acpi_portsFelix Held
There's no dedicated south bridge any more and now we have integrated FCHs in the SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03soc/amd/cezanne: remove UART2/3 AOAC device offsetsFelix Held
UART2 and UART3 don't exist on Cezanne which now has been verified, so remove the corresponding AOAC offsets. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-03soc/amd/picasso: clean up and re-sort UPD tableChris Wang
Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree. remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-03mb/google/volteer/variant/copano: support regular/numpad touchpadZhuohao Lee
Define the 25th bit of the fw_config for the regular touchpad and numpad touchpad selection. BUG=b:174027837 BRANCH=firmware-volteer-13672.B TEST=build pass Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037Subrata Banik
List of changes: 1. FSP-M Header: - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)Zheng Bao
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-03ec/hp/kbc1126: Wait a longer time after sendingPablo Stebler
This fixes the fan always running at full speed on ProBook 6360b, EliteBook 8470p and ProBook 640 G1 (because the fan control command was not sent). On the ProBook 6360b, the EC needs about 30 ms to process the first command on a cold boot, but other models such as the ProBook 640 G1 need more time. Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb Signed-off-by: Pablo Stebler <pablo@stebler.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-03pci_ids/intel: Add missing CFL-S GT1 IGD IDsNico Huber
Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
2021-02-03pci_ids/intel: Correct 0x3e96, it's a CFL-S partNico Huber
Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-03src: Remove unused <boardid.h>Elyes HAOUAS
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-03src: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-03soc/ti/am335x/header.c: Add missing includeElyes HAOUAS
Use of 'offsetof' needs <commonlib/bsd/helpers.h>. Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44738 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/google/volteer/variants/drobit: Modify touchpad I2C sequenceWayne3_Wang
Modify touchpad I2C sequence to meet requirement. BUG=b:178512111 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the touchpad I2C5 sequence by EE. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobitWayne3_Wang
Add the TBT PCIE rp setting to on and also fixes system hang in recovery screen after selected "Power off" item problem. BUG=b:177963941 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the system can power off normally in recovery page Cq-Depend: chrome-internal:3581043 Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selectedJohnny Lin
Because ACM already does TPM initialization. Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-03hatch: Update fan and thermal settings for ambassadorNeill Corlett
Update fan and thermal settings for ambassador, per recommendations from Quanta. BUG=b:177765580 TEST=Built AP firmware Change-Id: I080859f872caf696f0c085defb8372de658da58a Signed-off-by: Neill Corlett <corlett@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50100 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joe Tessler <jrt@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/biostar/th61-itx/early_init.c: Clean includesElyes HAOUAS
Change-Id: I0619e567527812bd0e7088d23d91f114c8fec9ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-03drivers/aspeed: Fix some issuesPatrick Rudolph
* Use probe_resource instead of find_resource. This prevents a call to die and instead returns NULL. * Handle the case where BAR2 isn't present * Don't hardcode legacy VGA when BAR2 is present. This fixes graphic initialisation when the Aspeed isn't the primary GPU and thus doesn't decode VGA cycles. This makes the coreboot code more similar to the Linux kernel code. Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/google/sarien: Turn `hda_verb.h` into `hda_verb.c`Angel Pons
Change-Id: I40c8145fdddf9605bc3cc66ae8075e52dca4e539 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03soc/intel: Fix compilation on x86_64Patrick Rudolph
Change-Id: I18a0c18fe1c64611f95bc423916447c89585db9f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-02soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI codeFelix Held
commit 3f2467032e3e40cd456d2d9fe5120a60283784aa changed this in the APCI code itself, but the change in the ACPI byte code generation in pcie_gpp.c was missed and this patch fixes that. TEST=Fixes the regression on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60de29581296101947336f70343d6206af97e307 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-02soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE definesFelix Held
This define was copied over from Stoneyridge, but isn't present on Picasso and newer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-02tests: Add lib/region_file-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic48e52a97b18d55fd983315f25dc972f472cc473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-02mb/siemens/mc_apl1: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02soc/intel/baytrail,braswell: Drop TOLM from GNVSKyösti Mälkki
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-02soc/intel/baytrail,braswell: Sync PCI memory region in ASLKyösti Mälkki
Baytrail had (only) occurence of DwordMemory vs DWordMemory. Braswell one had bogus comments about the PCI memory range. The actual region details are dynamically filled in _CRS. Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 21:52:25 +0000