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2016-07-22soc/intel/apollolake: add dual rank option to meminitAaron Durbin
Despite the UPD comments the Chx_RankEnable fields are a bit mask which indicates which ranks are enabled for physical channel. Add the ability to set the rank mask correctly for dual rank LPDDR4 modules. BUG=chrome-os-partner:55446 Change-Id: I9dbed7bb6a4b512e57f6b4481180932a7cce91ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15771 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22soc/intel/apollolake: die() when FSP silicon init failsAaron Durbin
The reset requests are handled in the FSP 2.0 wrapper, but the current code doesn't check any non-successful return values. Provide parity with the memory init path which die()s under those circumstances. Change-Id: I9df61323f742b4e94294321e3ca3ab58a68ca4dd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15766 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22intel car: Unify postcodesKyösti Mälkki
Not all are matched, but this makes it easier to backport MTRR changes from haswell. Change-Id: Ida5943b1469fc0089a31ff3b18131fb82b0941c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15759 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22intel car: Remove guard on XIP_ROM_SIZEKyösti Mälkki
These guards have been removed starting with model_206ax. Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15758 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-22intel model_106cx: Include CAR from socket directoryKyösti Mälkki
Since the socket layer is implemented with this CPU model, there could potentially be multiple CPU models included. There can be only one cache_as_ram include, so select it directly within the socket directory. Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15757 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-21mainboard/google/reef: handle eMMC power signal polarity changeAaron Durbin
The EVT board uses an active high power control signal while the previous board used an active low signal. Update the tables to reflect the differences. BUG=chrome-os-partner:55470 Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21mainboard/google/reef: reverse the memory config bitsAaron Durbin
I mistakenly assumed the order of the bits matched how one would assign values as they wrote them msb .. lsb. However, the gpio lib doesn't do that. Correct the order so that values are read out correctly. BUG=chrome-os-partner:54949t Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15753 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21timestamp: Drop duplicate TS_END_ROMSTAGE entriesKyösti Mälkki
This entry gets added in run_ramstage(). Change-Id: I18cda4ead3614c6d07c3269cbee53e6def6408c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15755 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21AMD k8 fam10: Fix CAR GLOBALS late in romstageKyösti Mälkki
Zero-filling memory below 1 MiB resets car_migrated variable so any CAR GLOBALs are not addressed correctly for the remaining time in romstage. Also there is no actual need to do this as ramstage loader handles BSS. This fixes regression with commit 70cd54310 that broke fam10 boards with romstage spinlocks enabled. Change-Id: I7418821997a980ae5b818bd57e8a1b6507a543af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15754 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-07-21buildgcc: Never set GMP CFLAGS manually in order to get the right flagsPaul Kocialkowski
When no CFLAGS are explicitly provided to it, the GMP configure script will figure out the best optimization flags to use on its own. In particular, it will setup the march, mfpu and mtune flags based on hardware detection. However, when CFLAGS are provided, they are used as-is and such detection doesn't happen. When the march, mfpu and mtune flags are not provided (which happens when GMP wasn't built already), not only will related optimizations be disabled, but some code might not build because of missing support. This happens with NEON instructions on ARMv7 hosts. Thus, it is better not to set CFLAGS and leave it up to the GMP configure script to get them right and still reuse those later. Change-Id: I6ffcbac1298523d1b8ddf29a8bca1b00298828a7 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15452 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-21soc/intel/apollolake: Add new Intel HD Graphics Device ID's.Abhay Kumar
B stepping onwards we have to support two Graphics Device ID. BUG=chrome-os-partner:55449 Change-Id: I520791ad8573dc5deb6ea1e33e1486f05050438c Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15767 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-20coreinfo: Add support to read timestampsAntonello Dettori
Read timestamps from the last boot sequence and display the information as if using cbmem -t. Tested on QEMU with a SeaBIOS payload. Change-Id: I44f1f6d6e4ef5458aca555c8a7d32cc8aae46502 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15600 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20cbmem: share additional time stamps IDsAntonello Dettori
Split the additional time stamps concerning depthcharge from the cbmem utility sourcecode and move them into commonlib/timestamp_serialized.h header. Change-Id: Ic23c3bc12eac246336b2ba7c7c39eb2673897d5a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15725 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20google/reef: Add wake signal for trackpadFurquan Shaikh
EVT has a wake signal for track pad which is routed to GP_15. BUG=chrome-os-partner:54960 Change-Id: I9a73a3dc74e3bbed63509a3c076ec17a6559da55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15723 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-20tpm2_tlcl: Use signed integer for tpm2_marshal_command return valueDuncan Laurie
The tpm2_marshal_command() function returns a negative value on error, so we must use a signed type for the return value. This was found by the coverity scan: https://scan.coverity.com/projects/coreboot?tab=overview CID:1357675 CID:1357676 Change-Id: I56d2ce7d52b9b70e43378c13c66b55ac2948f218 Signed-off-by: Duncan Laurie <dlaurie@google.com> Found-by: Coverity Scan Reviewed-on: https://review.coreboot.org/15717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-07-20soc/intel/quark: Fix legacy GPIO readsLee Leahy
Add missing break to LEG_GPIO_REGS case to return the correct value for legacy GPIO reads. Fixes coverity issue CID 1357460. Found by Coverity, Fixes: * CID 1357460 (#1 of 1): Unused value (UNUSED_VALUE) returned_value: Assigning value from reg_legacy_gpio_read(step->reg) to value here, but that stored value is overwritten before it can be used. value_overwrite: Overwriting previous write to value with value from reg_pcie_afe_read(step->reg). TEST=Build and run on Galileo Gen2. Change-Id: I6c52e8801a32f510ac94276fe0c097850cbfde57 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15732 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20amd/db-ft3b-lc: Add board supportKyösti Mälkki
Change-Id: Ibab9039306730bfd3063b34cf085e854e4608902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-20amd/db-ft3b-lc: Copy of amd/olivehillplusKyösti Mälkki
Change-Id: I70330278bae54392e236d762716ba7c4d39a05a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14969 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-19rockchip/rk3399: Remove unused variableMartin Roth
The 'speed' variable isn't being used after refactoring. Change-Id: Id27a920c61b2bba18d391a7bfefe570235402dec Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15749 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19intel/amenia: Add DA7219 support in acpiHarsha Priya
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45021 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19drivers/intel/fsp2_0: Split reset handling logicAndrey Petrov
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The rest 6 codes are platform-specific and may vary. Modify helper function so that only basic resets are handled and let SoC deal with the rest. Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15590 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19soc/intel/apollolake: Implement reset_prepare()Andrey Petrov
At first boot CSE spends long time preparing media for use. As result it may not be able to deal with a CPU reset. Add reset_prepare() callback that polls CSE readiness. BUG=chrome-os-partner:55055 TEST=build with release version of fsp, reboot, observe polling for CSE, then proper reboot happening Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/common: Add reset_prepare() for common resetAndrey Petrov
Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/apollolake: Add basic HECI supportAndrey Petrov
Add functions to read Host Firmware Status register and a helper function to determine if CSE is ready. BUG=chrome-os-partner:55055 TEST=none Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15713 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPSAaron Durbin
The FSPS component can request resets. Handle those generically. BUG=chrome-os-partner:52679 Change-Id: I41c2da543420102d864e3c5e039fed13632225b4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15748 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPMAaron Durbin
The FSPM component can request resets. Properly handle those. BUG=chrome-os-partner:52679 Change-Id: If21245443761cb993e86c0e383c8bca87f460a85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15747 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: range check stack provided to FSPMAaron Durbin
Ensure that the stack provided to FSPM doesn't overlap the current program which is loading the FSPM component. If there is a conflict that's an error since it could cause the current program to crash. BUG=chrome-os-partner:52679 Change-Id: Ifff465266e5bb3cb3cf9b616d322a46199f802c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15746 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: don't use saved memory data in recovery modeAaron Durbin
If the system is in recovery mode force a full retrain. BUG=chrome-os-partner:52679 Change-Id: I4e87685600880d815fe3198b820a10aa269baf37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15745 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: honor FSP revision for memory training dataAaron Durbin
Utilizing the FSP revision while saving the memory training data is important because it means when the FSP is updated the memory training is redone. The previous implementation was just using '0' as a revision. Because of that behavior a retrain would not have been done on an FSP upgrade. BUG=chrome-os-partner:52679 Change-Id: I1430bd78c770a840d2deff2476f47150c02cf27d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15744 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19drivers/intel/fsp2_0: remove unused fsp_load_binary()Aaron Durbin
Remove the now unused fsp_load_binary() function. BUG=chrome-os-partner:52679 Change-Id: I5667eb71689a69a9e05f7be05cb0c7e7795a55d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15743 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: load and relocate FSPS in cbmemAaron Durbin
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM componentAaron Durbin
The previously implementation for loading the FSPM component didn't handle platforms which expects FSPM to be XIP. For the non-XIP case, romstage's address space wasn't fully being checked for overlaps. Lastly, fixup the API as the range_entry isn't needed any longer. This API change requires a apollolake to be updated as well. BUG=chrome-os-partner:52679 Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: separate component validation from loadingAaron Durbin
The current FSP component loading mechanism doesn't handle all the requirements actually needed. Two things need to be added: 1. XIP support for MemoryInit component 2. Relocating SiliconInit component to not corrupt OS memory. In order to accommodate those requirements the validation and header initialization needs to be a separate function. Therefore, provide fsp_validate_component() to help achieve those requirements. BUG=chrome-os-partner:52679 Change-Id: I53525498b250033f3187c05db248e07b00cc934d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15740 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: implement common memory_init() tasksAaron Durbin
Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: set BootLoaderTolumSize genericallyAaron Durbin
The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: fix hand-off-block types and sizeAaron Durbin
The gcc compiler treats sizeof(void) == 1. Therefore requesting a 1 byte reservation in cbmem and writing a pointer into the buffer returned is wrong. Fix the size of the request to be 32-bits because FSP 2.0 is in 32-bit space by definition. Also, since the access to the field happens across stage boundaries it's important to ensure fixed widths are used in case a later stage has a different pointer bit width. BUG=chrome-os-partner:52679 Change-Id: Ib4efc7d5369d44a995318aac6c4a7cfdc73e4a8c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15737 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19soc/intel/apollolake: remove unused FIT_POINTER defineAaron Durbin
Change-Id: I97be4f8cecbf9cf2adda2e0c1650e03acd7eb1cb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15736 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19commonlib: fix 'AFTER CAR' spacing to align with othersAaron Durbin
The cbmem string for 'AFTER CAR' didn't have the proper spacing so when that entry is added to cbmem it results in a misaligned log entry with the others. Change-Id: If940e85b7dc5fb8372d7e2845270dadad67ab3a0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15735 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19lib: provide memrange library in romstageAaron Durbin
BUG=chrome-os-partner:52679 Change-Id: I79ffc0749fba353cd959df727fb45ca2ee5c1bf6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15734 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19mainboard/google/reef: explicitly set shipping Chrome OS optionsAaron Durbin
The Chrome OS options that will be shipped on this platform were being set in the chromium repo with an external config file. Set the options in the mainboard Kconfig file so there's no discrepancy as to what will be used. Change-Id: I05f0d1245611c16f54273728519a08e6edff3429 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19soc/intel/apollolake: Fix bitshift issue in bootblockAndrey Petrov
Fix issue where zero-sized BIOS region could cause bitshift for '-1' which is an unspecified behavior. Change-Id: Icb62bf413a1a0d293657503ef21fe97b5f9a5484 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15727 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19nb/intel/x4x: Fix CAS latency detectionDamien Zammit
Fix and use the failsafe CAS detection logic rather than recalulating the values from raw SPDs. Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs (which worked before and still work) Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
This function is unused since coreboot starts payloads in machine mode, and it uses the obsolete eret instruction. Change-Id: I98d7d0de5a3959821c21a0ba4319efb610fdefde Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
Using the opcode directly is necessary for the transition to the GCC 6.1.0 based toolchain, because the old toolchain only supports eret and the new toolchain only supports mret. Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18google/oak & elm: initialize touchscreen reset gpioYH Huang
In order to save power in S3, we remove reset gpio setting in kernel. We still need to initialize touchscreen ic. Do it by pulling low reset gpio for 500us and then pulling high in firmware. BRANCH=none BUG=chrome-os-partner:55170 TEST=build on elm. Change-Id: Idbe0175a1fc1fa0b05e81706194c79d52c6101f6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f40cc9a22c2551c2c9455cb8b60f36353602bca6 Original-Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/360312 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw> Reviewed-on: https://review.coreboot.org/15719 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-18gru: implement hw reset functionVadim Bendebury
Asserting this GPIO will send a signal to the EC to trigger a reset for the AP and the CR50. BRANCH=none BUG=chrome-os-partner:55252 TEST=the device now reboots when it needs to switch between different boot modes instead of hanging with "failed to reboot" message. Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7 Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/360238 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15718 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-18elog: Use rdev_mmap to find offset of ELOGFurquan Shaikh
In case of elog not being stored in CBMEM, calculate flash offset by using rdev_mmap instead of assuming that the entire flash is mapped just below 4GiB. This allows custom mappings of flash to correctly convert the flash offset to mmap address. BUG=chrome-os-partner:54186 TEST=Verified behavior on reef. mosys able to read out the elog correctly. Change-Id: I3eacd2c9266ecc3da1bd45c86ff9d0e8153ca3f2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15722 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-17mainboard/amd: add support for F2950 system boardAndrey Korolyov
F2950 SBC, also known as TONK 1201/TONK 1202, was originally produced as a Centerm F2950 using DB800 reference design. Common configuration does include a 600 MHz GeodeLX CPU underclocked to 500 or 400 MHz, 128 or 512 MiB of RAM in the single SODIMM slot and 128 or 512 MB IDE DOM. The board does have three USB 2.0 ports (none of them possessing debug capabilities), PS/2, VGA, Geode audio in/out and the serial port. EEPROM needs to be soldered out and flashed externally at the time of this message because flashrom would neither be able to dump BIOS correctly while running vendor BIOS nor write flash contents. All peripherals were tested against Linux 3.16 and seem to work flawlessly. At the moment of this commit coreboot does not pass PCI_COMMAND_IO from the configuration space to SeaBIOS, thereby preventing VGA OPROM from being executed. This would be fixed in the SeaBIOS itself or in a subsequent commit. As a workaround, user may put VGA OPROM to vgaroms/seavgabios.bin in CBFS. Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4 Reviewed-on: https://review.coreboot.org/15565 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
The API called to write the name of the child table in the dp entry (type ACPI_DP_TYPE_CHILD) was not including the quotes, e.g., it was DAAD and not "DAAD". Thus, the kernel driver did not get the right information from SSDT. Change the API to acpigen_write_string() to fix the issue. Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8984e7 Reviewed-on: https://review.coreboot.org/15724 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-16buildgcc: Update the revision to 1.41Martin Roth
The binutils patch went in without updating the revision, so we need to update it now. This was done in commit bcfa7ccb (buildgcc: Update to binutils-2.26.1 & Fix aarch64 build issue) Change-Id: Ifad4a2e3973f1f60d0ea840945e2bd097e1b4474 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15712 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15intel/amenia: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Platform wakes up from S3 on lidopen. Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15618 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/apollolake: Properly disable PCIe root portsKane Chen
1. The hotplug feature needs to be disabled so that pcie root ports will be disabled by fsp 2. Correct PcieRootPortEn mapping. The correct mapping should be like below PcieRootPortEn[0] ==> 00:14.0 PcieRootPortEn[1] ==> 00:14.1 PcieRootPortEn[2] ==> 00:13.0 PcieRootPortEn[3] ==> 00:13.1 PcieRootPortEn[4] ==> 00:13.2 PcieRootPortEn[5] ==> 00:13.3 BUG=chrome-os-partner:54288 BRANCH=None TEST=Checked pcie root port is disabled properly and make sure pcie ports are coalesced. Also make sure the device will still be enabled after coalescence when pcie on function 0 is disabled devicetree Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/15595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15google/reef: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Reef board wakes up from S3 on lidopen. Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15intel/x4x: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15intel/pineview: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15715 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15AMD binaryPI: Use common romstage ram stackKyösti Mälkki
Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: I52d0bd7dac86822242400f68f6dc202f02d6e0f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AMD binaryPI: Split romstage ram stackKyösti Mälkki
Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AMD binaryPI: Use common ACPI S3 recoveryKyösti Mälkki
Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15254 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AGESA: Use common romstage ram stackKyösti Mälkki
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AGESA: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15253 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15mainboards/skylake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15689 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15soc/intel/skylake: provide poweroff() implementationAaron Durbin
Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15688 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15mainboards/apollolake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15687 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15soc/intel/apollolake: provide poweroff() implementationAaron Durbin
Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15686 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15ec/google/chromeec: provide common SMI handler helpersAaron Durbin
The mainboards which use the Chrome EC duplicate the same logic in the mainboard smi handler. Provide common helper functions for those boards to utilize. BUG=chrome-os-partner:54977 Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15685 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15lib: add poweroff() declarationAaron Durbin
Add a function to power off the system within the halt.h header. BUG=chrome-os-partner:54977 Change-Id: I21ca9de38d4ca67c77272031cc20f3f1d015f8fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15684 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15soc/intel/quark: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I884da90d24bc41e566a290f4135166d9e0cdf474 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15682 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/fsp_i89xx: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ibf2bc3ae89cb5a013cb1ccc439c906b00bf78d66 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ia113672fa3cb740cb193c23fd06181d9ce895ac3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/i82801gx: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I08fb52ca13a4355d95fe31516c43de18d40de140 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/i82801dx: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I29918fe70b5e511785ed920d8953de3281694be2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/ibexpeak: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I65270ddcb612f9c63d7dbb2409e4395f96e10a51 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15677 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/lynxpoint: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15676 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/bd82x6x: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ie709e5d232c474b41f2ea73d3785a7975d6604ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/fsp_baytrail: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/broadwell: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15672 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-07-15soc/intel/skylake: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15671 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15soc/intel/braswell: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15670 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15soc/intel/baytrail: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15669 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/common: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15668 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/apollolake: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15667 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
In the ACPI specification the PM1 register locations are well defined, but the sleep type values are hardware specific. That said, the Intel chipsets have been consistent with the values they use. Therefore, provide those hardware definitions as well a helper function for translating the hardware values to the more high level ACPI sleep values. BUG=chrome-os-partner:54977 Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15drivers/intel/fsp1_1: align on using ACPI_Sx definitionsAaron Durbin
The SLEEP_STATE_x definitions in the chipsets utilizing FSP 1.1. driver have the exact same values as the ACPI_Sx definitions. The chipsets will be moved over subsequently, but updating this first allows the per-chipset patches to be isolated. BUG=chrome-os-partner:54977 Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15665 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15mainboards: remove direct acpi_slp_type usageAaron Durbin
Use the acpi_is_wakeup_s3() API instead of comparing a raw value to a global variable. This allows for easier refactoring. Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15690 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
Instead of open coding the literal values provide more semantic symbol to be used. This will allow for aligning chipset code with this as well to reduce duplication. BUG=chrome-os-partner:54977 Change-Id: I022bf1eb258f7244f2e5aa2fb72b7b82e1900a5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15663 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-15soc/intel/skylake: don't duplicate setting ACPI sleep stateAaron Durbin
The ramstage main() in lib/hardwaremain.c has the logic to set the ACPI sleep state based on romstage_handoff. Thus, there's no need to do it a second time. Change-Id: I75172083587c8d4457c1466edb88d400f7ef2dd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15662 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/braswell: don't duplicate setting ACPI sleep stateAaron Durbin
The ramstage main() in lib/hardwaremain.c has the logic to set the ACPI sleep state based on romstage_handoff. Thus, there's no need to do it a second time. Change-Id: I88af301024fd6f868f494a737d2cce14d85f8241 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15661 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15arch/riscv: Move CBMEM into RAMJonathan Neuschäfer
CBMEM should be placed at the top of RAM, which can be found by parsing the configuration string. Configuration string parsing isn't yet implemented, so I'll hard-code the CBMEM location for now. Change-Id: If4092d094a856f6783887c062d6682dd13a73b8f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15284 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-15chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sectionsPaul Kocialkowski
This fills up the RO_FRID, RW_FWID_A and RW_FWID_B FMAP sections with the relevant version from KERNELVERSION, padded to the right size and gap-filled with zeros. Change-Id: I45c724555f8e41be02b92ef2990bf6710be805c2 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15rockchip/rk3399: extend romstage rangeLin Huang
rk3399 sdram size is 192K, and there still some unused space. We need more romstage space to include the sdram config, so extend the romstage range. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: Ib827345fe646e985773e6ce3e98ac3f64317fffb Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 626ab15bb4ebb004d5294b948bbdecc77a72a484 Original-Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/359092 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15660 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: set kevin rev3 pwm regulator initial value to 0.95vLin Huang
kevin rev3 pwm regulator ripple is still not great, especially for center logic. To make sdram at 800MHz stable, raise it to 0.95v. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If4a15eb7398eea8214cb58422bca7cfb5f4a051a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d29bc581effb0008eb196685aa22dd65b5d478a5 Original-Change-Id: Ideec9c3ab2f919af732719ed2f6a702068d99c8f Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/359130 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15659 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15Google Mainboards: Increase RO coreboot size on flashDaisuke Nojiri
Bitmap images will be moved to CBFS from GBB. This patch adjusts the flash map accordingly for rambi, samus, peppy, parrot, falco, panther, auron, and strago. BUG=chromium:622501 BRANCH=tot TEST=emerge-{samus,falco} chromeos-bootimage CQ-DEPEND=CL:354710,CL:355100 Change-Id: I6b59d0fd4cc7929f0de5317650faf17c269c4178 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 201a82311ba539b9b02d546ba331ff5bf73e0edf Original-Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355040 Reviewed-on: https://review.coreboot.org/15658 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: Remove empty function in sdram.cDerek Basehore
This removes an empty function for sdram training. If it's needed later, we can always add it back. BRANCH=none BUG=none TEST=build and boot firmware for kevin/gru Change-Id: Id526ef86cf5044894a1a736cc39f10d32f49c072 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3e93461b96bfadc08bf0b46cf99052d9cdffa422 Original-Change-Id: I6bf77d2f81719c68cd78722c3fe9ae547ea1e79c Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354164 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15657 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: Change copy_to_reg arg typeDerek Basehore
This changes the src arg for copy_to_reg to a const u32 * instead of a u32 * in sdram.c. BRANCH=none BUG=none TEST=emerge-gru coreboot Change-Id: I80f49258b2f8102f0d988fec85b8038a00e18a34 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e0342e5c0181bf65ae78aa9518b0d6bd6cb1d5ec Original-Change-Id: I362727f1dbe6726bf3240f9219c394786162a1a0 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354163 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15656 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 13:24:28 +0000