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2016-06-26intel/i945: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I6f0cdc80870fddeaada3191e493bd85fdefee07f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-26ifwitool: Fix gcc error due to shadowed global declarationWerner Zeh
The name 'bpdt_size' is used for a function as well as ia local variable. As ifwitool is compiled using HOSTCC, there can be an older gcc version used for the compilation. With gcc version 4.4.7 I get the following error: declaration of 'bpdt_size' shadows a global declaration To fix it, rename the function to get_bpdt_size so that names are unique now. Change-Id: I47791c705ac4ab28307c52b86940a7a14a5cfef8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15343 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24rockchip/rk3399: provide multiple SDRAM configurationsLin Huang
We want to be able to easily change SDRAM clock rate for debugging purposes. This patch adds configurations for 4 different clock rates. Same configs are used for all rk3399 boards at 200, 666 and 800 MHz. Kevin board does not run reliably at 666 MHz, an option for it is added to run at 300 MHz, this option is available to Kevin only. There is not much room left in the coreboot romstage section, this is why the config file for 928 MHz is being added with this patch but is not included in the code, one of the lower frequency options will have to be dropped for the higher frequency option to be added. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and gru. Verified that on Kevin the firmware reports starting up SDRAM at 300 MHz and on Gru at 800 MHz. Change-Id: Ie24c1813d5a0e9f0f9bfc781cade9e28fb6eb2f1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ef5e4551b79c3f0531f9af35491f2c593f8482f1 Original-Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353493 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15309 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24rk3399: clean up sdram controller initialization codeVadim Bendebury
This is a purely cosmetic change replacing some of the more prominent copy and paste sections of the code with compressed versions of the same. BRANCH=none BUG=none TEST=with the rest of the patches applied stressapptest still runs for an hour on both Kevin and Gru. Change-Id: I492e1898e312473d07d9e5eceb3e3e10b48ee35f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb8043f96457d090dbbee57097bc1d685e7d32d2 Original-Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353774 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15308 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add elog supportSimon Glass
Add code to start up elog. This uses the EC RTC to obtain the timestamp. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages Change-Id: I4971d661b267ae8b7e3befeff482ca703b741743 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e4e9823d8cecbf9873e78b048e389c7a737ff512 Original-Change-Id: I0fcf55b3feccf9a0ad915deb6d323b65bf2e9811 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353822 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15306 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add get_developer_mode_switch()Simon Glass
Add this function and make it return 0, as there is no physical dev switch (at least I think this is what we are supposed to do). This is needed for elog to work, which is needed so we can test RTC properly. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages: elog_init() SF: Detected W25Q64 with sector size 0x1000, total 0x800000 elog_find_flash() FMAP: area RW_ELOG found @ 5d8000 (32768 bytes) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) ELOG: flash area invalid elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096) SF: Successfully erased 4096 bytes @ 0x5d8000 elog_prepare_empty() elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) elog_is_header_valid() elog_update_event_buffer_state() elog_is_buffer_clear(base=0x000000000031d670 size=4088) elog_is_area_valid() ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000] ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024 elog_add_event_raw(type=16) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11) ELOG: Event(16) added with size 11 elog_add_event_raw(type=17) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13) ELOG: Event(17) added with size 13 elog_add_event_raw(type=A0) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9) ELOG: Event(A0) added with size 9 elog_add_boot_reason: Logged dev mode boot I can't actually see the timestamp, but the EC traffic is visible. Change-Id: I82bcf296dce4f4d146edf90b23bfae955fbe9e3a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ffc7a7e0e7b136144d2a0b2ed21a543eafee49fa Original-Change-Id: I1489c6b874cc49495635aec0bf303f7098455716 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353821 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15305 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Show the current time on start-upSimon Glass
Display the current time from the EC. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I4288efc56f00e47f7575d0379a44871351da6200 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d0361193e0ec135e21f0611d7fa6e5c02f2b2bfc Original-Change-Id: I04a072c788ba3fc915e6d73703f966955bbd3e7e Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351783 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Enable EC-based RTCSimon Glass
Obtain the real-time clock value from the EC on start-up and show the current time. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and EC clock set, boot on gru into Linux shell and check the firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:09:16 Change-Id: Id3ef791f546419c4881a891251cbb62d7596884b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 348e9373b0e95a17f5c39ec28a480712e6e45caf Original-Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351781 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15303 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24soc/apollolake: Clear SLP_TYP in PM1_CNTHannah Williams
Change-Id: Id49319ec6b52648b03eaeddfdd1580dd82110fb9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Add handling of global reset in FspNotify stageAndrey Petrov
Call basic FSP reset handling in FspNotify stage. Handling of reset requests for other stages need to be implemented as well. BUG=chrome-os-partner:54149 BRANCH=none TEST=with FSP that returns reset codes, do cold boot, check that reboot sequence occurs properly. Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24drivers/intel/fsp2_0: Add simple reset handlerAndrey Petrov
Any FSP API call may request a reset. This is indicated in API function return code. Add trivial reset handler code. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: Ieb5e2d52ffdaf3c3ed416603f6dbb4f9c25a1a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Implement global reset handlingAndrey Petrov
Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Move PMC BAR setup to bootblockAndrey Petrov
Some features of PMC needs to be accessed before romstage. Hence, move PMC BARs setup into bootblock. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15332 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Add utility functions for global resetAndrey Petrov
Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/common: Add prototype for global_reset() resetAndrey Petrov
Add prototype for global_reset() that some SoCs need to provide. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I8afe076b6f4f675b3c6a3ec0e4dd69f950baa4ef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15333 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24Revert "intel/apollolake: Use custom reset calls"Andrey Petrov
Looks like we need to do real cold reset in some FSP flows, so reverting this. This reverts commit 6f762171de4b8514fddd430052cbf24524e09e5d. Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15331 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24ec/google: Add support for the EC 'get time' functionSimon Glass
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to implement rtc_get() so that this can be plumbed in. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits, boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I3b38f23b259837cdd4bd99167961b7bd245683b3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4a4a26da37323c9ac33030c8f1510efae5ac2505 Original-Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351780 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24lib: Add real-time-clock functionsSimon Glass
Add functions to convert between seconds and a struct rtc_time. Also add a function that can display the time on the console. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and after setting RTC on the EC: boot on gru into linux shell, check firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:01:44 Then reboot ~10 seconds and check again: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:01:54 Change-Id: Id148ccb7a18a05865b903307358666ff6c7b4a3d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b02dbcd7d9023ce0acabebcf904e70007428d27 Original-Change-Id: I344c385e2e4cb995d3a374025c205f01c38b660d Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351782 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24intel/kunimitsu: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tesed on a Chell mainboard since I lack a kunitmisu device. I used different GPIOs across boots to verify that the different audio codec devices would be "detected" and generated in the SSDT. Change-Id: I9b3b2247a84aeb7c07780958377d5bea14417ce6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15317 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/lars: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tested on a Chell mainboard since I lack a lars device. Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15316 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/glados: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified on a glados board by verifying the SSDT contents against what used to be in the DSDT. Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/chell: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified by comparing the generated ACPI code in the SSDT to what was in mainboard.asl and ensuring the contents are functionally equivalent. Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24soc/intel/apollolake: Include _PTS, _WAK and _SWSHannah Williams
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-24src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copyBenjamin Barenblat
Rewrite inline assembly for ARMv7+ to correctly annotate inputs and outputs. On ARM GCC 6.1.1, this causes assembly output to change from the incorrect @ r0 is allocated to hold dst and x0 @ r1 is allocated to hold src and x1 ldr r0, [r1] @ clobbers dst! ldr r1, [r1, #4] str r0, [r0] str r1, [r0, #4] to the correct @ r0 is allocated to hold dst @ r1 is allocated to hold src and x1 @ r3 is allocated to hold x0 ldr r3, [r1] ldr r1, [r1, #4] str r3, [r0] str r1, [r0, #4] Also modify checkpatch.pl to ignore spaces before opening brackets when used in inline assembly. Change-Id: I255995f5e0a7b1a95375258755a93972c51d79b8 Signed-off-by: Benjamin Barenblat <bbaren@google.com> Reviewed-on: https://review.coreboot.org/15216 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24arch/x86/smbios: Correct manufacturer IDElyes HAOUAS
Correct standard manufacturer's identification code. Change-Id: I273711e121a61a91176c15cd4cab75420f1f5a39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15271 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-24SPD: Add DRAM devices typesElyes HAOUAS
Add SDRAM or module types to byte 2. Change-Id: Id6e654a3a714c164bc9a7fbd9ab3e2f3c44ca5ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15265 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24SPD: fix DDR3 SDRAM memory module typesElyes HAOUAS
Correct the definitions for 16b and 32b SO-DIMM modules. Regarding JEDEC Standard No. 21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules (2014), the hex values used for 16b-SO-DIMM is 0x0c and for 32b-SO-DIMM module type is 0x0d Change-Id: I9210ac3409a4aaf55a0f6411d5960cfdca05068d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15262 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24SPD: fix and add DDR2 SDRAM memory module typesElyes HAOUAS
Correct the definitions and add 72b-SO-CDIMM and 72b-SO-RDIMM Change-Id: I33532e30f45f6c8c0eb6d47b0bea87689d2d9a1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15204 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24spd: Add module voltage for 1.8VElyes HAOUAS
Add SSTL 1.8 V Interface Level as specified in JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10. Change-Id: I0112a85f557826b629109e212dbbc752aeda305d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-23intel/apollolake: Enable prefetching and caching for BIOS readsFurquan Shaikh
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15321 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23samsung/lumpy: Fix build with System Agent blobKyösti Mälkki
Broken with commit: 2585209 mb/samsung/lumpy/romstage: read SPD data of removable DIMM The blob can pick SPDs from the addresses defined in pei_data and we do only define read_spd() with USE_NATIVE_RAMINIT. Change-Id: Ibd6d7a4a53fa808b476d3060872cb10d3dfce534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15329 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
Broken with commit: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Available sandybridge/systemagent-r6.bin has MMCONF hard-coded at some places and samsung/lumpy fails at boot here: CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 2fc94 System Agent: Starting up... System Agent: Initializing These are the last lines as captured over USB debug. Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15328 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23google/reef: Update chromeos.fmd fileFurquan Shaikh
1. Mark 256KiB at end of BIOS region as unusable BIOS region is memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it accordingly in fmd file. 2. Use up holes in RW region for RW_A and RW_B. 3. Fill up holes in RO with UNUSED regions. BUG=chrome-os-partner:54672 Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15313 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA valueLin Huang
for per cs training, there should be more cycles to switch delay line. so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/352953 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rockchip/rk3399: fix sdram training issueLin Huang
After write leveling for all ranks, check the PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or (0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write leveling again. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I1a0e4e888eb62b5fae5b5e5437a385e8660a246d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 717cbac97b2045f2934e99859ce405aa3637b1c4 Original-Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351825 Reviewed-on: https://review.coreboot.org/15300 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23kconfig: add missing SPI TPM CS config definitionVadim Bendebury
To fully define TPM attachment to a SPI interface both bus and CS (chip select) settings are required. Add the missing CS configuration option. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied it is possible to compile in and run TPM2 SPI driver. Change-Id: If297df8e5b9526f156ed1414eb9db317d6af5b33 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353913 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15299 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-23tpm2: add SPI TPM driverVadim Bendebury
This introduces a SPI TPM driver compliant with the TCG issued "TPM Profile (PTP) Specification Revision 00.43" which can be found by googling its title. The driver implements both the hardware flow control protocol and the TPM state machine. The hardware flow control allows to map SPI based TPM devices to the LPC address space on x86 platforms, on all other platforms it needs to be implemented in the driver software. The tis layer is somewhat superficial, it might have to be expanded later. A lot more implementation details can be found in the code comments. Also, it is worth mentioning that this is not a complete version of the driver: its robustness needs to be improved, delay loops need to be bound, error conditions need to propagate up the call stack. BRANCH=none BUG=chrome-os-partner:52132, chrome-os-partner:50645, chrome-os-partner:54141 TEST=with the rest of the patches applied coreboot is able complete Chrome OS factory initialization of the TPM2 device. Change-Id: I967bc5c689f6e6f345755f08cb088ad37abd5d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5611c6f7d7fe6d37da668f337f0e70263913d63e Original-Change-Id: I17d732e66bd231c2289ec289994dd819c6276855 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/350124 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15298 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Tested-by: build bot (Jenkins)
2016-06-23rockchip/rk3399: Clean up voltage rail settingsLin Huang
The CENTER LOGIC should always be 0.9V and can not be adjusted, so use duty_ns = 2860 to correct CENTER LOGIC to 0.9V. And now DDR seems to run stable at 800MHz on the gru board. BRANCH=none BUG=chrome-os-partner:54144, chrome-os-partner:53208 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: Ia900e248c10ddd0ab630446a324cc0446c0fa49b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f4fb1cefb59ac4099cef8b32a68ed9222e708478 Original-Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/352772 Reviewed-on: https://review.coreboot.org/15297 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23gru: kevin: initialize cr50 SPI interfaceVadim Bendebury
Set up the pins and initialize the driver. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate with the cr50. Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349852 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15296 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rk3399: add definition for SP0 iomuxVadim Bendebury
This register is described in the TRM in section called GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0 interface. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate over SPI0 Change-Id: Ieee3fcae6095020042b02673c7d863f398ed2eb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8f155e3b47c9f44ad4e5a2513916572e7d5ec0ab Original-Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349851 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15295 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23kconfig: allow various tpm type and interface permutationsVadim Bendebury
Until now it was assumed that all TPM devices were of the same type (TCG 1.2 spec compliant) and x86 based boards had LPC connected TPMs and all other boards had I2C connected TPMs. With the advent of TPM2 specification there is a need to be able to configure different combinations of TPM types (TPM or TPM2) and interfaces (LPC, I2C and SPI). This patch allows to do it. Picking Chrome OS still assumes that the board has a TPM device, but adding MAINBOARD_HAS_TPM2 to the board's Kconfig will trigger including of TPM2 instead. MAINBOARD_HAS_LPC_TPM forces the interface to be set to LPC, adding SPI_TPM to the board config switches interface choice to SPI, and if neither of the two is defined, the interface is assumed to be I2C. BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that none of the generated board configurations change as a result of this patch. With the rest of the stack in place it is possible to configure different combinations of TPM types and interfaces for ARM and x86 boards. Change-Id: I24f2e3ee63636566bf2a867c51ed80a622672f07 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5a25c1070560cd2734519f87dfbf401c135088d1 Original-Change-Id: I659e9301a4a4fe065ca6537ef1fa824a08d36321 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349850 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15294 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-22mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_ENDFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15293 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-22intel/apollolake: Add API for get_bios_size and use itFurquan Shaikh
get_bios_size returns the value of bios_size. Use this function to calculate bios_size for caching in bootblock. BUG=chrome-os-partner:54563 Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15292 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-22drivers/i2c/generic: Fix compile failureDuncan Laurie
This variable name was changed in chip.h but not the consumer and it was submitted before it was caught. Change-Id: I7c492b588b2fd854a9eeac36029a46da324a7b1b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15109 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22soc/intel/common/acpi: Add _PTS, _WAK methodsHannah Williams
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15121 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22ACPI S3: Add common recovery codeKyösti Mälkki
There is nothing to backup with RELOCATABLE_RAMSTAGE. Change-Id: I780a71e48d23e202fb0e9c70e34420066fa0e5b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22ACPI S3: Fix prohibited wakeupKyösti Mälkki
No boards affected, resume is always allowed when enabled in the build. Change-Id: I1816557da8201af9e137c389b57852ec20390b6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15275 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22ACPI S3: Split support for HAVE_ACPI_RESUMEKyösti Mälkki
Some of the support functions will be built for romstage once HIGH_MEMORY_SAVE is removed. Change-Id: I43ed9067cf6b2152a354088c1dcb02d374eb6efe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22cpu/cpu.h: Change guard around function declarationsKyösti Mälkki
This file is pulled for x86 bootblock builds using ROMCC, which would choke on struct bus. Change-Id: Ie3566cd5cfc4b4e0e910b47785449de81a07b9ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22ACPI S3: Move SMP trampoline recoveryKyösti Mälkki
No need to make low memory backup unless we are on S3 resume path. Hide those details from ACPI. Change-Id: Ic08b6d70c7895b094afdb3c77e020ff37ad632a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15241 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel: Drop old romstage main() without asmlinkageKyösti Mälkki
Change-Id: I0d471766fdf46f6e61ac692fc98730a2429f981f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15234 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15231 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15230 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel cache-as-ram: Fix comment about MTRRsKyösti Mälkki
Change-Id: I5b9e10fe119c1a046494235e85f730bedfe8578d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15282 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21rockchip: kevin/gru: Slow memory down to 300 MHzDouglas Anderson
At the higher speeds stressapptest shows memory errors. We don't want to track down random problems due to simple memory corruption, so slow memory back down to 300 MHz until someone figures out how to make it faster without sacrificing reliability. BRANCH=None BUG=chrome-os-partner:54144 TEST=stressapptest -M 1024 -s 240 Change-Id: I2417f93f65b1491a028a63ce563ed7dd7831becc Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I02182b25e677e27e8541445938f9da9ae9553fa6 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/350480 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15120 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21rockchip: gru: pass poweroff gpio parameter to BL31Lin Huang
To support gpio power off SOC, we need to pass the power off gpio parameter to BL31. Gru reuse tsadc overtemp pin as power off gpio, so need to iomux to gpio function when use gpio power off function, either in bl31 or depthcharge. BRANCH=None BUG=chrome-os-partner:53448 TEST=Build gru Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349703 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15119 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21rockchip: gru: pass reset gpio parameter to BL31Lin Huang
To support gpio reset SOC, we need to pass the reset gpio parameter to BL31. Note: request BL31 have supported this function. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349702 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15118 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-21rockchip: gpio: add macro so we can get gpio numberLin Huang
sometimes we need gpio number, so add this macro so we can get the gpio number if we need. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I0c8c6cc0643a66e9ae1f21b02c7364c641b9805d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I98e8cf15543179904295a86e9f720c2d7c8b443a Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/349701 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15117 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21google/reef: Keep ISH enabled for nowFurquan Shaikh
Disabling ISH causes resets in FSP which leads to hang. This should be fixed in a later stepping. Until then keep ISH enabled. BUG=chrome-os-partner:54033 Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15142 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21libpayload/pci: Correct MASK macro namesFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: I8ef1c595205fe46dd64357051eeb232e2bbbebc1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21intel/apollolake: Calculate BIOS mmap at runtimeFurquan Shaikh
Instead of hard-coding the BIOS region start and end addresses, read BIOS_BFPREG to determine the base and limit for the mapped BIOS region. BUG=chrome-os-partner:54563 Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21intel/apollolake: Add helper routine for spi reg readFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: I56bc6b5292aec676103a436048abee8577edd961 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake: Rename _spi_reg_read/write to _spi_ctrlr_read/writeFurquan Shaikh
This makes it clearer that the read/write operations are being performed on the host controllers registers. Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15281 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21commonlib/region: Add helpers for dynamic initialization of region devFurquan Shaikh
This allows initialization of runtime region devices and xlate region devices where all parameters cannot be statically determined. BUG=chrome-os-partner:54563 Change-Id: Ia6e1b695fed3bbfa08598d1593e650fc1465d41f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15267 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21commonlib/region: Rename XLATE region device init macroFurquan Shaikh
This makes the name consistent with other region device init macros. Change-Id: I248894ba6c85326b615dcb71e8f498bc8be50911 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15277 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake/spi: Add support for reading status regFurquan Shaikh
spi_read_status reads the status register using hardware sequencing and returns 0 on success and -1 on error. Use spi_read_status to return appropriate value for get_sw_write_protect. BUG=chrome-os-partner:54283 Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake: Disable setting of EISS bit in FSPFurquan Shaikh
chrome-os-partner:54589 Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15276 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/skylake: Run spi_init as early as possible in ramstageFurquan Shaikh
spi_init should be run early enough in ramstage so that any init calls (e.g. mainboard_ec_init) that write on flash have right permissions set. Change-Id: I9cd3dc723387757951acd40449d4a41986836d2a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21intel/apollolake: Enable SPI properly in bootblock and ramstageFurquan Shaikh
Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-06-21lpss_i2c: Set SDA hold and support custom speed configDuncan Laurie
This I2C controller has separate registers for different speeds to set specific timing for SCL high and low times, and then a single register to configure the SDA hold time. For the most part these values can be generated based on the freq of the controller clock, which is SOC-specific. The existing driver was generating SCL HCNT/LCNT values, but not the SDA hold time so that is added. Additionally a board may need custom values as the exact timing can depend on trace lengths and the number of devices on the I2C bus. This is a two-part customizaton, the first is to set the values for desired speed for use within firmware, and the second is to provide those values in ACPI for the OS driver to consume. And finally, recent upstream changes to the designware i2c driver in the Linux kernel now support passing custom timing values for high speed and fast-plus speed, so these are now supported as well. Since these custom speed configs will come from devicetree a macro is added to simplify the description: register "i2c[4].speed_config" = "{ LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30), LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30), LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30), LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30), }" Which will result in the following speed config in \_SB.PCI0.I2C4: Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) Name (FPCN, Package () { 52, 120, 30 }) Name (HSCN, Package () { 38, 90, 30 }) Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21payloads/external/GRUB2: Pass CONFIG_GRUB2_EXTRA_MODULESBenjamin Barenblat
Set CONFIG_GRUB2_EXTRA_MODULES from the Kconfig when building GRUB2. This causes the specified modules to actually enter the built payload. Change-Id: I345026af705ba8af77c6c12aba8e1bd4135e519c Signed-off-by: Benjamin Barenblat <bbaren@google.com> Reviewed-on: https://review.coreboot.org/15203 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-06-21cbfstool: Change CONFIG_FMD_GENPARSER if not set to nAlexander Couzens
When doing make in util/cbfstool it contaminates the tree because it generates the fmd_parser. Change-Id: Ida855d1e57560c76d3fcfcc8e2f7f75bcdfdd5d4 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/15221 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-21flashmap: Use CONFIG_ROM_SIZE as flash size in flashmapWerner Zeh
Currently there are two sources for the final size of the flash image. One is defined as a Kconfig variable (ROM_SIZE) and the other can be provided in a user defined flashmap.fmd. This patch will enable the usage of CONFIG_ROM_SIZE in flashmap.fmd to define the flash size. In this way, the Kconfig variable is the only source of information for the flash image size. This way is optional. Change-Id: Id5298e06d360aaa6d94f2b5a2ffa65e45919853e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15219 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21fmaptool: Make base offsets absolute in fmap_config.hJulius Werner
fmaptool generates a header file used to hardcode certain values from the FMAP in coreboot's binaries, to avoid having to find and parse the FMAP manually for every access. For the offset of the FMAP itself this has already been using the absolute offset from the base of the whole ROM, but for individual CBFS sections it only used the offset from the immediate parent FMAP region. Since the code using it intentionally has no knowledge of the whole section tree, this causes problems as soon as the CBFS is a child section of something not at absolute offset 0 (as is the case for most x86 Chromebooks). Change-Id: If0c516083949fe5ac8cdae85e00a4461dcbdf853 Reported-by: Rolf Evers-Fischer <embedded24@evers-fischer.de> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15273 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21google/reef: Add ACPI code for trackpadFreddy Paul
This patch enlists ELAN trackpad on I2C4 for reef board. BUG=None TEST=Build and boot to OS. Ensure ELAN trackpad is working with ELAN trackpad driver enabled in kernel. Change-Id: I788600f16dea9fac0e089cb82ccfc38a960157f9 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15213 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21soc/intel/apollolake: make gpo.h ACPI compatibleFreddy Paul
BUG=None TEST=Build with <soc/gpio.h> included in mainboard.asl Change-Id: Id6fdc50d09c014f930fdfd5c2fde0df827ad5181 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15272 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21beaglebone: Update bootblock.c to use new structs/codeGabe Black
New structures and functions have been added to make it easier and clearer to talk to GPIOs, configure the clock module, and toggle the LEDs. Use that code in bootblock.c instead of doing those things manually with hardcoded addresses. Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/3944 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-21mb/google: remove superfluous header includes in bdw chromeboxesMatt DeVillier
Change-Id: I71443c7547a113bf9b64d48fe5a85c6e2302c8aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-21intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15228 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21qemu/x86: car: drop pointless code, move stack out of the wayGerd Hoffmann
RAM doesn't need any initialization on qemu, so we can simply use it right away. No need to try using the cache as ram in the first place. We also can place the stack in normal ram right from start and we don't have to switch it to another place later on. Place the stack in real mode memory which isn't used for something else. Change-Id: Ib7a3f58a846d139f7babea5f43722a30fe0fe962 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: https://review.coreboot.org/15214 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21util/riscvtools: Add script that turns coreboot.rom into an ELFJonathan Neuschäfer
This is required because SPIKE doesn't support loading flat files yet. Change-Id: If745d78712ca8108b5dcc21591201bc2d3f70b86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20soc/apollolake: Include PCI _OSC methodHannah Williams
Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15110 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20Update SeaBIOS URL to httpsRyan Salsamendi
Change-Id: If1c37bf2bb7df35d5e5ec37cefb9bb92a251f93b Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/15206 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Antonello Dettori <dev@dettori.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20ACPI S3: Cleanup RSDP referenceKyösti Mälkki
Variable name shadows parameter name used on other functions, and it can be local anyway after function removal. Change-Id: I3164b15b33d877fef139f48ab2091e60e3124c3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15240 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-20soc/intel/common: Add _OSC methodHannah Williams
Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
Instead of programming unsupported CAS use the highest supported value. Start at DDR3 maximum of CAS 18T. Increase error message verbosity level. Useful for overclocking. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Allows to run a DDR3-1600 DIMM at 933Mhz. Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15217 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Calculate the value from current DDR frequency. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20arch/x86/smbios: Add DRAM manufacturerPatrick Rudolph
Add Ramaxel DRAM manufacturer id. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The manufacturer name shows up in dmidecode. Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15183 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20include/device/dram/ddr3: Add additional frequenciesPatrick Rudolph
IvyBridge memory controller supports more frequencies than SandyBridge. Required for future patches. Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15182 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Simplify calculation of value. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15181 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
Set max_mem_clock_mhz in devicetree to 933Mhz. Allows to run the memory at up to DDR3-1866. The same frequency was allowed within the first vendor bios, but Lenovo than decided to limit it to DDR3-1333. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The RAM is now running at DDR3-1600 instead of DDR3-1333. This gives about 4% performance increase in glmark2 using the Intel GPU. Change-Id: If15be497402d84a2778f0434b6381a64eda832d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15158 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-20amd/fam_10h-fam_15h: allow building without microcode updatesArthur Heymans
CPU_MICROCODE_MULTIPLE_FILES relies on SUPPORT_CPU_MICROCODE_CBFS, which is not set if CPU_MICROCODE_CBFS_NONE is set. This makes selecting CPU_MICROCODE_MULTIPLE_FILES conditional. Change-Id: I0c28f99a1b868bbf90a6f048cce3bea4ff849f76 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15259 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-20amd/geode: Fix comment about ACPI S3Kyösti Mälkki
As RAMTOP gets removed, comment becomes inaccurate. Change-Id: Iaf25b88a4065d15c0c0682425b1d033e4a36590f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20VIA C7 NANO: Fix early MTRR settingKyösti Mälkki
It would not be possible to set MTRR for range 1MiB to 4MiB. Our RAMTOP is power of 2 and enabling cache for bottom 1MiB should cause no problems. Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-19intel/broadwell: Remove old USBDEBUG backup store in CARKyösti Mälkki
Required EHCI state is maintained as a CAR_GLOBAL to have it properly migrated. Change-Id: I8df413bec6faae4952670710c8ac804e0331c966 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15236 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>