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2019-01-03sb/intel/*: Use common files for PCIe ACPIArthur Heymans
The result is that i82801{g,i,j}x now use the correct _PRT table for their root port number. Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03sb/intel/bd82x6x: Move pcie ACPI code to a common placeArthur Heymans
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03mb/google/poppy/variants/nami: Add sku_ids for PantheonFrank Wu
Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic03c3a6fe238f2692ce15c45016115087380c0ca Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-01-03google/kukui: Initialize DRAM from romstageJunzhi Zhao
Add DRAM support for google kukui. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-03mediatek/mt8183: Add DDR driver of memory test partHuayang Duan
Write a range of memory with special pattern, and read it back to check whether the read value same as write. The test pattern include 8bit offset read write, 16 bit offset read write, 32bit offset read write, and cross testing. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I30d5fbd3db2acf36e3058ba4f34558b981fba78c Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28845 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03mediatek/mt8183: Add DDR driver of runtime config partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-03mediatek/mt8183: Add DDR driver of rx datlat calibration partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28843 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZEElyes HAOUAS
Use already defined ARRAY_SIZE macro. Change-Id: Ie22e3557e958b562816921a985411dd55c712142 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-03nb/intel/pineview/raminit.c: Remove unused variableElyes HAOUAS
Change-Id: I1e0009677fda44faab2021e1c44827fdba803061 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-03Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixedTristan Corrick
PCIe graphics for display output still doesn't work, but that is now listed in the Haswell-specific documentation. Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03Doc/nb/intel/haswell: Add a list of known issuesTristan Corrick
Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30455 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03drivers/aspeed: Fix AST2400 POST failure without BMC FW or VBIOSTristan Corrick
This patch is from Linux, commit 3856081eede2. The commit message there is: > commit 3856081eede297b617560b85e948cfb00bb395ec > Author: Y.C. Chen <yc_chen@aspeedtech.com> > Date: Thu Feb 23 15:52:33 2017 +0800 > > drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS > > The current POST code for the AST2300/2400 family doesn't work properly > if the chip hasn't been initialized previously by either the BMC own FW > or the VBIOS. This fixes it. > > Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > Tested-by: Y.C. Chen <yc_chen@aspeedtech.com> > Acked-by: Joel Stanley <joel@jms.id.au> > Cc: <stable@vger.kernel.org> > Signed-off-by: Dave Airlie <airlied@redhat.com> Tested on a Supermicro X10SLM+-F with an AST 2400 where the BMC flash chip has been completely erased. Before the patch, the display resembled a rainbow. After the patch, the display works well. Original-Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com> Original-Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Original-Tested-by: Y.C. Chen <yc_chen@aspeedtech.com> Original-Signed-off-by: Dave Airlie <airlied@redhat.com> Change-Id: I72efcf907fbd1263fe21d4f36fe900b305419c44 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao
Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to implement GPIO toggling method, covered for both CNP_LP and CNP_H pch. BUG=N/A TEST=Build and boot up fine on sarien platform, add an dummy STSX in DSDT table, read back from iotools to confirm the GPIO tx state get updated. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f Reviewed-on: https://review.coreboot.org/c/30461 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03nb/intel/haswell: Add support for PEGTristan Corrick
This means that any PCIe device placed in a PEG slot should now work. During S3 resume, link training sometimes does not complete before device enumeration. However, no tangible issues have been observed. Fixing it would introduce a rather large delay in S3 resume. There are a few minor shortcomings: - Using PEG for display output is not yet supported. - Only PEG2 is supported. An extra (unknown) training sequence is said to be needed for PEG3. - The ACPI _PRT method is not yet generated, so legacy interrupt routing doesn't work for devices with multiple functions. Tested on an ASRock H81M-HDS. Using a Radeon HD 6450 graphics card works under GNU/Linux, with PRIME [1]. An x1 PCIe card was also tested in the PEG slot, and it appears functional. [1]: https://wiki.archlinux.org/index.php/PRIME Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointersTristan Corrick
If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL. The existing Lynx Point systems probably don't end up dereferencing NULL pointers this way. However, it might occur on a system using Flexible I/O to remap PCIe root ports to other functions. Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues presented themselves. Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30079 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03mb/asrock/h81m-hds: Move GPIO header to a linked C fileTristan Corrick
Using a linked C file is the standard approach for GPIO settings. Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03sb/intel/lynxpoint: Remove incomplete SATA ACPI codeTristan Corrick
The existing SATA ACPI code for Lynx Point implements some methods and devices, but not completely. These methods are optional and only used in IDE mode. The code was likely copied from bd82x6x, where it has since been removed. As a result, many remarks produced by iasl about unreferenced objects are eliminated. Tested on an ASRock H81M-HDS and an Acer C720. No issues with SATA were observed. Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03mb/lenovo/x200: Remove RCBA replayArthur Heymans
This either sets unwanted or unnecessary settings. Tested. Everything still works fine. Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-03src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER)Elyes HAOUAS
Use smm-$(CONFIG_HAVE_SMI_HANDLER) instead of smm-y Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/intel/wtm2: Remove duplicated HAVE_SMI_HANDLERElyes HAOUAS
HAVE_SMI_HANDLER already selected in broadwell/Kconfig file. Change-Id: Ic40b5296eae78cd83c59212042d94424251524b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/intel/{kblrvp,kunimitsu,saddlebrook}: Remove duplicated HAVE_SMI_HANDLERElyes HAOUAS
HAVE_SMI_HANDLER already selected in skylake/Kconfig file. Change-Id: I754cf41a4f97d1e692ad4209e4a59987dce2624b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/google/{auron,jecht}: Remove duplicated HAVE_SMI_HANDLERElyes HAOUAS
HAVE_SMI_HANDLER is selected here: broadwell/Kconfig Change-Id: I50c664198a954f661416c8cb1ced05f8775d8e07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/gigabyte/ga-b75m-d3{h,v}: Remove duplicated HAVE_SMI_HANDLERElyes HAOUAS
HAVE_SMI_HANDLER is already selected here: bd82x6x/Kconfig Change-Id: I920800bb7c67cb5efd5dac0a9338a76214de2cab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/google/{glados & variants}: Remove duplicated HAVE_SMI_HANDLERElyes HAOUAS
HAVE_SMI_HANDLER is already selected in soc/intel/skylake/Kconfig Use "smm-$(CONFIG_HAVE_SMI_HANDLER)" in Makefile.inc files. Change-Id: Ia60e34ee03958b05f2ac0c326632b6dd9f02a2e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/foxconn/d41s: Program the subsystemidArthur Heymans
Change-Id: I4f9d0cfc9a5bfa259d734f194b015e7be1694ceb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03mb/intel/dg43gt: Program the subsystemidArthur Heymans
Change-Id: I9f979e63378b1e0090a57849038eaafeb20d7a40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03util/chromeos/crosfirmware.sh: Print more messagesTristan Corrick
The existing code has several messages that are only printed when the DEBUG variable is set. These messages are not verbose, and are quite useful to see how the script is progressing. So, print them unconditionally. Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03util/chromeos/crosfirmware.sh: Check for dependenciesTristan Corrick
crosfirmware.sh has dependencies that might not be installed on some systems. If a dependency is missing, provide a clear message about the issue and how to resolve it. Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30549 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Print download statusTristan Corrick
It's quite useful to know the download progress, as it can take a while even with a fast connection. For example, the peppy recovery image is ~600 MiB. It also lets the user know that disk space is being filled. Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Add /sbin to PATHTristan Corrick
On some systems, such as Debian 9.6, `parted` and `debugfs` are located in /sbin. Adding /sbin to PATH means that this script can work when run as a regular user. Change-Id: I151dba467e2b196f13093334273dae8a05865491 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03Doc/nb/intel/haswell: Mention util/chromeos as a way to get mrc.binTristan Corrick
Change-Id: Ic099d0f052db5ef6a699d54b26028bae2fae4770 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-03mb: Remove duplicated ENABLE_VMXElyes HAOUAS
ENABLE_VMX is CPU specific and it is already enabled here: src/cpu/intel/common/Kconfig Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-03soc/intel: Fix bad uses of __SIMPLE_DEVICE__Kyösti Mälkki
Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught because files only build with __SIMPLE_DEVICE__ defined. Remove cases of testing __SIMPLE_DEVICE__ in files that are not build for ramstage. Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03mb/google/hatch: Make WP_RO range align with winbond specificationSubrata Banik
This patch ensures to make memory protected range between 01C00000h - 01FFFFFFh as per winbond spi datasheet https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf section 7.1.15 BUG=none BRANCH=none TEST=build for hatch. Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30552 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03mb/google/dragonegg: Make WP_RO range align with winbond specificationSubrata Banik
This patch ensures to make memory protected range between 01C00000h - 01FFFFFFh as per winbond spi datasheet https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf section 7.1.15 BUG=none BRANCH=none TEST=build and boot dragonegg. Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30551 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-02soc/intel/skylake/graphics: Ensure intel_gma_restore_opregion() is calledNico Huber
Change-Id: If981fa3db12b3a4fe1411f4cce9bac8564697769 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/25466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-01-02mb/google/octopus/variants: Add 20ms reset delay for WACOM deviceMarco Chen
Add reset delay in power resource to prevent from failing to bind after unbinding. And boards including yorp series - bobba / phaser and bip series - ampton are affected. BUG=b:121286833 BUG=b:117474421 BUG=b:121019320 BRANCH=None TEST=emerge-octopus coreboot, verified that WACOM touchscreen can re-bind successfully. Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488 Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/30422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-01soc/intel/cannonlake: Enable CNVi based on devicetreeMaulik V Vaghela
Set PchCnvimode to Auto if CNVi is enabled in device tree. This will allow FSP to configure CNVi. Change-Id: I4f77fe5e9f561d3b498403e42dfc7afdcfaedf6f Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30516 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-01mb/google/hatch: Enable CNVi Wifi for hatchMaulik V Vaghela
This patch enables CNVi wifi for hatch 1. Enable CNVi device in device tree 2. Configure GPIO pad config for CNVi BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30436 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-01mb/google/hatch: Add NC gpios for display and correct the orderMaulik V Vaghela
Correcting order of display related GPIOs and also adding not connected pin definitions for display GPIOs BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-31src/cpu/microcode: Add code to update microcode in assemblyArthur Heymans
Add code to update microcode from cbfsfiles using assembly. Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-31mb/google/hatch: Enable NVME support for HatchV Sowmya
This patch enables the x4 NVME device for hatch, * Enable the Root port 9. * Assign the usage type for clock source. * Configure the GPIO for CLK SRC 1. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30431 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-31mb/google/hatch: Add the USB port configurationV Sowmya
This patch adds the configurations for, * USB 2.0 ports. * USB 3.0 ports. * Enables USB xHCI controller. * GPIO config for USB2_OC2 and USB2_OC3. * Add the ACPI objects to configure USB ports. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30457 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-31mb/google/hatch: Enable SATA for HatchV Sowmya
This patch enables the SATA for hatch, * Enable the SATA port 1. * Configure the GPIO for SATA. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30435 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-30soc/intel: Fix ugly preprocessor macroKyösti Mälkki
Macro hides that dev_find_slot() takes two arguments. Change-Id: I639af31b9d4a2d702dfd2baebddbb8352e8bf9b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-30device/pci_early: Fixes for __SIMPLE_DEVICE__Kyösti Mälkki
The feature is used to enable PCI MMIO accesses behind PCIe links (or bridges) before PCI enumeration has been completed. Add the feature for bootblock, verstage and postcar, it is required with add-on PCIe serial cards for early console output. It's up to the board specific code to configure PCIe root port prior to calling console_init() for this to work. Remove feature from ramstage, it bypasses any resource allocations and bus number assignments. For the moment PCI configuration support before ramstage is available only on ARCH_X86. Also switch from device_t to pci_devfn_t. Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30drivers/uart/oxpcie: Fix early consoleKyösti Mälkki
Fix build for POSTCAR_STAGE=y. Also add driver for bootblock and verstage. Change-Id: If57033353c07854e21b630c58ad69931eb572da9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30arch/x86: Add CAR stack location symbolsKyösti Mälkki
Add symbols for the non C_ENVIRONMENT_BOOTBLOCK builds and use them for stack guards. Change-Id: Ib622eacb161d9a110d35a7d6979d1b601503b6f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30arch/x86: Use a common timestamp.inc with romcc bootblocksKyösti Mälkki
The same file was replicated three times for certain soc/intel bootblocks, yet there are no indications or need to do chipset-specific initialisation. There is no harm in storing the TSC values in MMX registers even when they would not be used. Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30arch/x86: Prevent romcc bootblock from using MMX registersKyösti Mälkki
Platforms with SSE=y or SSE2=y will invoke romcc with -mcpu=k7. This implicitly enabled romcc to consume MMX registers, if XMM set was consumed first. Explicitly tell romcc not to clobber MMX set. Change-Id: I37f1d6ea01873036712dfbb32bb1dcd5d769e85d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30cpu/intel/car: Drop remains of setup_stack_and_mtrrs()Kyösti Mälkki
Platforms have moved to POSTCAR_STAGE=y. Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30bootblock: Move function prototypeKyösti Mälkki
Change-Id: I01ecb9a16099ac6189ce3f0bdbd43c23ad7c621d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29mainboard: Add Supermicro X10SLM+-FTristan Corrick
This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-29mb/google/glados/variants/caroline/devicetree.cb: Remove unneeded white spacesElyes HAOUAS
Change-Id: I7fdf8934187d2786fdac23ed4460147867c25044 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-29mb/google/octopus: Override emmc DLL values for FleexBora Guvendik
New emmc DLL values for Fleex. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Id0022e9d0f0a7802113bbf193decff3c8aaa04f8 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30226 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29sb/intel/bd828x6x: Make CONFIG_ELOG=y compileArthur Heymans
The function pch_log_state() was overlooked when making the smi relocation code common. Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-29soc/intel/skylake: Remove romcc related Kconfig optionArthur Heymans
Change-Id: I9090be3ccaa8a61312293e9da3679a752a908062 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-29nb/intel/haswell: Handle boards that do not support IGDTristan Corrick
Processor graphics is disabled on, for example, the C222 and C224 chipsets. The change to resource assignment in northbridge.c prevents the following warning that occurs when the IGD is disabled: > skipping PCI: 00:00.0@3 fixed resource, size=0! Tested on a Supermicro X10SLM+-F, which has the IGD disabled by the chipset. The graphics memory is reclaimed and no issues were observed. Also tested on an ASRock H81M-HDS. This board has an IGD, but no regressions were observed. Change-Id: I86d4aef50b6588f08b86c9758a4b95ccd65e9a96 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-29nb/intel/haswell: Don't unconditionally set DEVENTristan Corrick
The existing code sets DEVEN with the intention of enabling the IGD and Mini-HD audio. However, according to the datasheet [1] and some testing on hardware, the bits in DEVEN are set by default if and only if the straps/fuses say the device should be enabled. To illustrate this, here are a few initial values of DEVEN on some Haswell systems: Supermicro X10SLM+-F: 0x0000002d ASRock H81M-HDS: 0x00000039 Acer C720: 0x000000b1 On the X10SLM+-F, the IGD is disabled by default, and PEG10 & PEG11 are enabled by default. On the C720, the PEG devices are all disabled by default, while the IGD and Mini-HD audio are already enabled. There are two issues that result from the existing behaviour: PEG devices are unconditionally disabled, and devices are set as enabled when it's not actually possible to enable them. So, don't touch the DEVEN register at this stage, as there are no benefits. Interestingly, on an Acer C720 (Google Peppy), a PCI device 00:04.0 appears. It is a thermal sensor. `powerstat` was used to measure idle power usage over 30 minutes under Debian GNU/Linux 9.6. There was no change in reported power draw. [1] Desktop 4th Generation Intel® Core TM Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family Datasheet – Volume 2 of 2. December 2013, revision 003, document number 328898. Change-Id: I242f9138472de5a0b26b5852f632b53b2920132d Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-29nb/intel/haswell: Use DEVEN to disable devicesTristan Corrick
This allows devices to be properly disabled when they are set to `off` in the devicetree, or when a device has its `enabled` property set to false. A message is printed stating that a device is being disabled, even if it was already disabled via DEVEN. However, it could be useful to have this information, so such messages are kept. The device 00:04.0 is a thermal sensor on the Acer C720, but it has not been named as such in this patch. This is because the public datasheets never formally acknowledge what the device is, and how it might differ across platforms. Tested on a Supermicro X10SLM+-F. The Mini-HD audio is disabled now, silencing a warning from Linux. Also tested on an Acer C720 (Google Peppy). Disabling "device 4" from devicetree.cb works. Also tested on an ASRock H81M-HDS. For this device, and all other test devices, there were no regressions observed. Change-Id: If1504e620967449a09f113a7c771a1ec30380644 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30270 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29mb/google/sarien: Adjust GPD3 pin terminationLijian Zhao
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf Reviewed-on: https://review.coreboot.org/c/30374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-29mb/google/hatch: Enable Host Bridge/CSME/PMC/P2SB/SMBusRizwan Qureshi
* Enable host bridge. * Enable CSME. * Enable Power Management Controller. * Enable Primary to Side Band Bridge Controller. * Enable SmBus Controller. BUG=b:120914069 BRANCH=None TEST=code compiles with the changes Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-28mb/pcengines/apu2/romstage.c: disable SVI2 wait completionKrystian Hebel
On some platforms SVI command completion is not reported by voltage regulator. Because of that CPU got stuck in invalid P-State, which resulted in lower frequency and inability to reboot platform without performing cold reset. Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-28util/xcompile/xcompile: Use tab for indentElyes HAOUAS
Change-Id: I9878e6d962004003e2c05a6cdb8ecb0a3a02ae66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-28superio/smsc/sch5147/acpi/superio.asl: Remove unneeded white spacesElyes HAOUAS
Change-Id: I8a5d937bfc1e0ff61736c19a24b03c1a8defc427 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-28util/inteltool: Add support for Sunrise Point LPMatthew Garrett
Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-28intel/fsp1_0/cache_as_ram.inc: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I93cf734daefabe1f7cfaa5f49ba789ac04c8a635 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-28arch/x86/c_start.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I415993bf11f6a019ff8ef4c0cba3b5bb511271fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30453 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28drivers/amd/agesa/cache_as_ram.S: Fix coding styleElyes HAOUAS
Change-Id: Iada9b3ba71b991b6f9c7ebb5f300c8d28829ab4f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-28src/cpu/intel/model_f4x: Update cpu_tableElyes HAOUAS
CPUID 0xf47 tested on on 945G-M4 board. Needs more MSR's consistency tests. To do: test if speedstep.c and speedstep/acpi.c are ok for model_f4x. Change-Id: I285ad33804592e3df510d61dd24f14f944e05142 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/17409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28ec/chromeec: fix LPC read/write for MEC devicesMatt DeVillier
Commit 8cf8aa2 [ec/google/chromeec: Use common MEC interface] changed the return mechanism for the checksum on reads/writes for MEC devices, but incorrectly handled the passed-in csum parameter by not dereferencing. This led to the returned csum value always being zero, which causes all EC commands with non- NULL data_in to fail with a checksum error. Fix this by storing the returned checksum in a temp variable, and only assigning to csum when the pointer isn't NULL; Test: build/boot google/chell, verify EC hello command succeeds, keyboard backlight turned on at boot. Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28mb/google/poppy/variant/nami: add the vbt setting for bard skuRen Kuo
Modify the vbios's eDP signal setting from level0(0dB) to level1 (3.5dB) for bard Add VBT blobs and include it in cbfs BUG=b:119448457 TEST=Test & measure eDP signal Change-Id: I0b854a6adad43844282aed61d26e798727b5cb62 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30375 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28intel/gma/Makefile.inc: Add a helper function to add VBT binariesArthur Heymans
This adds a convenient helper function to add vbt binaries to cbfs. Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30430 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28sb/intel/lynxpoint: Handle H81 only having 6 PCIe root portsTristan Corrick
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30077 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mb/google/octopus: Override emmc DLL values for PhaserBora Guvendik
New emmc DLL values for Phaser. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30144 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mainboard/google/poppy/variants/rammus: Fixed touchscreen function failedKane Chenffd
According to issue tracker b:119238959 #4 & #6. Hardware modify design to make GPP_E3 to be a switch of touchscreen I2C CLK and SDA. Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during power on initialization to avoid data transfer during this time. After touchscreen IC initial complete, control GPP_E3 to high to make touchscreen I2C CLK and SDA work normally. Depending on touchscreen IC specification, device take 105ms for power on initialization. Change delay time from 120ms to 105ms. BUG=b:119238959 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, run S5 stress test and verify the result Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86452c1445243c499aeaf931dba286db169c5628 Reviewed-on: https://review.coreboot.org/c/30180 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki
Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mb/google/hatch: Enable SPI controller for HatchRizwan Qureshi
Enable SPI controller(D31:F5). BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-28arch/x86: SSE2 implies SSE supportKyösti Mälkki
Change-Id: Ic9ffcfadd0cd41bb033ed2aec9fb98009dd62383 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-28mb/google/hatch: Enable console UARTMaulik V Vaghela
This patch incorporates following changes to enable console on UART0 1. update default console number to 0 2. Enable PCI port for UART0 GPIO configuration will be done by coreboot based on correct console number. Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-28mb/google/hatch: Enable LPC/eSPI controllerAamir Bohra
Enable LPC/eSPI controller(D31:F0). EC would be using eSPI interface, since the strap GPP_C5 is pulled up. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-28src/northbridge: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-28soc/intel: Drop romstage_after_car()Kyösti Mälkki
Platforms moved to POSTCAR_STAGE so these are no longer used. Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-27mb/google/hatch: Add SMI handlersAamir Bohra
Add SMI handlers for below SMI events: 1. eSPI SMI event. 2. ACPI enable/disable SMI event -> Add support for EC to configure SMI mask on ACPI disable. -> Add support for EC to configure SCI mask on ACPI enable. 3. Sleep(S3/S5) SMI event -> Add support for EC to configure wake mask for S3/S5 event Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25mb/google/hatch: Add HPD GPIO support for displaysMaulik V Vaghela
Adding hot plug detect GPIO support for external Type-C display in event for cable connect/disconnect. Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30365 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-25mb/google/hatch: Modify hatch SPI flash layoutV Sowmya
This patch modifies the hatch flash layout to support IFWI 1.6 with the following regions, Flash Region 0: Descriptor [0x0 - 0xFFF] Flash Region 1: IFWI (consist of ME and PMC FW) [0x1000 - 0x3FFFFF] Flash Region 2: BIOS [0x1400000 - 0x1FFFFFF] Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30413 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-25mb/google/hatch: Enable EC LPC interface and configure IO decode rangeAamir Bohra
Enable EC LPC interface and configure below LPC IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25mb/google/hatch: Add SoC and EC asl files in DSDTAamir Bohra
This implementation adds below code: 1. Add SOC ACPI code in dsdt.asl -> platform.asl -> globalnvs.asl -> cpu.asl -> northbridge.asl -> southbridge.asl -> sleepstate.asl 2. Add chromeos.asl in dsdt.asl 3. Add EC ACPI code in dsdt.asl -> superio.asl -> ec.asl 4. Remove config for WAK/PTS ACPI method as chromeec doesn't implement those. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25mb/google/hatch: Add EC trigger events and acpi configsAamir Bohra
This implemetation adds EC SCI, SMI, S5/S3 wake trigger events. Also adds the EC specific ACPI configs to enable support for ALS, EC PD device and PS2 keyboard device. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I3a86f609c269cb59e546fc7ba4ba032e5ea8341a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30281 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24soc/intel/*: Select SUPPORT_CPU_UCODE_IN_CBFS only onceArthur Heymans
This was selected twice. Change-Id: I7e20b7d3f05ecae98db1addf5aea7bf1159f4682 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-24Remove intel/skylake/bootblock/timestamp.incKyösti Mälkki
Platform has been moved to C_ENVIRONMENT_BOOTBLOCK and this file was for romcc bootblock. Change-Id: I2c249b18edd41c9a7798400d24b1c9228422d59b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-24soc/intel/quark: Drop BOOTBLOCK_SAVE_BIST_AND_TIMESTAMPKyösti Mälkki
This was empty stub call doing nothing, to avoid targeting non-existing MMX registers. Change-Id: I78b83e6724159ea1eb0f8a0cf9d5b7ddfc9877b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-24mb/asus/p5qpl-am: Add mainboardArthur Heymans
This mainboard has the BSEL straps hooked up to the SuperIO similar to the ASUS P5GC-MX and might therefore require a restart. Tested: - FSB 800, 1067 and 1333MHz CPUs - USB - Ethernet - Serial - 2 DIMM slots - SATA - Libgfxinit (VGA) TESTED with SeaBIOS (sercon disabled) and Linux 4.19. Change-Id: Id845289081751ff8900e366592745f16d96f07c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-24driver/spi/eon.c: Add EN25F80Arthur Heymans
TESTED on ASUS P5QPL-AM (writes MRC_CACHE) Change-Id: I5aebe4703a033a0f0226f405d8933b12f3af136f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24arch/x86/wakeup.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24arch/arm/memmove.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24x86/smm/smmhandler.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I7a10ddf79cf457b5dde21714b13890fc9510e7ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24car/non-evict/exit_car.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I53e33c54fe3ff7b6276a5bbf7defd2db33a60f0f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24Documentation/nb/intel: Add Haswell documentationTristan Corrick
At the moment, this just gives some details on the MRC. Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-24drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT`Tristan Corrick
Any board that uses the AST driver will have support for native graphics init. So, select the option in the driver instead of every board. Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 07:20:46 +0000