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2017-09-08soc/amd/stoneyridge: Update amdfw buildMartin Roth
- The SMU firmware used to be named *.sbin, now is named *.csbin. Update the makefile so that the files can be named as they are delivered and don't have to be renamed. - Add a Kconfig option to allow the secure os binaries to be excluded. BUG=b:64932297 TEST=Build with old and new firmware, verify file sizes. Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-08soc/intel/braswell: add USB2 PHY PERPORTRXISET UPDKevin Chiu
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add USB2 phy setting overrideMatt DeVillier
Adapted from Chromium commit 9756af8. Create hook function to override USB2 phy setting from board level. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add SoC stepping identify helperMatt DeVillier
Adapted from Chromium commit 9756af8. Add SOC helper to identify BSW SoC stepping. Will be used to override USB2 phy setting based on stepping in subsequent commit. Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08soc/intel/braswell: Add I2C clock config optionsDivagar Mohandass
Cherry-pick from Chromium commit e3c1ec2. This change includes - FSP config parameters to configure I2C clock speed. - Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz. Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08drivers/intel/fsp1_1: Adjust check for FSP header revisionMatt DeVillier
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1 header files, so adjust the header revision check to ensure that the FSP blob isn't newer than the header, rather than an exact version match. This resolves a version mismatch issue with Braswell ChromeOS devices, which ship with FSP blobs newer than the publicly-released blob (1.1.2.0), but older than the current Braswell FSP 1.1 header (1.1.7.0). TEST: build/boot google/cyan and edgar boards, observe no adverse effects from using current FSP header (1.1.7.0) with the factory- shipped FSP blobs (1.1.4.0/1.1.4.2). Change-Id: I8934675a2deed260886a83fa34512904c40af8e1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08soc/intel/common/block: Common ACPIShaunak Saha
This patch adds the common acpi code.ACPI code is very similar accross different intel chipsets.This patch is an effort to move those code in common place so that it can be shared accross different intel platforms instead of duplicating for each platform. We are removing the common acpi files in src/soc/intel/common. This removes the acpi.c file which was previously in src/soc/common/acpi. The config for common acpi is SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's Kconfig file in order to use the common ACPI code. This patch also includes the changes in APL platform to use the common ACPI block. TEST= Tested the patch as below: 1.Builds and system boots up with the patch. 2.Check all the ACPI tables are present in /sys/firmware/acpi/tables 3.Check SCI's are properly working as we are modifying the function to override madt. 4.Extract acpi tables like DSDT,APIC, FACP, FACS and decompile the by iasl and compare with good known tables. 5.Execute the extracted tables in aciexec to check acpi methods are working properly. Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-08siemens/mc_apl1: Disable internal UARTsMario Scheithauer
APL internal UARTs are not used on this mainboard. Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08siemens/mc_apl1: Set bus master bit for on-board PCI deviceMario Scheithauer
There is one on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I45202937eba11da3bea14fef6ebed70599804335 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08intel/car: Fix stack guard placementKyösti Mälkki
Make sure guard placement is above CAR region. Change-Id: I780cdc0b2a549e7ac4b23b0870619f5648a644e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21313 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08AGESA: Drop old ACPI S3 resume pathKyösti Mälkki
Fixed ACPI S3 support will use POSTCAR_STAGE and no longer uses the code removed here. Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08arch/x86/postcar: Support CBMEM_TOP_BACKUPKyösti Mälkki
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE for MTRR setup after adding this file in the build. Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08arch/x86 postcar: Fix use with stage_cacheKyösti Mälkki
Postcar failed when loading from stage_cache, if romstage did not pass same pcf->stack on normal and resume paths. Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08stage_cache: Add rmodule params in metadataKyösti Mälkki
The change allows to update rmodule parameters after it has been loaded from stage cache. Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08soc/intel/skylake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik
This patch implements soc function to get previous sleep state using chipset_power_state global structure. acpi_get_sleep_type is needed in PRE_RAM stage when soc selects CONFIG_EARLY_EBDA_INIT kconfig option. Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-07soc/intel/common/sgx: Fix null pointer dereference warning from klocworkPratik Prajapati
Fix the warnings of klocwork scan. e.g. "Pointer 'dev' checked for NULL at line 158 will be dereferenced at line 159" Change-Id: I6cc9c68652b074c666c86456183460ca38a886ed Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06google/gru: Re-enable 3V rail GPIO on ScarletJulius Werner
We've decided to move control for the 3.0V rail (technically 3.3V on Scarlet, but who cares about millivolts) back to a GPIO on the AP for Scarlet rev2. This patch adds the necessary code to enable it and make ARM TF aware of its existence. Since the pin had previously not been connected to anything, we shouldn't really need to guard this by board ID... older Scarlets will just be twiddling an empty pin. Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-09-06AGESA f14: Work around soft-resetsKyösti Mälkki
Vendorcode expects some DRAM controller registers to be writable, but they are actually locked after soft resets if C6 states are enabled. Without the workaround, raminit fails on soft resets. Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06mainboard/lippert: Refactor SEMA watchdog messageKyösti Mälkki
It's too critical to ignore when sending the message on SMBus fails, so allow for a fair amount of retries. Failure here causes watchdog to do hard reset later. Move it out of mainboard.c as we need to call this early in romstage while we are debugging. Change-Id: I1006b079269d6dd44de630db7a5694124af2f974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kgpe-d16: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kcma-d8: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-09-06asus/kcma-d8 kgpe/d16: Fix regression for shutdownKyösti Mälkki
Fix regression caused by commit: 714709f AMD fam10 ACPI: Use common fixed sleepstates.asl Adding common sleepstates.asl got lost in rebase process. Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Iru Cai <mytbk920423@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-06mb/google/{poppy,soraka,eve}: Add imon and vmon params for Max98927 codecHarsha Priya
This patch adds imon and vmon slot numbers for Maxim 98927 driver. These values are used to confiure IV feedback for audio playback on speakers. BUG=b:36724448 TEST=After boot, the register dump for Max98927 codecs should have imon and vmon slots numbers set in 0x1e register. Change-Id: I4382da4f984507d147751c168e8177b58c88a70f Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06driver/i2c/max98927: Add imon and vmon paramsHarsha Priya
This change list adds imon and vmon slot numbers as params for Maxim 98927 driver. These values are looked up in the kernel driver to confiure IV feedback for audio playback on speakers. BUG=b:36724448 TEST=After boot, the register dump for Max98927 codecs should have imon and vmon slots numbers set in 0x1e register. Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06util/cbmem: Pretty print STAGEx_META and _CACHEKyösti Mälkki
Also align entries without name with additional indents. Change-Id: Ia6aa303daa11e6aec249232aadf4e346bad659d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06soc/intel/cannonlake: remove duplicate uart.c from bootblockNick Vaccaro
There was already a uart.c added to bootblock. Remove the duplicate addition. Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06soc/intel/cannonlake: Add Vboot/ChromeOS supportLijian Zhao
Add Vboot and ChromeOS support in SOC Kconfig, include a separated verstage in Makefiles.inc as well. Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06mb/google/soraka: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. Change-Id: I76742801e84449d0910ddadf31d39597df3263b9 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06soc/intel/skylake: Add config for enabling PCIe AERRizwan Qureshi
Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06tint: Use the current time as random seedNicola Corna
Previously the random seed was fixed, which led to the same sequence of blocks for each run. Now that libpayload has time(), no change is needed in the function rand_init() of tint. Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/20980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-06util/testing: Don't keep tegra lp0 build resultsPatrick Georgi
We don't actually care for them on our testers, just that the files can be built. Change-Id: Ib656a085d70e2aeb1601f1943ad8581af3133839 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21420 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06AGESA vendorcode: Auto include-dirsKyösti Mälkki
AGESA internal headerfiles are allover the place. Luckily, they have unique names within the Proc/ tree so include every existing directory in undefined order. Change-Id: I86f080e514391a3f0f05d379d24d490ce075060e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-063rdparty/vboot: update to latest masterPatrick Georgi
Besides some internal changes that won't have much effect on coreboot, the newer version also supports building host tools on systems that self-designate as i686. Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06util/testing: Also test-build tegra's lp0 resume codePatrick Georgi
The regular build doesn't build it, so it fails every now and then due to changes in its dependencies. Make sure we notice these early. Change-Id: I0603b22887487d8871611d91e6f8ab0ec210bff1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06Revert "soc/intel/cannonlake: Add dummy ACPI DSDT table"Kyösti Mälkki
This reverts commit 6c0f3c7ee1d53872851dbab636787852e3572c98. Reason for revert: Broke master builds, this was submitted out-of-order, some of the dependencies have not passed review with +2 yet. Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-09-06postcar: Add cbmem_stage_cacheKyösti Mälkki
S3 resume path executing through postcar was unable to utilise cached ramstage in CBMEM. Change-Id: Icc8947c701ca32b4f261ebb78dfc1215b7ed2da0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06AGESA: Drop LATE_CBMEM_INIT in new interfaceKyösti Mälkki
Change-Id: Iffa6cf495b4649f73a1095732509f195ac828248 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06AGESA: Rename assembly from .inc to .SKyösti Mälkki
Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06AGESA f14: Fix duplicate call on S3 resume pathKyösti Mälkki
Change-Id: Ie316df6e2babd8b3e9e79f45ea9719b52b0c2902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06AGESA f15tn f16kb: Fix ACPI S3 resume for FCHKyösti Mälkki
This recovers FCH configuration on S3 resume path. Appearst to work, but other defects of HAVE_ACPI_RESUME must be fixed also before S3 support is re-enabled. Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06mb/sapphire/pureplatinumh61: Disable the SuperIO serialNicola Corna
There is no serial port on this platform. In addition, put the LPC serial IRQ into quiet mode. Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/21226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06soc/intel/cannonlake: Add dummy ACPI DSDT tableLijian Zhao
A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06arch/x86/Kconfig: Add deprecation warnings for LATE_CBMEM_INITJonathan Neuschäfer
The deprecation of late (post-romstage) CBMEM initialization was announced in this blog post: https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ There are two warnings: * In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that aims to explain the problem. * In src/mainboard/Kconfig (just below the mainboard selection), there's a warning which points the user at LATE_CBMEM_INIT, if such a board is selected. Also update the function that needs to be implemented, as pointed out by Keith Hui and Kyösti Mälkki. Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-06nb/intel/i945/raminit.c: Refactor tRD selectionArthur Heymans
Inspired by gm45 code, which sets this value the same way. Some values for tRD on 800 and 1067MHz FSB were set wrong because the CAS/Freq selection was wrong. CAS was often selected to low and when fixing CAS this results in tRD being too high, due to an incorrect lookup table which caused instability. PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5 on GA-945GCM-S2L. Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06device/dram/ddr2: Add a function to normalize tCLKArthur Heymans
Also make most significant bit function accessible outside the scope of this file. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06Makefile: Include Makefile from site-localNaresh G Solanki
Include Makefile from site-local even in absence of DOTCONFIG. This will allow execution of Makefile option from site-local in absence of DOTCONFIG as well. Change-Id: I62d1562687ffe18546add80fdde1196700a65236 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/21303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06Makefile: Keep list of exported variablesNico Huber
This can be useful to unexport them later. Change-Id: I2ce9eff32d817ec190441550116376843abd1c11 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06mb/winnet/g170: Drop AMD car.h file from Via mainboardJonathan Neuschäfer
08f7d1ae0d ("mainboard/via*: Drop AMD car.h file") did the same for all Via mainboards that were in tree at that time, but the winnet/g170 was merged a bit later. Change-Id: Iedb33f4c2fce6fc2cf2669fee4ffb25bf793c92b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06intelmetool: Add support for Sunrise Point-HShawn Chang
Tested on P10S-M WS. Change-Id: I62f78fe5ca03bf70497939a12f0036bf247b2aa7 Signed-off-by: Shawn Chang <citypw@gmail.com> Reviewed-on: https://review.coreboot.org/21301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-09-06abuild: Allow building with any toolchainDamien Zammit
Adds -A --any-toolchain option to abuild This is handy for those who want to test compiling all board configs with abuild using a non-coreboot toolchain Change-Id: Idd599b0d2c324ad88ba3c83cdf3b180eb6d1fc80 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0Martin Roth
Cherry-pick from Chromium 414024e. Update the FSP 1.1 header to version 1.1.7.0, required for susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices. As this header update doesn't shift offsets, only adds new fields in previously unused/reserved space, it should not negatively impact existing boards built against the older header version. Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020 Original-Signed-off-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Tested-by: Martin Roth <martinroth@chromium.org> Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06sb/intel/i82801jx: Use __packedJonathan Neuschäfer
__packed has been introduced in commit 6a00113de8 ("Rename __attribute__((packed)) --> __packed"). Use it. Change-Id: Ifd33129ae4fbe14c26ceeaaa88832ef994a32dfb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06soc/amd/stoneyridge: Use __packedJonathan Neuschäfer
__packed has been introduced in commit 6a00113de8 ("Rename __attribute__((packed)) --> __packed"). Use it. Change-Id: Ie654567ebff884b911de10bd9fef605436e72af8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06ec/lenovo/h8: Add BDC detection supportPatrick Rudolph
* Add support for detecting BDC. * Allows to turn off power to BDC if no card is installed. * Should fix https://ticket.coreboot.org/issues/99 . Add the following devicetree values: * has_bdc_detection Set to one to indicate that the following register are sane. * bdc_gpio_num SB GPIO num to read. * bdc_gpio_lvl SB GPIO level for card to be present (usually zero). Don't enable BDC power if no card is detected. As there are no devicetree values yet, the new code doesn't have any effect. Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-06ACPI S3: Remove conflicting local acpi_get_sleep_type()Kyösti Mälkki
We now require EARLY_CBMEM_INIT and romstage_handoff to support HAVE_ACPI_RESUME. Thus acpi_handoff_wakeup() would never call an externally defined acpi_get_sleep_type(). Name _sleep_type() was also inapproriate here, as it referred to hardware-dependent SLP_TYP field of PM1CNT but still returned ACPI_Sx value instead. Change-Id: I8dc130f1e86dd7e96922d546f0ae9713188336cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-09-06soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocworkSubrata Banik
This patch fixes klocwork bug due to recent memmap.c implementation where “Pointer 'dev' returned from call to function 'dev_find_slot' at line 144 may be NULL.” Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05intel/skylake: nhlt: Add capture configuration format for IV feedback from ↵Harsha Priya
max98927 This changelist adds the capture format to be set for max98927. The nhlt blob is the same but the format params for capture are different from the render. BUG=b:36724448 TEST=IV feedback data is of good quality Change-Id: I135cf4479e89cd2046ff46027f94c0f71aed650e Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05mb/google/soraka: Camera PMIC run time power controlNaresh G Solanki
Currently PMIC (tps68470) is in active state even when cameras are not in use. PMIC is put into SLEEP mode only when entering S3 via smihandler. With this change PMIC will be put into SLEEP mode as soon as sensors & VCM voltage outputs are turned off. This will allow run time power saving when camera is not in use. PMIC will be reset in first boot & across S3 & S0ix cycles. Also, remove the smi handler for PMIC power management & handle it as part of sensor and VCM ACPI PowerResource. BUG=b:63903239 TEST= Build for Soraka. Check Camera probe, Capture image across S3 & S0ix cycles. Also checked the following & found no regression: 1. Typical camera use cases 2. Stability tests related to camera 3. Reliability tests related to camera 4. PnP tests related to camera 5. Latency related tests with camera Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05nvidia/tegra*: Use xcompile for compiler prefix unless specifiedPatrick Georgi
GCC_PREFIX is uncommon in the coreboot tree. If not provided, take data from .xcompile to fill in the blanks. Change-Id: I711a73be9d35d896198664f0ae213218653f275e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-05Move ADDR32() hack to arch/x86Patrick Georgi
It's arch specific, so no need to pollute non-x86 with it. Change-Id: I99ec76d591789db186e8a33774565e5a04fc4e47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21392 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-05mainboard/intel/harcuvar: Add support for Intel Harcuvar CRBMariusz Szafranski
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC ("Denverton" and "Denverton-NS") for the communications segment/market. The MohonPeak coreboot was used as the starting template with additions/modifications from other Intel Apollo Lake/Skylake coreboot. Tested with TianoCore payload (UDK2015) and Poky (Yocto Project Reference Distro) 2.0 with kernel 4.1.8 booted from SATA drive and external USB pendrive. Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-05soc/intel/denverton_ns: Add support for Intel Atom C3000 SoCMariusz Szafranski
This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-05soc/intel/cannonlake: Set IGD stolen memory size to 64MBSubrata Banik
This patch overrides default FSP IGD stolen memory size UPD value. TEST=Ensures FSP-M UPD “IgdDvmt50PreAlloc” value is 0x2 (64MB) Change-Id: I63d992e139810ad203137b34c98d1a463f88b92d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-05nb/intel/common: Write MRC cache at exit of BS_DEV_INITNico Huber
We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat- forms now. The SPI controller is initialized at start of BS_DEV_INIT (dev_initialize()). The SPI lockdown usually shouldn't be a problem but the SPI driver imple- mentation lacks full support for the locked interface. Also, some options exist to lock all flash regions read-only until the next reboot. Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com>
2017-09-05Documentation: Update Lesson2.mdEvelyn Huang
Update Lesson2.md to include information about updating a commit after it has been pushed to the remote repository. Change-Id: Iebf86113b13d859d9c9e3db51e22ea44cb1144f6 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-05soc/intel/common/block/gpio: Fix PAD_DW1_MASKHannah Williams
for case CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y https://ticket.coreboot.org/issues/128 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I2b0b9c07ebc99f4b4d7e8c5a72483bedd33e2e07 Reviewed-on: https://review.coreboot.org/21282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-04Kconfig: Move and rename ADD_VBT_DATA_FILEPatrick Rudolph
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to INTEL_GMA_ADD_VBT_DATA_FILE. Depend on Intel platforms to avoid confusing users of non-Intel platforms. The Intel GMA driver will use the vbt.bin, if present, to fill the ACPI OpRegion. Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-04util/board_status: do a spell checkIdwer Vollering
Change-Id: Ie39be471851586076343b8e9454a9140d4664b8d Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/21322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-02libpayload/storage: Add Sunrise Point AHCI PCI idNico Huber
Change-Id: I9645d76d05014722e4ae0c398d82f7f8e34d6f1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-02mainboard/google/fizz: Enable support for DPTFTsai, Gaggery
This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for fizz. It also enables the DPTF flag in the device tree for fizz. BUG=b:64915426 BRANCH=None TEST=emerge-fizz coreboot and run DPTF observation tool to make sure DPTF is up and running. Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-02buildgcc: Fix up cross GCC buildingNico Huber
Add a missing line-break escape and, rather cosmetic, guard execution of $CXX which we allow but don't force to be set. Change-Id: Icf6d3b7de4b7999b8214489f28997964c490d1e9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21307 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02mainboard/google/soraka: Remove wacom digitizerWisley Chen
We have no wacom digitizer on I2C#3, so remove it. TEST=build and boot on soraka. Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21309 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-02mb/hp: Enable ExpressCard hotplug in all ElitebooksIru Cai
The MPC.HPCE bit of the ExpressCard root port is not set in vendor firmware, so autoport didn't generate the right pcie_hotplug_map to support ExpressCard hotplug. Also add comments for each PCIe root port. Change-Id: Ic53e36a7192b9bfa8ff9fca57f4556e972e2611b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/21310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-02clang: Allow ANY_TOOLCHAIN for non-coreboot clangDamien Zammit
Previously, only when selecting GCC could any toolchain be selected, this allows compiling with distro clang/llvm. Change-Id: I2d9d02f360d54ed92d6b6f55e6fcd530aae79adb Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-02Fix build with CLANG, avoid GCC only CFLAGSArthur Heymans
Commit 7c8d331fbb "Fine-tune compiler flags" added CFLAGS that are not existing on CLANG hence breaking building coreboot with clang. Fixes: https://ticket.coreboot.org/issues/134 Change-Id: Ie0250e285b0c5a9f8ee2eb99401aeca875d2789a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-02clang: Enable integrated assembler on clang buildsDamien Zammit
Change-Id: I883bf7eb2ab52ba3d7a284c96d4aade8bc1ee4ae Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21221 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-02cpu/x86/smm: Fix explicit 'addr32' usage in clang buildsEdward O'Callaghan
The addr32 prefix is required by binutils, because even when given an explicit address which is greater than 64KiB, it will throw a warning about truncation, and stupidly emit the opcode with a 16-bit addressing mode and the wrong address. However, in the case of LLVM, this doesn't happen, and is happy to just use 32-bit addressing whenever it may require it. This means that LLVM never really needs an explicit addr32 prefix to use 32-bit addressing in 16-bit mode. Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb Also-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02soc/intel/cannonlake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ib4943a7f7929775bd5e9945462e530ef68a398b8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02soc/intel/skylake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02intel/common/cpulib: Add API to configure MCAPratik Prajapati
Add mca_configure() API to configure Intel Machine Check Architecture (MCA). Change-Id: I5e88c7527ce350824e48892caa978b2b78f1de20 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02util/lint/checkpatch: Untaint variables from env & command lineMartin Roth
Jenkins is giving warnings due tainted variables from the environment and command line: Insecure $ENV{PATH} while running setgid at util/lint/checkpatch.pl line 907, <$conststructs> line 39. Insecure dependency in piped open while running setgid at util/lint/checkpatch.pl line 907, <$conststructs> line 39. This should fix those warnings. Change-Id: I6a09915d13547bf9a86c011d44cbcd39c46f3fec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02nb/intel/pineview: Enable dram remappingArthur Heymans
Without this remapping code enabled, the system fails to boot properly if the amount of ram inserted is larger than 4G minus the mmio space (hardcoded to 1G here). Change-Id: I02e7ceed0cd9db7eb7182481b6989f80cef31ee5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-01soc/intel/cannonlake: Define Max PCIE Root PortsPratik Prajapati
This patch defines Max PCIE Root Ports and fixes bellow Coverity scan defect, *** CID 1380036: Control flow issues (NO_EFFECT) /src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params() 79 >>> CID 1380036: Control flow issues (NO_EFFECT) >>> "i" is converted to an unsigned type because it's compared to an unsigned constant. 80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { 81 if (config->PcieRpEnable[i]) 82 mask |= (1 << i); Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: add *spi.c files to makeNick Vaccaro
Adds spi.c and gspi.c to verstage. Change-Id: I363d9aafa989c5a7a0b36ad9edf1c70a75604d28 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: add gpio files to makeNick Vaccaro
Adds gpio.c to romstage and ramstage. Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS. Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01nb/intel/i440bx/debug.c: Bugfix and cleanupKeith Hui
Fix dump_pci_device() broken by commit 65b72ab5 (Drop print_ implementation from non-romcc boards) in 2015 (!) where only one in 16 bytes were being dumped. Also remove the #if made redundant by commit aef8542 (Compile debug.c only if CONFIG_DEBUG_RAM_SETUP) as this whole file is only compiled in that case. Also clean up headers that were included twice. Change-Id: I60e272b29417039feb15540e49d7300f86e5ed21 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-01intel/i440bx: Move LATE_CBMEM_INIT under mainboardKyösti Mälkki
Some of these will move to EARLY_CBMEM_INIT. Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
2017-09-01buildgcc: Integrate nds32 update from Andes TechnologyStefan Reinauer
This patch has been provided by Mentor Chih-Chyang Chang on behalf of Andes Technology. It fixes using the coreboot toolchain to compile the Chrome EC code base on the ITE8320 embedded controller. The new patch incorporates a fix for the issue previously fixed by patches/gcc-6.3.0_nds32.patch, so that patch can be removed. patches/gcc-6.3.0_riscv.patch needs to be slightly adjusted to still apply cleanly (configure scripts only). Change-Id: I0033888360f13ba951b692b3242aab6697ca61b3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-01soc/intel/canonlake: Enable LPSS UART in 32bit PCI modeLijian Zhao
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode. To maintian compatibilty with previous generation of SOC, select 32 bit mode as default. Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/toucan-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/frontrunner-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik
This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/apollolake: Use SMM library to get tseg region informationSubrata Banik
This patch uses smm common library function to get tseg base address and size. Hence removing definitions of smm_region() from soc directory. BRANCH=none BUG=b:63974384 TEST=Build and boot reef successfully. Change-Id: I091ca90cf576c0da35cf3fe010f8c22a18ef82d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/skylake: Use SA library to get smm region informationSubrata Banik
This patch uses system agent common library to know tseg region start and size. Unable to remove smm_region() function from soc code as SMM common library is not yet available for skylake use. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If98b65805753db2c30d6fea29e401a17cef39799 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-31google/gru: Support Nefario rev0Philip Chen
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario. Also, remove DVS support for CENTERLOGIC. BUG=b:64702054, b:63537905 TEST=build coreboot Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/21176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-31lenovo/g505s: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: Ia65f9ecb62767424744e399a43e4728666fd28b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31lenovo/g505s: Enable XHCI device in devicetreeKyösti Mälkki
Enabling XHCI is additionally controlled with Kconfig option HUDSON_XHCI_ENABLE. Even when it is enabled, it EHCI debug works on the USB port next to the DVD drive door. Change-Id: I83738da6015f58ecd0819c553d333a176365dc78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31AGESA: Remove separate f15rlKyösti Mälkki
Change-Id: I18c62ad034249c5ad14e5d5e708b4f0d4bcbf400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31lenovo/g505s: Switch from f15rl to f15tnKyösti Mälkki
Support code for Trinity and Richland is identical now. I have also come across a unit with Trinity model CPU, whose CPUID was not listed in f15rl while f15tn already had support for f15rl. Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31cpu/x86 asm: Just use the correct op suffixEdward O'Callaghan
LLVM AS doesn't support as much GNU junk extensions, data16/32 is almost never needed in truth if we just use the correct op suffix. So do that here, fixes clang/llvm builds with the integrated-as toggled on. Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0 Also-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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