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2018-02-15drivers/i2c: Add chip driver for I/O expander PCA9538Werner Zeh
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C bus. Add a chip driver to support this chip. Beside the pure chip driver two interface functions are provided to read the state of the pins and write output values to the pins. As the slave address of this chip is hardware configurable the function pca9538_get_dev() is used to get the right slave address. This function needs to be implemented in mainboard code if one needs to use the interface functions to read and write I/O state. Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)Jonathan Neuschäfer
This format (one hex digit, followed by 'b', followed by binary digits) is arguably useful, but also confusing. Use the more common format instead. Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-14drivers/i2c/designware: Remove spurious word ("familuar")Jonathan Neuschäfer
Fixes: b8dc63bdfe ("ic2/designware: Move Intel i2c logic to shared driver") Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23714 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Reviewed-on: https://review.coreboot.org/23677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-14drivers/adau7002: Fix include fileDaniel Kurtz
Add missing license and include guard and remove unneeded include. BUG=b:72121803 TEST=compiles Change-Id: Ic359ed262086596a98131669f8eecd531857187a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23721 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-14soc/amd/stoneyridge: Set up LAPICMarc Jones
LAPIC setup is required to set virtualwire mode for legacy interrupts. This was omitted when stoneyridge was changed to use the common mp_init. BUG=b:72351388 TEST=Verify keyboard now works in SeaBIOS Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-13mb/google/poppy: Fix the SPD for samsung_dimm_K4A8G165WBFurquan Shaikh
Original SPD provided by the vendor had bytes after 254 shifted by 16 bytes. This change fixes the SPD data based on the latest details received from the vendor. BUG=b:72749394 TEST=Verified that the device with this memory part boots to OS fine. Also, mosys is able to dump the right memory information. Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-13drivers/uart/pl011: Improve PL011 driverDavid Hendricks
This adds a struct for registers along with some bits from ATF to the generic PL011 driver. It also adds a naive implementation of uart_tx_flush() which was previously stubbed out. Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-12arm64: Add read64() and write64()David Hendricks
Change-Id: I89cf4b996405af616f54cf2d9fabd4e258352b03 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23036 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12armv8: Allow for ARMv8 extensions to be chosenDavid Hendricks
There are now a few architectural extensions available for ARMv8, some of which introduce instructions or other features that may be useful. This allows the user to select an extension implemented on their SoC which will set the -march option passed into the compiler. Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-12mainboard/google/zoombini/variants/meowth: enable touchscreenNick Vaccaro
BUG=b:69011806, b:72179988 BRANCH=master TEST=Verify touchscreen on meowth works with this change. Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-02-12google/kahlee: Select HAVE_ACPI_RESUMEMarshall Dawson
TEST=Run powerd_dbus_suspend and resume with button press BUG=b:69614064 Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22732 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12amd/stoneyridge: Add S3 support to POSTMarshall Dawson
Add/update the romstage and ramstage paths to check for S3 resume and call the appropriate AGESA functions. TEST=Suspend/Resume Kahlee with full S3 patch stack BUG=b:69614064 Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12soc/amd/common: Call AmdS3FinalRestoreMarshall Dawson
AMD support in coreboot has typically not used the AmdS3FinalRestore() Entry Point. Add a call to it immediately prior to resuming to the OS. BUG=b:69614064 TEST=Check console log for execution Change-Id: Iadc4438d8cda9766002f6edade3c7b00b23b98b4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12soc/amd/common: Add S3 resume functions to wrapperMarshall Dawson
Add new functions that can execute InitRtb, InitResume, LateResume, and FinalResume. Note that the name AmdInitRtb supersedes the deprecated AmdS3Save. TEST=Suspend/Resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12vc/amd/00670F00: Introduce S3FinalRestore helperMarshall Dawson
The Arch2008 spec describes an AmdS3FinalRestore Entry Point that coreboot has been missing. Add the helper function that can call into the blob to execute this. BUG=b:69614064 Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12soc/amd/common: Replace missing AmdReleaseStruct() callsMarshall Dawson
The AGESA spec states that "Failure to release a structure can cause undesired outcomes." Uncomment the one in AmdInitLate(). The function only dealocates the structure used for the AGESA entry point, and not the internal data used by coreboot. Release the structure in AmdInitEnv(). This appears to have been an omission years ago when duplicating agesawrapper.c for every mainboard was still common. BUG=b:70671742 TEST=Build and boot Kahlee, inspect console log Change-Id: Ib1ff94ec2acdc845c5e4b4ed7088061cfc0c55f3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22888 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12soc/amd/common: Add S3 supporting functionsMarshall Dawson
Add functions that the wrapper will call to get and save the S3 data. The wrapper requires two types of data saved: * Non-volatile: Information that is the minimum required for bringing the DRAM controller back online. This change uses the common mrc_cache driver to manage the storage * Volatile: May be stored in DRAM; information required to complete the system restoration process. TEST=Suspend/Resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12ec/chromeec: Fix battery ACPI mutex levelMatt DeVillier
Commit 07fe618 [chromeec: Add support for reading second battery info] added a mutex as part of the ACPI code to determine battery statuses. Windows is extremely picky about ACPI code, and attempting to acquire a level 1 mutex without first having acquired a level 0 mutex causes Windows to hang on boot. Since there's no reason to use a level 1 mutex here, change it to level 0. Test: Boot Windows on device with ChromeEC without hanging Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-12google/snappy: enhance BigDaddy USB#2 2.0 strengthKevin Chiu
Fine tune 14" BigDaddy USB#2 2.0 strength: PERPORTPETXISET: 7 PERPORTTXISET: 1 IUSBTXEMPHASISEN: 3 PERPORTTXPEHALF: 0 this value could have USB#2 2.0 EA/function pass. BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23649 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11soc/intel/cannonlake: Add Pch iSCLK programmingLijian Zhao
In order to reduce BOM cost and board area for imaging solution, the sensor requires a 19.2/24MHz reference clock from PCH. In addition to that, having PCH to supply the sensor reference clock will prevent dependency on CPU power management and also avoid level shifter cost. Pch iSCLK is only required for CNP-LP with the camera sensor on the platform. BUG=None TEST=Boot up into OS and read back PCH iSCLK programming through iotools. Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23367 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11mb/google/fizz: Set SATA GPIOs in bootblockShelley Chen
Previously, we were seeing device boot into the recovery screen with error code 0x5a. This was root caused to the SATA GPIOs (specifically DEVSLP) not being initialized early enough, causing the SATA 1 link detection to time out and the device to reboot into recovery with 0x5a instead of booting into the OS as usual. BUG=b:69715162 BRANCH=None TEST=after flashing BIOS, set gbb flags to 0, then type reboot from the OS. Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mb/google/poppy/variants/nautilus: set oem_id, oem_table_id fields of ↵Naveen Manohar
acpi_header_t This change makes the Nautilus platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:68686020 TEST=Build, booted nautilus board. Verified kernel reads new strings. Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/23648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mainboard/google/meowth: Enable ECT againLijian Zhao
Previously ECT was disabled in commit 22401, on D0 stepping system and FSP version 7.x.20.52, disabling ECT will cause memory training failure and the system is stuck at post code 00D5h. BUG=b.72473063 TEST=Apply patch and build coreboot image, flash into meowth P0 system with D0 stepping silicon installed, system can pass memory training and boot up into OS. Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-10mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_tKaiyen Chang
This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23670 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10payloads: Add an option to compress secondary payloadsArthur Heymans
Both GRUB and SeaBIOS can chainload lzma compressed payloads. Therefore it is beneficial to compress secondary payloads like Memtest86+, coreinfo, nvramcui,... for both size reasons and often also speed reasons since the limiting factor is generally the IO of the boot device. Tested with SeaBIOS and memtest86+ master on Thinkpad X220. Change-Id: Iddfd6fcf4112d255cc7b2b49b99bf5ea4d6f8db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-10mb/google/grunt: Add ADAU7002 to devicetreeDaniel Kurtz
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S converter. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10drivers/adau7002: Add driver for handling ADAU7002Daniel Kurtz
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from Analog Devices. On some boards they are a used to convert a PDM audio data stream from a DMIC to an I2S signal. Add a driver for populating ACPI table entries for this part. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2018-02-10mb/google/kahlee: Add grunt audio codecs to devicetreeDaniel Kurtz
Remove manually written asl entries for grunt's DA7219 and MAX98357A audio codecs, and replace them with equivalent devicetree entries. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-10drivers/i2c/da7219: Allow GPIO based interruptDaniel Kurtz
Allow specifying the DA7219 interrupt pin as either an Interrupt or GpioInt. BUG=b:72121803 TEST=(with whole patch series) Grunt Kernel discovers DA7219 on i2c0 Change-Id: I2d26731bf4c0ad590dad2c5d26c252371f415f9a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-10util/broadcom/secimage: Add distclean targetMartin Roth
When running 'make distclean' on coreboot, the build cleans the tools as well. Since secimage didn't have a distclean target, it gave an error that the distclean target didn't exist. This didn't actually affect anything more than the secimage clean, but it was impossible to tell that from the warning: % make distclean make[1]: *** No rule to make target 'distclean'. Stop. Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10soc/amd/stoneyridge: Put outl arguments in correct orderMartin Roth
outl takes value then port. BUG=b:72130849 Test=None Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-09chromeec: Fix ACPI compile warningLijian Zhao
For system without secondary battery, current DSDT will report warning during build time. Add a conditional check to make sure only battery index 0 can return success. TEST=Build pass. Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-09drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driverSubrata Banik
As per FSP 2.0 specification and FSP SOC integration guide, its not expected that SMBIOS Memory Information GUID will be same for all platform. Hence fsp_find_smbios_memory_info() function inside common/driver code is not generic one. Removing this function and making use of fsp_find_extension_hob_by_guid() to find SMBIOS Memory Info GUID from platform code as needed. Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08soc/intel/cannonlake: Add support for EMMC DLL updateLijian Zhao
Add option to have customized DLL setting for EMMC interface to make EMMC able to run at HS400 speed. BUG=None Change-Id: I38bc022d8c05dd1fbd03dc26aa6f33cd249e8248 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08mb/intel/kblrvp: Enable Kabylake RVP8V Sowmya
Add support for KBL RVP8 board * Add KBL RVP8 support in Konfig. * Add KBL RVP8 config option in make menuconfig. * Add descriptor and ME binary paths for RVP8 in Kconfig. * Add RVP8 board name Kconfig.name. * Add devicetree.cb for RVP8 in the variants path. * Add gpio.h for RVP8 in variants/include/variant path. TEST= Build and boot RVP8. Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23383 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-08mb/google/poppy/variants/nami: Revise AC/DC loadlinesGaggery Tsai
This patch revises AC/DC loadlines from VRTT reports. +----------------+-------+-------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------+-------+-------+-------+ | AcLoadline | 11 | 2.4 | 3.1 | 3.1 | | DcLoadline | 10 | 2.46 | 3.1 | 3.1 | +----------------+-------+-------+-------+-------+ BUG=b:72351128 b:72129954 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings are passed to FSP. Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-08soc/intel/skylake: Clean up SMBIOS Table Type 17 creationSubrata Banik
* Add Memory Channel Status Enum for Channel detection. * Align > 80 characters per line. * Add hob_size == 0 check. Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17Subrata Banik
This patch ensures to have Type 17 SMBIOS table for CannonLake Platform. TEST=Enable to get correct SMBIOS DIMM type information as per SMBIOS spec 3.1 Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/google/fizz: Set Pmax to 120 for all SKUsShelley Chen
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4 (71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) + ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W. BUG=b:71594855 BRANCH=None TEST=Make sure correct pmax value is being passed into fsp Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23633 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-02-07google/kahlee/grunt: Fix 2 device specific variablesAkshu Agrawal
* micbias_lvl -> micbias-lvl * mic_amp_in_sel -> mic-amp-in-sel BUG=b:71875600 TEST=Checked in kernel the values are set Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/23603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/amd/gardenia: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build gardenia. Change-Id: I24a71490777b101b069175460f3715ec3ff78240 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07soc/amd/common: Add generic create_struct call to wrapperMarshall Dawson
Create a generic function that reports an unsuccessful call to AmdCreateStruct(). Change-Id: I2654b4f21de5a2621086142681181a687be2c8e3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-02-07mb/google/poppy/variants/poppy: Enable EC_ENABLE_SECOND_BATTERY_DEVICENicolas Boichat
BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: I869bf08341b83f359066709e1e9c03af99482b2c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-07chromeec: Add support for reading second battery infoNicolas Boichat
We share the same shared memory fields for both batteries. When the host wants to switch battery to read out, it will: - Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index - Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value - Then fetch the data BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23598 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-07soc/amd/common: Improve misc. formatting in AGESA wrapperMarshall Dawson
Improve the file with: * C99 inializations for structures * reorder include files for aesthetics * remove extraneous whitespace * remove a stale comment * make variable naming consistent * make function arguments consistent This change clears up all remaining checkpatch issues with the wrapper with the exception of errors created with AMD definitions, e.g. ERROR: need consistent spacing around '*' (ctx:WxV) #32: FILE: src/soc/amd/common/block/pi/agesawrapper.c:32: void __attribute__((weak)) SetFchMidParams(FCH_INTERFACE *params) {} BUG=b:62240746 TEST=Build and boot Kahlee Change-Id: I40985e0cf50df6aa4d830937e7f6b6e7908f72fe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07amd/stoneyridge: Put stage cache into TSEGMarshall Dawson
Add a function to allow an external region to be located in TSEG. Select the option to use memory outside of cbmem. Increase the size reserved in TSEG. Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07lib/stage_cache: Add save/get raw storageMarshall Dawson
Leverage the stage_cache mechanism to store a non-specific type of data. This is not interesting when the location for the cache is in cbmem. However it will be more useful when an external location is used, e.g. when the cache is in TSEG, locked from user modification. Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for ↵Subrata Banik
CNP-PCH This patch ensures soc/sata.c correctly translates pci config offset 0x92 Bit 0-2 [SATA Port x Present (SPDx)] 0 = Port x is enabled. 1 = Port x is disabled. Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07soc/intel/common/block: Fix SATA chipset register definitions anomaliesSubrata Banik
SATA PCH configuration space registers bit mapping is different for various SOCs hence common API between SPT-PCH and CNL-PCH causing issue. Add new Kconfig option to address this delta between different PCH. Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22Furquan Shaikh
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is removed from deep_sx_config as well. BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23594 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07security/vboot: overwrite existing spaces during factory init for tpm2Andrey Pronin
In TPM 2.0 case, if the factory initialization is interrupted after defining, say, the kernel tpm nvram space but before writing to this space, the following will happen upon reboot when the factory initialization will be re-attempted. Writing to this space will be skipped, and coreboot will finish the factory initialization with this space remained unwritten. At a later stage, when the rollback logic will attempt to check the version in the kernel space, it will fail (TPM2.0 returns an error when reading from unwritten spaces), and the system will go into recovery with no way out (since the kernel space will never be written). This change fixes that by always writing to the kernel, MRC hash and firmware spaces during factory initialization, even if the space already existed by that time. BUG=b:71884828 TEST=delete, define, but not write to the kernel space; trigger factory initialization; coreboot should fill the kernel space and continue booting. Change-Id: I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b Signed-off-by: Andrey Pronin <apronin@google.com> Reviewed-on: https://review.coreboot.org/23456 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2018-02-07storage: Fix CMD13 failure issueBarnali Sarkar
This patch stores the correct capabilities for EMMC media which in turn sets the correct timing data for HS400 mode. Without this code change, EMMC CMD13 is failing at the end of HS400 mode switching. BUG=none BRANCH=none TEST=Build and boot Soraka Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23541 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCESBarnali Sarkar
This patch changes the sequence of post_cpus_init() function of mp_init to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path. Also, the fast_spi_cache_bios_region() call inside post_cpus_init() function is left out, since caching the SPI Bios region is not required now at this stage. BUG=none BRANCH=none TEST=Build and boot in Soraka (KBL), executed stability tests on multiple systems. Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07soc/intel/skylake: Add Kabylake PCH H device ID'sV Sowmya
Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H. Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23382 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06nb/intel/sandybridge: Always use the same MMCONF_BASE_ADDRESSArthur Heymans
'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the use of fallback/normal with both the native raminit and the mrc.bin. Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that 128MB less is available to devices using the native raminit. Most devices reserve 2048M for non memory resources below 4G, which in most cases is more than adequate. Devices with only 1024M (and that don't already use the mrc.bin) are: * lenovo/x220 * lenovo/x230 * lenovo/x131e * lenovo/x1_carbon_gen1 Those could fail to allocate PCI resources, but on at least x220 with a somewhat default configuration (USB3 expresscard, Wireless PCIe card) it still boots fine, so one should not expect many problems from this change. Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-06google/gru: Add another 512KB to the COREBOOT FMAP regionJulius Werner
With the new extra detachable UI elements, we're running out of space in Scarlet's RO CBFS. Thankfully, the GBB is still massively overdimensioned, so we can steal another half MB from there. This patch changes the FMAP for some boards that have already had production firmware releases. However, all the new changes are to the RO parts of the FMAP, so there shouldn't be a way this could cause a problem for updates. Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06soc/intel/skylake: sort CPU_SPECIFIC_OPTIONS and drop duplicateVadim Bendebury
ACPI_NHLT happens to be selected twice. BRANCH=none BUG=none TEST=generated fizz .config does not change Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/23601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06util/broadcom/secimage: Add HMAC testAlex Thiessen
One of responsibilities of the `secimage` tool is signing the image using the HMAC-SHA256 algorithm. The test being added verifies that secimage's internal call yields same result as the according openssl tool does. Change-Id: I8de4328f435af56901a861e3d5e733657c3c7f78 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06nb/intel/haswell: Use the common MRC cache driverArthur Heymans
This driver uses an fmap region for the MRC cache instead of a CBFS file which makes it easier to manage if one wants to write protect it. Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPIArthur Heymans
Tested to display the register content correctly on a Lenovo Thinkpad X220. Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-06inteltool: Fix displaying 64bit spi registersArthur Heymans
The registers were taken from the wrong addess since the spibar offset was not added to it. This also fixes the endianness. Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23478 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06mb/google/kahlee: Fix grunt I2C rise/fall timesJustin TerAvest
I2C bus rise/fall times were measured as follows. Signals were generated with: - bus 0: manual i2c driver in depthcharge - bus 2,3: i2cdetect -r <bus_number> and then measured manually with an oscilloscope. BUG=b:72442912 Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06soc/intel/appololake: Remove dead MPINIT code selectionArthur Heymans
This not hooked up anywhere. Change-Id: I95a2d14aea6f1a6013edf1bcb88bb35de88cba4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23458 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06cpu/intel/haswell: Don't select PARALLEL_CPU_INITArthur Heymans
PARALLEL_CPU_INIT pertains to initialize_cpus() in src/cpu/x86/lapic/lapic_cpu_init.c which haswell does not use as it uses PARALLEL_MP init. Change-Id: I46b6f72e8e372b8c8564243ece7aed3a9371c621 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06nvramtool: Fix message when option table is not foundArthur Heymans
Having an option table pertains to CONFIG_USE_OPTION_TABLE. Change-Id: Ia8a84e3e59ee50444c7f7d17b34bea86ee475909 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded codeRichard Spiegel
Remove #if statement and replace it with if(IS_ENABLED(...)) per coreboot recommendations. BUG=b:62200858 TEST=Build kahlee. Change-Id: I268b228706a625e1415c4f24e808261c279ba41e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-06mb/google/kahlee: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build kahlee. Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-06soc/intel/cannonlake: Increase heap sizeJohn Zhao
After adding NHLT and max98373 amp support, cnlrvp fails to boot with error: out of memory (free_mem_ptr >= free_mem_end_ptr). Increase HEAP_SIZE from 0x4000 to 0x8000. BUG=None TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp and verify cnlrvp boots to kernel. Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mainboard/broadcom/blast: Remove unnecessary braces {}Elyes HAOUAS
Fix coding style Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23523 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/asus/m2v-mx_se: Add `cmos.default`Paul Menzel
Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB for size for video RAM. Order the entries like in `cmos.layout`. Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/23468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-06mb/google/eve: Enable HotPlug on PCIe root port for WiFiDuncan Laurie
Enable HotPlug for the PCIe root port that the WiFi device is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23512 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06soc/intel/skylake: Add devicetree variable for PCIe HotPlugDuncan Laurie
Add a variable to fill out the FSP UPD variable for PCIe HotPlug, which allows a mainboard to enable HotPlug on individual root ports. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06google/kahlee: Initialize non-early i2c buses in mainboard_initDaniel Kurtz
Initialize non-early i2c buses in ramstage. BUG=b:69407112 TEST=Boot depthcharge w/ CLI enabled on grunt. devbeep => plays beep BRANCH=None Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06soc/amd/stoneyridge: Add API to initialize non-early_init i2c busesDaniel Kurtz
Provide a method for initializing i2c buses that are not marked as early_init in the device tree. These i2c buses can be enabled in a mainboard's ramstage, for example. BUG=b:69407112 TEST=Boot depthcharge w/ CLI enabled on grunt. devbeep => plays beep BRANCH=None Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06soc/intel/skylake: Set PsysPmax valueGaggery Tsai
According to doc #543977 Power Architecture Guide, PsysPmax is the maximum platform power. It maps to the full-scale of Psys signal. This patch adds a "psys_pmax" member in chip information which allows boards to set up maximum platform power. BUG=b:71594855 BRANCH=None TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure correct PsysPmax value is passed to FSP-S through UPD. Verfied on KBL-R and KBL-U SKUs. Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06mb/google/fizz: Determine PsysPl3 and Pl4 valuesShelley Chen
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid brownouts. According to Intel doc #560604, page 74, the max time window is 64ms (code=6) and the min duty cycle we can set is 4%. BUG=b:71594855 BRANCH=None TEST=Boot to OS and check MSRs using iotools for expected values Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06mb/google/nautilus: Work around the power issue of MIPI and USB camerasAndy Yeh
On EVT, the USB and MIPI cameras share the same power source. As a result, when the MIPI camera driver turns off the camera once probed, USB camera will be disconnected. To make USB camera work on EVT devices, we will need a hack in coreboot to leave the camera power always-on. BUG=b:72839352 TEST: Verified the MIPI and USB camera function on DUT board TODO: This power issue will be fixed on DVT build. Will revert this patch once confirmed power sources for MIPI and USB camera could be supplied individually. Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Reviewed-on: https://review.coreboot.org/23546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andy Yeh
2018-02-05mb/google/fizz: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails, it falls back to GPIO pins. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05ec/google: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch adds EC_CMD_GET_CROS_BOARD_INFO and two APIs to fetch OEM ID and SKU ID from cros EC. CBI abbreviates Cros Board Info. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: Iff69a2dc0e562d87dd287f79c407f23aeb09fb9e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05mb/intel/glkrvp: Set S0ix lazy wake maskShamile Khan
Enable S0ix wake mask programming from coreboot using unified host event programming interface. BRANCH=none BUG=none TEST=Verify masks with ec hostevent command on S0, S3, S5 and S0ix. Also check that lidclose/lidopen command from EC console wakes system up from S3 or S0ix. Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23453 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: Fix instabilityRichard Spiegel
A file that has several methods cannot be included inside a method. It has to be included inside a scope, but not inside a method or it'll cause problems (instability). There is an ugly construction in method _INI. It's needed because if AmdImc is not included then the call to ITZE would break the build. BUG=b:62200858 TEST=Build kahlee. Change-Id: If6c877df5a87df1b348de92868b91eed4a76de55 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-05Update blobs submodule to upstream masterMarc Jones
Updating from commit id a5efee5: 2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs) to commit id 19dea8d: 2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9) This brings in 2 new commits. Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23562 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-02-05google/lars: Turn on keyboard backlight in romstageJenny TC
Cherry-pick from Chromium: a60ac10 [Lars: Turn on keyboard backlight in romstage] Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. TEST=boot on Lars and see keyboard backlight come on early Original-Change-Id: I4fede6cff85f4487cedfbccf6cc24c6380d905e0 Original-Signed-off-by: Jenny TC <jenny.tc@intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I4b1fed10d9bd1ae1b265e848417836f816f252f3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Update GPIO mappingdavid
Combination of several commits from Chromium tree: 949037c [Lars: coreboot GPIO changes for EVT] c286789 [Lars: Set USB Type A current limit to 2A] 0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low] 4a0650d [Lili: Support touchscreen] Disable unused GPIOs based on schematic and adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK. Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A charging from the USB Type-A port. GPP_F_23 is set to NC currently and is floating, causing the on-board speaker to have no audio or the audio has noise; set to output/low. These commits bring lars' GPIO mapping in line with the Chromium tree. Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397 Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com> Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com> Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Update the MAINBOARD_FAMILY string in KconfigDuncan Laurie
Cherry-pick from Chromium: 99cd8f8 [lars: Update the MAINBOARD_FAMILY string in Kconfig] This string was left at the default for kunimitsu and should be updated to indicate the proper mainboard. Original-Change-Id: Icc0e162d57242e7b0610fb570ef1a8a45ee16e4f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4b70227c8cfdfe939e40ea6258d494337a2907b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Update SPD DataMatt DeVillier
Combination of several commits from Chromium tree: 3b875a2 [Lars: Update Memory ID for DVT board] b6d7c63 [Lili: Update Memory IDs] f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD] a6571bf [Lili: Update Memory IDs] 80e1841 [Lili: Update Memory IDs] 58d4487 [Lili: Fix memory string show error in spd data] These commits bring lars' SPD data in line with the Chromium tree. Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084 Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39 Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991 Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Add sdmode-delay property for max98357aMatt DeVillier
Adapted from Chromium commit: af3ec09 [Lars: Add sdmode-delay device property for maxim98357a] Add "sdmode-delay" as a device property for the maxim98357a codec. This speaker amp requires both SFRM & BCLK to active and stable before it is unmuted. If there is a BCLK and no SFRM, that results in a pop noise. Adding a configurable delay parameter for all Skylake platforms to allow sufficient time for the BCLK & SFRM on I2S to be stable before the amp unmutes itself to avoid a pop noise at the start of playback. Setting the delay to 5ms since the observed delay between SFRM and unmuting of the amp is around 2ms. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: update device properties for Nuvoton codecMatt DeVillier
Adapted from Chromium commit: 848ee3a [Lars: Add device properties for Nuvoton codec] Update sar-threshold, sar-compare-time, sar-sampling-time properties to match values in lars' Chromium branch. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars,lili: Set new thermal parametersdavid
Cherry-pick from Chromium: 55c0eb3 [Lili: Set new thermal parameters] Set new parameters of DPTF for both Lars and Lili. The acoustic will have higher 1.6dB in transition mode, when using Lili fan table on Lars. Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05google/lars: Update DPTF settingdavid
Cherry-pick from Chromium: dff141b [Lars: Update DPTF setting] Original-Change-Id: I1f2686eced07c7fb1bde3c660df6d6efac607695 Original-Signed-off-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3e844688588b6d1c69459f75c0d7da93ba3688 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05soc/intel/skylake: Set PsysPl3 and Pl4Shelley Chen
If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-02-05soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config spaceHannah Williams
read_resources in common/block/pmc/pmc.c is corrupting the BAR at offset 0x20. pch_pmc_read_resources | pci_dev_read_resources | pci_get_resource Within pci_get_resource, the BAR is read and written back. Since read of ACPI BAR does not return the correct value, the subsequent write corrupts the BAR. Hence re-programming the BAR. Also, reading PMC STATUSCOMMAND register does not return bit 0 correctly in pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled. Hence making sure IO ACCESS gets enabled by setting dev->command TEST=Can boot to OS Without this change coreboot will be stuck at "Disabling ACPI via APMC:" Change-Id: I27062419d06127951ecbbb641835d06ca39ff435 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05mb/google/kahlee: Enable wlan card so it can be detectedMartin Roth
The wifi card was not being powered, and was being held in reset during PCI enumeration, so it was not being brought up. BUG=b:72738963 TEST=Verify wlan card shows up in lspci Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23552 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05coreboot_tables: Document coreboot framebufferNico Huber
A discussion around the `bytes_per_line` field (it was ignored in CorebootPayloadPkg for some reason) made the lack of documentation obvious. Change-Id: I5e1343b5fe37ac106e61e6907fbcc1737ac56f8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-05soc/intel/apollolake: Clear RTC failure bit after reading itFurquan Shaikh
This change ensures that the RTC failure bit is cleared in PMCON1 after cmos_init checks for it. Before this change, RPS was cleared in dev init phase. If any reboot occurred before dev init stage (e.g. FSP reset) then RPS won't be cleared and cmos_init will re-initialize CMOS data. This resulted in any information like VBNV flags stored in CMOS after first cmos_init to be lost. BUG=b:72879807 BRANCH=coral TEST=Verified that recovery request is preserved when recovery is requested without battery on coral. Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-02arm64: Pass COREBOOT flag to ARM TF, always enable loggingJulius Werner
This patch changes the way coreboot builds ARM TF to pass the new COREBOOT flag introduced with the following pull request: https://github.com/ARM-software/arm-trusted-firmware/pull/1193 Since the new coreboot support code supports the CBMEM console, we need to always enable LOG_LEVEL INFO. Supporting platforms will parse the coreboot table to conditionally enable the serial console only if it was enabled in coreboot as well. Also remove explicit cache flushes of some BL31 parameters. Turns out we never really needed these because we already flush the whole cache when disabling the MMU, and we were already not doing it for most parameters. Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02rockchip/rk3399: Pass coreboot table pointer to ARM TFJulius Werner
This patch passes the coreboot table base address to ARM TF on RK3399 devices to be able to use the new coreboot table parsing support. Change-Id: I5cb2f13ce71e374207d0fa7a71c38852d680dc56 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23557 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02rockchip: Correct UART reference clock valueJulius Werner
The Rockchip UARTs are tied directly to the 24MHz oscillator and are thus clocked with exactly 24MHz. The reasons why our code instead uses some 23.xxMHz value have long been lost in time. For the current shared 8250 implementation, the baud rate divisor for 115200 would be the same. Correcting this does make the information in the coreboot table more accurate and help payloads chose a better divisor, though. Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02rockchip/rk3288: Fix includes for <soc/clock.h>Julius Werner
This header uses common types and macros so it needs to include the headers that provide those itself. Change-Id: Ieceb0deadbeef8ddbbb00b13542b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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