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2013-09-10intel/i82801ix: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-10intel/gm45: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO for all boards with gm45 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3600 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06libpayload: Set heap's header size to 64-bitNico Huber
For libpayload clients with larger memory needs (eg. FILO with integrated flashrom) the current configuration isn't enough. Change-Id: Ic82d6477c53da62a1325400f2e596d7d557d5d1e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3889 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2013-09-06libpayload: Make heap code independent of its header sizeNico Huber
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Change-Id: Ie69ceb343494b7dd309847b7d606cb47925f68b6 Reviewed-on: http://review.coreboot.org/3888 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-06usbdebug: Fixes for LynxPoint LPKyösti Mälkki
Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Use CAR migrationKyösti Mälkki
If we already initialized EHCI controller and USB device in romstage, locate active configuration from salvaged CAR_GLOBAL and avoid doing the hardware initialisation again. Change-Id: I7cb3a359488b25abc9de49c96c0197f6563a4a2c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3476 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Dump low-level protocol detailsKyösti Mälkki
Dumping these EHCI host controller registers is useful to solve problems with debug devices. Change-Id: I0610cecca57b1b952d4f87211dd00c8c0bc398b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3866 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Adjust endpoint retry timeoutsKyösti Mälkki
Change Setup Stage of control messages to have no retries, while data and status stages may retry until timing out after 1000 retries. The correct amount of retries might vary by endpoint and device dongle used, so make it a variable. Change-Id: I63313f994d0bd3444a3aab527ca942da5de9e6fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3882 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06usbdebug: Adjust transaction retriesKyösti Mälkki
Transaction consistently completes with 80 to 150 status reads on my setups. Hardware should always be able to complete this within 125us as the debug port is serviced at the beginning of each microframe. Timeout is set to DBGP_MICROFRAME_TIMEOUT_LOOPS=1000 status reads. Do not retry transactions if this timeout is reached as the host controller probably needs full re-initialisation to recover. If this timeout is not reached, but a transaction is corrupted on the wire, or it is otherwise not properly delivered to the USB device, transaction is retried upto DBGP_MICROFRAME_RETRIES=10 times. Change-Id: I44bc0a1bd194cdb5a2c13d5b81fc39bc568ae054 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3881 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-03libpayload: reduce libcbfs verbosityPatrick Georgi
Prettier in real-world payloads (ie. FILO) Change-Id: I9ed968fe527c5d46090e707e2d89b7406a43662e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3887 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-31Add Kconfig options for Linux as payloadPatrick Georgi
These allow to define a kernel image, initrd and command line. Change-Id: I40155b812728a176b6d15871e1e6c96e4ad693c8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3893 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-08-31Remove NRV2B compression supportPatrick Georgi
It wasn't even hooked up to the build system anymore. Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3892 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-08-31Add a (b)zImage parser to cbfstoolPatrick Georgi
In the great tradition of LinuxBIOS this allows adding a kernel as payload. add-payload is extended to also allow adding an initial ramdisk (-I filename) and a command line (-C console=ttyS0). Change-Id: Iaca499a98b0adf0134e78d6bf020b6531a626aaa Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3302 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-29usbdebug: Fix control messagesKyösti Mälkki
Add support for control messages with a write of data stage. Add status stage after a read of non-zero length data stage. Do not retry control message if device responds with STALL. Change-Id: I16fb9ae39630b975af5461b63d050b9adaccef0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3867 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Use separate data toggle for each pipeKyösti Mälkki
USB defines a mechanism to detect certain cases of lost handshakes using an alternating data sequence number, referred to as data toggling. This patch fixes each pipe to have its own tracking of the data toggle state. Change-Id: I62420bdaeadd0842da3189428a37eeb10c646900 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Reference endpoints by pipes in callsKyösti Mälkki
Add allocation for endpoint0 as a pipe for control messages. Endpoint number was already stored in the pipe object, place devnum there too, although all pipes will use same devnum==127. Change-Id: I299d139bdd8083af8b04a694e8e41435ec026a25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29intel usbdebug: Add choice of EHCI controllerKyösti Mälkki
Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Support choice of EHCI controllerKyösti Mälkki
Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Change debug port scanningKyösti Mälkki
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29kontron/ktqm77: Allow disabling onboard NICsPatrick Georgi
Two new nvram variables control disabling the two non-ME NICs on the mainboard. This is implemented by disabling their PCIe bridge. Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3870 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-29lenovo/x60/romstage.c: Collect timestamps in romstagePaul Menzel
Collect early timestamps in Lenovo X60’s romstage. Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then doing `cbmem --timestamps` should output the timestamps. Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3587 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-08-29Sandybridge/Ivybridge: Unify and fix Kconfig defaultsStefan Reinauer
Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28kontron/ktqm77: Drop MRC_FILE definitionPatrick Georgi
The northbridge defines it already and to the same value. Change-Id: Ia5d856258fac52ea0b249142f70a89123ca04f82 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3876 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28Fix up Stumpy/Lumpy PEI data for system agent r6Stefan Reinauer
Change-Id: I79937fd1671af23184ab830d5ba6242c8067d944 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-27ASRock IMB-A180: Add CODEC initialization tableBruce Griffith
Change-Id: Ic4d191bd34179af707449a15026079da1412ed60 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3886 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2013-08-27Locate the generated iasl in acpica-unix-20130626Zheng Bao
acpica-unix-20130626 doesn't use bin32 and bin64 to save the objects any more. Change-Id: I419ecc987e2adcd860a8ad1bf2f6b5c4dd40fd8a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-27ASRock IMB-A180: Add new AMD Embedded G-Series SOC mainboardWANG Siyuan
Tested on Ubuntu 12.10. S3 is supported. No HD Audio. Mainboard details: http://www.asrock.com/ipc/overview.asp?Model=IMB-A180 Change-Id: I75254194ab5da8e5c61383d8f85aa4e300815637 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3880 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-27AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in YangtzeWANG Siyuan
src/southbridge/amd/agesa/hudson/Kconfig config default value, mainboard Kconfig config value for specific mainboard. bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3 Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3879 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-26libpayload: Add a few more PCI constantsStefan Tauner
flashrom has started to use revision IDs to distinguish AMD chipsets and fails (even more) to build with libpayload since then because PCI_REVISION_ID is undefined in libpayload's pci header. Change-Id: If7440a48c1005a4ba4fc09303f47cdfa9f408ad1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3884 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-08-24usbdebug: Change reference to EHCI BARKyösti Mälkki
Change the defines, as follow-up patch will replace use of constant CONFIG_EHCI_BAR. Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3875 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24Add test to match struct device with pci_devfn_tKyösti Mälkki
Add a function to test if pci_devfn_t matches with a device instance of struct device, by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3474 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24Add pnp_devfn_t and use with __SIMPLE_DEVICE__Kyösti Mälkki
Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PNP access functions for ramstage using the inlined functions from romstage. Change-Id: I2a0bd8194acaf9c4c7252a29376eec363397e3a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3871 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24Add pci_devfn_t and use with __SIMPLE_DEVICE__Kyösti Mälkki
Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24usbdebug: Only test two possible USB device numbersKyösti Mälkki
After an USB device sees USB bus reset on the bus, it will reset to device number 0. Per the EHCI debug port specification, a debug dongle device may reset to the fixed debug device number of 127 instead. Thus there is no need to try device numbers from 1 to 126. Do a sanity-check on a returned debug descriptor as I experienced some USB flash memory to respond on this request with zero-fill data. Change-Id: I78d58f3dc049cd8c20c6e2aa3a4207ad7e6a6d33 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3861 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-23usbdebug: Halt host controller before resetting itKyösti Mälkki
Resetting an EHCI controller when it is not halted can have undefined behaviour. This mostly fixes a case where calling usbdebug_init() twice would fail to reset the USB dongle device properly. On amd/persimmon it still requires one extra retry, but at least it is now possible to have usbdebug enabled for both romstage and ramstage. Change-Id: Ib0e6e5a0167404f68af2edf112306fdb8def0be9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3862 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-08-23SPI: Support STMicro partial page writeKyösti Mälkki
Ported from spi/winbond.c. Fixes this error: ICH SPI: Too much to write. Does your SPI chip driver use CONTROLLER_PAGE_LIMIT? Change-Id: I50db8fd1104d3b7d319b278b14f97e3ff9cb6404 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3877 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-08-23usbdebug: Do not support logging from SMMKyösti Mälkki
Letting SMI handler touch EHCI controller is an excellent source of USB problems. Remove usbdebug entirely from SMM. It may be possible to make usbdebug console work from SMM after hard work and coordination with payloads and even OS drivers. But we are not there. Change-Id: Id50586758ee06e8d76e682dc6f64f756ab5b79f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3858 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-08-23usbdebug: Add compatibility quirk for FX2Kyösti Mälkki
This quirk is needed with a DIY debug dongle using obsolete CY7C68013 (aka FX2) USB chips. Old revision of chip requires a SET_CONFIGURATION to be sent, while this is not required in EHCI debug port specs. Change-Id: I4926eb19b7e991d6efeef782682756571ad006b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3386 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-08-23usbdebug: Block recursive calls of printkKyösti Mälkki
When we create low-level debugging of EHCI controller registers, we call printk() within printk(). In ramstage this would leave us with deadlock waiting on the console spinlock. Change-Id: Idbe029af9af76de27094bb2964c60d9ccfdd96e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3860 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-23usbdebug: Add logging level to debuggingKyösti Mälkki
Increase existing level from DEBUG to INFO. Change-Id: Ic5934aec449f921af96dd3a6524f7275f8de1304 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3859 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-19Don't include LZMA in romstage if ramstage is not compressed.Andrew Wu
If ramstage is not compressed, the CBFS module in romstage doesn't need to support LZMA. Removing the LZMA module in this case can save about 3000 bytes in romstage. Change-Id: Id6f7869e32979080e2985c07029edcb39eee9106 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3878 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16AMD Southbridge CS5536: make use of #include <device/smbus_def.h>Christian Gmeiner
Change-Id: Ia2dff49d3e2b086546785d992f2d92bcf4d1ef1c Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16AMD AGESA: Remove INVD instruction when transitioning from CARBruce Griffith
The AMD AGESA function to move the stack from cache-as-ram to actual RAM doesn't need any help. The current implementation has an INVD instruction just before cache-as-RAM is torn down. It isn't needed for Trinity processors and makes Kabini boot unreliable. Change-Id: Ibe9e4105eee032471ccbb2d537471d5fa5847d22 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3852 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-16kontron/ktqm77: Update MRC pathPatrick Georgi
It still pointed to the old binary despite implementing the newer interface Change-Id: Iebd5dae98168f5568f3ad6a18c5ebde9abc3ece0 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3869 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16emulation/qemu-i440fx: style cleanupPatrick Georgi
Drop unused and commented out variable, and fix a comment while at it. Change-Id: I1bd7d10aca949c8579433ea1c91264fd816a3fb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3873 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-16Fix lint-stable targetPatrick Georgi
SEABIOS_PS2_TIMEOUT needs a default, otherwise the "allyesconfig" target hangs in an endless loop. The given default is correctly overridden by the (currently sole) user, the lenovo/x60 target. Change-Id: I3f5e347c29ccbb4d711a489d067b6c909f030bd0 Reported-by: Kyösti Mälkki Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3874 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2013-08-16console: Squelch console output from AP CPUs in romstageKyösti Mälkki
Add Kconfig option SQUELCH_EARLY_SMP and have it enabled by default. Console drivers have unpredictable results if multiple threads attempt to share same resources without spinlock. Serial UARTs have not had huge problems, only distorted output, but those relying on cache-as-ram (CBMEM and usbdebug) may require this. Change-Id: I7f406fdea7b6dc6a341c4da2fab56f7b7ff568b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3854 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-15w83627hf/acpi: Move floppy drive enumeration from _INI into _FDE.Christoph Grenz
Move the floppy drive enumeration from _INI() and PROB(), which stored the enumeration results into _FDE into _FDE(). _INI is called by any ACPI-capable OS on boot while _FDE is rarely used. So it's better to run the enumeration when requested rather than unconditionally. Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15w83627hf/acpi: Make `AddressMax` a multiple of `AddressAlignment`Christoph Grenz
The parallel port of the W83627HF can be configured on any port between 0x100 and 0xFFC with 4 byte alignment for traditional modes and 8 byte alignment for EPP mode. As the ACPI specification says that the maximum acceptable starting address has to be a multiple of the alignment granularity, correct the maximum starting address from 0xFFC to 0xFF8. Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/2942 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variablePeter Stuge
This allows mainboards to preconfigure a ps2-keyboard-spinup timeout when SeaBIOS is chosen as the payload. The Kconfig option can be changed manually if CONFIG_EXPERT is set. Change-Id: I5732b18ef04f4bdef6236f35039656ad02011aec Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3734 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15cbfstool: Add an add-int command that adds a raw 64-bit integer CBFS filePeter Stuge
This simplifies storing SeaBIOS parameters in CBFS. Change-Id: I301644ba0d7a9cb5917c37a3b4ceddfa59e34e77 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15qemu: fix ioapic reservationGerd Hoffmann
The slightly hackish ioapic ressource reservation is needed for i440fx emulation only, for q35 the ich9 southbridge driver handles this just fine. [ Side note: The i440fx chipset emulated by qemu is pimped up with alot of stuff which never existed on real hardware, which leads to tweaks like this one. ] Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VDRudolf Marek
Use the same HD Audio [1] verb table for the Realtek ALC887-VD audio chip as the one set up by the proprietary vendor BIOS. Linux’ ALSA exposes this pin configuration under the virtual filesystem sysfs. /sys/class/sound/hwC1D0/init_pin_configs The script `alsa-info.sh` [2][3] is able to decode the table. Only one channel audio playback (rear connectors) is tested [4], which worked already before. [1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html [3] http://alsa-project.org/main/index.php/Help_To_Debug [4] http://review.coreboot.org/#/c/3170/2//COMMIT_MSG Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-15AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`Paul Menzel
The board name in that variable name is not necessary, as it is not board dependent, that means using the file as a template for making a new coreboot port for another motherboard the variable does not need to be changed, and just increases the code differences between AMD Parmer, AMD Thather and ASUS F2A85-M. So use a generic name. The same was done for AMD Persimmon (and inherited by the LiPPERT FrontRunner/Toucan-AF) in the following commit. commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt Reviewed-on: http://review.coreboot.org/2529 The board name is *not* removed from the `CODEC_ENTRY` variable name as the verb table not only depends on the codec but also on the board [1]. Having the board name in the variable name is a good indicator that the pin configuration needs to be adapted when taking this file as a template for a new port. If it was board independent, a default chip configuration could be used and shared between all boards, which is unfortunately not the case. [1] Unfortunately I was not able to find Jens’ comment in my mail archive and in the Gerrit Web interface. Not sure where it is, but I am sure he made that comment. Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15w83627hf/acpi: Fix logical device power down in ACPIChristoph Grenz
As Nico noticed for the W83627DHG, the power management bits to power down individual logical devices on Winbond superios are named counterintuitively and need to be set when the logical device should be powered. This corrects the power management methods for the W83627HF. Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3605 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15CBFS: Change how the bss is zeroed when loading a stage.Gabe Black
For reasons explained in a previous CL, it might be necessary to "load" a file from CBFS in place. The loading code in CBFS was, however, zeroing the area of memory the stage was about to be loaded into. When the CBFS data is located elsewhere this works fine, but when it isn't you end up clobbering the data you're trying to load. Also, there's no reason to zero memory we're about to load something into or have just loaded something into. This change makes it so that we only zero out the portion of the memory between what was loaded/decompressed and the final size of the stage in memory. Change-Id: If34df16bd74b2969583e11ef6a26eb4065842f57 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3579 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15CBFS: Change the signature of cbfs_decompress.Gabe Black
Instead of returning 0 on success and -1 on error, return the decompressed size of the data on success and 0 on error. The decompressed size is useful information to have that was being thrown away in that function. Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15lenovo/t60 lenovo/x60: Default SEABIOS_PS2_TIMEOUT to 3 secondsPeter Stuge
The ThinkPad keyboard controller sometimes needs a while in order to initialize, so let's ask SeaBIOS to wait for it. This change ensures that the internal keyboard always functions correctly on the ThinkPad when coreboot is built with SeaBIOS as payload. Change-Id: I562475ec98b0c1f5d0debf6e9b597748a420f068 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-15qemu: reserve portsGerd Hoffmann
QEMU has a bunch of non-standard virtual devices on various I/O ports. Allocate resources for them so the coreboot resource management knows those ports are used. Change-Id: I51a85967cf2dcd634b0c883210bb52c0c34c8283 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15AMD Richland: Add new graphics device IDs to Family 15, Models 10-1FBruce Griffith
Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3857 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-15AMD Fam16: Add OSC method to PCI0Mike Loptien
The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices. During Linux boot, an error is logged to dmesg if _OSC is not found. Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15AMD Fam16: Add secondary bus number to CRES methodMike Loptien
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the AMD FCH ACPI code. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3822 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15AMD Kabini: Split DSDT into common sectionsMike Loptien
Split the Family16 (Kabini) DSDT file into logical regions. Olive Hill is the only mainboard and Kabini is the only NB/CPU currently using Family16 AGESA code. Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3821 Tested-by: build bot (Jenkins)
2013-08-13dmp/vortex86ex: Initialize Reatek ALC262 audio codecAndrew Wu
Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone did not work. With the new logic it does. Now line-in,line-out and microphone all work. The verb data table is generated by Realtek. Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3855 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-13Add a generic Intel HD audio (Azalia) module azalia_device.cAndrew Wu
This module uses cim_verb_data to detect and initialize HD audio codecs. The module source code is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c. Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3844 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-13Fix some wait_for_valid functions return value from 1 to -1.Andrew Wu
codec_init expects wait_for_valid returns -1 for timeout, not 1. Change-Id: I0f2a3ebb1934d0adaf13765434526bbc9efca9a3 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3843 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-10usbdebug: Add option for verbose logging of connectionKyösti Mälkki
Add option to log changes in USB 2.0 EHCI debug port connection. For romstage move usbdebug as the last initialised console so one actually can see these messages. Init order of consoles in ramstage is undetermined and unchanged. Change-Id: I3aceec8a93064bd952886839569e9f5beb6c5720 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3387 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-10usbdebug: Fix AMD cimx/sb700 cimx/sb800Kyösti Mälkki
These Kconfig entries were forgotten from the commit that re-enabled usbdebug for these southbridges. Change-Id: Ia17f1dd3340408da7c033c2c949404d2636bed44 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3849 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-09intel/sandybridge intel/bd82x6x: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3810 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-08ASUS F2A85-M: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the F2A85-M DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the F2A85-M dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for F2A85-M. Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3805 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-08AMD Thatcher: Split DSDT into common sections (as per Parmer)Kimarie Hoot
Rearranged the Thatcher DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the Thatcher dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Thatcher. Change-Id: Ie44a32959cc547840914365e872416d4624d33df Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/3804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-07usbdebug: Support AMD cimx/sb700 cimx/sb800 once againKyösti Mälkki
Support code for sb700 and sb800 existed already, but Kconfig and compile-time issues prevented from enabling USBDEBUG for boards with the affected AMD southbridges. Change-Id: I49e955fcc6e54927320b9dc7f62ea00c55c3cedf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-07usbdebug: Use __SIMPLE_DEVICE__ on early enableKyösti Mälkki
With USBDEBUG selected, the file is built for both romstage and ramstage. For the ramstage build, we need to explicitly use the simple PCI config operations without devicetree. Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-07Make EARLY_CONSOLE optionalKyösti Mälkki
This change brings back the possibility to disable console output while in romstage, like before commit d2f45c65. For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM CONSOLE do not work correctly for romstage due the way cache-as-ram is set up, but might already work for ramstage. Change-Id: Id8d830e02a18129af419d3b5860866acf315d531 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3846 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-06AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER`Paul Menzel
Copied from a similar commit for Family 10h AGESA [1] Remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments [2] fc47bfa Revert "AMD f14 vendorcode: Fix warning" Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD AGESA: Add missing breaks to switch statement in one fileBruce Griffith
This is the same patch as an earlier one applied to family 15 [1]. Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". [1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ... Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)Bruce Griffith
Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-06AMD Olive Hill: Change SB800 references to YangtzeBruce Griffith
Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3815 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Add HUDSON_LEGACY_FREE flagBruce Griffith
Olive Hill does not have a Super I/O or keyboard controller. Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Olive Hill: Remove default VBIOS vendor/device IDBruce Griffith
The VBIOS device ID is set by processor family using the map_oprom_vendev() function in the northbridge code. There is rarely a reason why this should be overridden by the mainboard. Since Kabini includes a default VBIOS vendor/device ID in the northbridge Kconfig code, remove the setting from the Olive Hill mainboard settings. Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3816 Tested-by: build bot (Jenkins)
2013-08-06AMD Kabini: Add "const" modifier to AGESA function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. This same change was made for AMD Trinity APUs (Family15tn) [1]. [1] 283ba78 AGESA: Add "const" modifier to function parameters Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3837 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-05AMD SATA: Correct "them implement" to "then implement" in commentsPaul Menzel
This changelist was cherry-picked from merged community code for Parmer [1] and the paths modified so that the Parmer modification is applied against Olive Hill. [1] 0086162 AMD SATA: Correct _them implement_ ... in comments Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3841 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-05AMD Kabini: Add map_oprom() function for Vendor/Device IDsBruce Griffith
Change-Id: I14285f0677003fbf8b9b112207af202658807894 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Enable HDMI audio setting in build optionsBruce Griffith
Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3814 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Eliminate unnecessary memory copyBruce Griffith
Eliminate an unnecessary copy of the DDI descriptor list and the PCIe port descriptor list. As descriptor tables, these tables do not need dynamic updating and should be used from ROM without runtime copying. There will be a corresponding patch for AGESA that adds CONST modifiers to function parameters that are pass-by-reference "IN" values (read-only pointers). Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3818 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Olive Hill: Add new AMD mainboard using Kabini processorSiyuan Wang
Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Hudson/Yangtze: Enable support for SATA port multipliersBruce Griffith
This patch sets a bit in the Yangtze southbridge to enable the extra protocol necessary to handle port multiplier chips. This has been turned on during most of Kabini development without any notable impact. Olive Hill has an optional daughter board that incorporates Silicon Image Steel Vines chips. This change has been tested with and without the daughter board. This change can be regression tested using any Hudson-based motherboard, although it has no impact on boards with discreet Hudson/Bolton southbridges. This was tested for impact on SATA performance in the absence of a port multiplier using the IOZone benchmarks within the Phoronix Test Suite. A SATA 3 hard drive (6.0 Gbps) and an SSD were connected to the ports on Olive Hill without using the port multiplier card. The test results contained more run-to-run variation within the same configuration than was seen in the aggregate results comparing the interface with and without the port multiplier protocol additions. In other words, the test had less accuracy than the impact caused by turning on port multiplier support. Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3808 Tested-by: build bot (Jenkins)
2013-08-05AMD Kabini: Modify Hudson southbridge to support new AMD processorSiyuan Wang
Yangtze uses Hudson AGESA wrapper code but has some changes. The changes are necessary and have no effects on Hudson. Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)Siyuan Wang
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also changed because these two files depend on F16kb northbridge macros Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05AMD Kabini: Add CPU AGESA wrapper for new AMD processor familySiyuan Wang
Change-Id: I4a1d2118aeb2895f3c2acea5e792fbd69c855156 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-04AMD Kabini: Add AGESA/PI code for new processor familySiyuan Wang
Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Nick Dill <nick.dill@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3836 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-02Remove unnecessary space characters.Andrew Wu
Change-Id: I4ed9329126b216eb4ae58355672603ce79a6d4ef Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3847 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-01intel/lynxpoint: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I71923790aa03e51db01ae3a4745e1c44556d281f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3812 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-01Add directive __SIMPLE_DEVICE__Kyösti Mälkki
The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3555 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-31Drop unused EXTERNAL_MRC_BLOBStefan Reinauer
The Kconfig variable EXTERNAL_MRC_BLOB is not used. Drop it. Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3829 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-30Makefile: Fix adding intel/commonKyösti Mälkki
Directory intel/common must be conditionally added in the list of source directories, as the parent directory southbridge/intel is unconditionally added even for boards without such device. Change-Id: I7088bc6db9f56909ffa996aa7eff76cd72e177eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3827 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-30usbdebug: Fix missing includeKyösti Mälkki
Change-Id: I74d28c13e6597c56e3b85ccd2b83386b86c200f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3828 Tested-by: build bot (Jenkins)
2013-07-30cpu/intel/model_67x: Add missing includeKyösti Mälkki
The added device.h file was indirectly picked from cpu.h, which will have this include removed in a follow-up patch. Change-Id: Ifc0a4800de3b1ef220ab1034934f583be8c527b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3826 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:51:57 +0000