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PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating
error status registered (such as MCA MSRs) to list fatal errors happened
during the previous boot session.
The header file supports 3 different error source types. CPX-SP FSP
supports only McBankType.
Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Remove copyright notices and add authors to AUTHORS
- Use SPDX license identifiers for all files
- Add coreinfo to the license header lint
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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GPP_E12 should not be defined in the baseboard as its use is
determined by the variant. For legacy reasons, we still have GPP_E12
defined in early_gpio but should not. Malefor and volteer* have the
same GPP_E12 definition, but that is a misconfiguration. I think that
was a copy-paste that slipped through the reviews.
BUG=b:157597158
TEST=volteer2 boots to the OS
Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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1. Set tcc offset to 5 degree celsius
2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Clean up the DPTF section of the baseboard devicetree; this makes
overrides simpler, as not necessarily all of the fields need to be
overridden.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.
BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system
Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.
Bug=None
Branch=None
Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.
Found-by: Coverity CID 1432491
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable EC software sync for terrador and todor
BUG=None
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Selects Cache QoS mask MSR programming flow for Tigerlake SoC.
BUG=b:145958015
TEST= Build and boot to Chrome OS on TGL-UP3 RVP.
Recipe used:
1. Patch https://review.coreboot.org/c/coreboot/+/43494 that
implements calculation of CQOS mask dynamically based on stack
size usage & incorporates Tigerlake SoC specific programming flow.
2. QS Engineering Microcode based on 0x56 Official Microcode with
LLC CQOS change.
3. QS SoC Part
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.
The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.
TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.
Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.
BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
CAR configuration.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The latest debian image needs the python2 package specified instead of
just 'python'. Also add python3 to the builder as we'll probably be
getting python3 scripts before too long.
Change-Id: Iceea3981b1e219141bf06ad0b559cdbf1c98b360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The current realloc() works by freeing the origin buffer, allocating a
new one, and copying the data over. It's true that free() won't touch
the actual memory. However, the alloc() following it will potentially
modify the memory that belongs to the old buffer in order to create a
new free block (right after the newly allocated block). This causes 8
bytes (HDRSIZE) to be overwritten before being copied to the new buffer.
To fix the problem, we must create the header of the new free block
after the data is copied. In this patch, the content of alloc() is split
into two functions:
1. find_free_block(): Find a free block with large enough size, without
touching the memory
2. use_block(): Update the header of the newly allocated block, and
create the header of the new free block right after it
Then, inside realloc(), call memmove() call right after
find_free_block() while before use_block().
BUG=b:165439970
TEST=emerge-puff libpayload
TEST=Puff boots
TEST=Verified realloc() correctly copied data when buffers overlapped
Change-Id: I9418320a26820909144890300ddfb09ec2570f43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The AOAC device number is never negative, so make it unsigned.
BRANCH=zork
Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change is separate from CB:45308 to only have the directly UART-
related changes in this patch train.
BRANCH=zork
Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BRANCH=zork
Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The usual structure of these files is a global enable symbol, usually
followed by an if-block which contains all other dependent symbols.
Use this instead of having a `depends on` line to each symbol. Guard all
symbols, even if they originally were not guarded, since they don't do
anything useful unless the global enable option is selected.
Change-Id: If5347187b07a46192f0063011ab197b5047f555f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id fefcaa65:
vboot: adjust VB2_SECDATA_KERNEL_FLAGS in non-recovery path
to commit id 4bb06cc1:
COIL: Change denylist to blocklist
This brings in 20 new commmits.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Include console/uart.h for the declaration of uart_platform_base instead
of declaring the function in the source file.
Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The UART index is never negative, so make it unsigned and drop the check
for the index to be non-negative.
BRANCH=zork
Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is required for Super I/Os to be able to read the CPU temperature
through PECI.
On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default.
This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL
MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested
workaround is "Do not initialize PECI before processor update is
loaded". Since coreboot performs microcode updates before running this
code it should not cause any trouble. It was tested on a Core 2 Duo
E8400, stepping E0.
PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium
Dual-Core E2160.
See commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 for the same change
on cpu/intel/model_6fx.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ica66ad6da61376f64f9d24de015f84d250327d66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I1e543f8ff701fa20eaaee601ef54f0b056e61909
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ic4f51a59524bacb374d90c5620f810e96d7b8eb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target
Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic7c1b4defa8c65ed739b1cf3861087cd53cd997c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I5eaf33558e14f63045928215d88d2ad2554fdbf2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I2f8d6d9e8b6e84bb6c2b4e73b0fbeca476130d05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The debug statement to print WiFi SAR file can potentially have a NULL
pointer. Also the debug statement does not add much value. Hence remove the
debug statement.
BUG=b:165613510
TEST=Build and boot the drawcia board to OS.
Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Rarely, the driver of one device needs to know about another device
that can be anywhere in the device hierarchy. Current applications
boil down to EEPROMs that store information that is consumed by some
code (e.g. MAC address).
The idea is to give device nodes in the `devicetree.cb` an alias that
can later be used to link it to a device driver's `config` structure.
The driver has to declare a field of type `struct device *`, e.g.
struct some_chip_driver_config {
DEVTREE_CONST struct device *needed_eeprom;
};
In the devicetree, the referenced device gets an alias, e.g.
device i2c 0x50 alias my_eeprom on end
The author of the devicetree is free to choose any alias name that
is unique in the devicetree. Later, when configuring the driver the
alias can be used to link the device with the field of a driver's
config:
chip some/chip/driver
use my_eeprom as needed_eeprom
end
Override devices can add an alias if it does not exist, but cannot
change the alias for a device that already exists.
Alias names are checked for conflicts both in the base tree and in the
override tree.
References are resolved after the tree is parsed so aliases and
references do not need to be in a specific order in the tree.
Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1955390fcceeb42ecb644ac74541b7e9dd25320f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible.
Use tablet mode of fw config to decide to load custom wifi sar or not.
BUG=b:165613510
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable FW_CONFIG and add tablet mode field in devicetree
BUG=b:165613510
TEST=emerge-dedede coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:165613510
TEST=emerge-dedede coreboot
Change-Id: Ic575889fd9b726a710abff78e1ecc8427b668d5d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J.
BUG=b:165611555
TEST=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.
BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork
Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Use one tab instead of 8 spaces at the beginning of the lines added in
commit 39a8040ddc551306d823d52a459fdb5dd717b2fe.
Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Calling espi_open_generic_io_window in espi_open_io_window depends on
the condition in the preceding if statement, so move the command into an
else block to make it more obvious that this is the case.
TEST=Timeless build results in identical image.
Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I82fc362589389081b1b1856524a972b780af9a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The build error `incompatible-pointer-types` occurs while using
`pci_dev_request_bus_master` as part of device ops
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_F14 should be configured to be routed via APIC and not SCI.
BUG=b:162528549
TEST=verified on a volteer2
Signed-off-by: Alex Levin <levinale@google.com>
Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apparently what I thought was lazor-rev2 is actually lazor-rev3 and
nobody is really sure what lazor-rev4 is going to be at this point or
how we proceed from there. What seems to be somewhat agreed upon is that
for now all Lazor revisions use the "old" GPIO mapping and it's not very
clear if that's ever going to change for Lazor, so let's take the
revision restriction out from Lazor for now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.
BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
Build and boot ezkinil
Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This fixes the hex-to-bin conversion command, used to generated binary
SPD files from hexdumps.
An issue that only appeared on one of my systems, where conversion of
'01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03:
for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1
00000000: 01 32 03 .2.
The reason for this was that the syntax in lib/Makefile.inc is wrong,
because the backslash must be escaped due to chaining two printf
commands.
Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bayou and OpenBIOS aren't supported by the coreboot build system
anymore, so remove these mentions.
Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.
Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Dump MADT and IVRS tables. Cross check ioapic entries
in MADT against IVRS.
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot. Do the same
for the northbridge's IOAPIC base address.
Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.
BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sync the UPD definitions with the latest auto-generated files.
Definitions and usage will be updated in a subsequent FSP
Integration Guide.
Cq-Depend: chrome-internal:3247431
BUG=b:167421913, b:166519072, b:159664044
TEST=Boot morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:163789704
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use the 96 character limit for pad macros.
Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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GPIO Driver mode is used for configuration interrupt routing for
external devices through GPI. But there is no point in configuring
this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro
with others that do not set the corresponding bit in the Host Software
Pad Ownership register.
Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h)
hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing
compilation issue.
Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Rename the pch_init function to bootblock_pch_init to
maintain the parity with previous generation SoC code block.
Refer to commit 1201696.
Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch converts inconsistent white space into tab.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.
Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.
Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.
Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.
Changes in V4:
- update gpio config for lazor board.
Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add sn65dsi86 bridge driver to enable the eDP bridge.
Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf
Changes in V1:
- fix the dp lanes using mask
- separate out the refclk and hpd config to init function
Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change adds support for sc7180 dsi interface host programming.
Changes in V1:
- remove dual dsi config code.
- update register access using struct overlays.
- remove dsc config & command mode code.
Changes in V2:
- remove dsi read and write functions.
- remove target and panel related code.
Changes in V3:
- move prototypes to headers.
- define macros for constants.
Changes in V4:
- define register bits instead of hardcoded values.
Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/28014/44
Change-Id: Ia961ee0e30478e21fd786ce464655977449df510
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Nothing uses this code anymore.
Change-Id: I5da1020597c126a40b015beb6e43fb0168aa330f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
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Adds basic headers as well as source required for display
dsi 10nm phy & pll programming.
Changes in V1:
- add struct overlays to model hardware registers.
- remove typedef structures.
- remove dead code such as dual dsi,split config etc.
Changes in V2:
- remove panel related header files.
- update the bitclock calculation using edid parameters.
- add phy timing calculation function.
- update copyright license.
Changes in V3:
- update the mdss clock structure.
- remove dsi_phy_configinfo_type struct.
- remove unused struct fields.
Changes in V4:
- update clock apis.
- remove unused structures.
Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add support for display external clock in coreboot for SC7180.
Tested: Display clocks are configured.
Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Configure GPIO pins as I2S mode for audio speaker.
The audio speaker does not work on Trogdor revision 1, as the
layout was changed.
Developer/Reviewer reference, be aware of this issue:
https://partnerissuetracker.corp.google.com/issues/146533652
Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3
Signed-off-by: vsujithk <vsujithk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Following blobs will includes with SoC makefile:
* AOP
* BOOT
* QTISECLIB
* QCSEC
* QUPV3FW
Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add memory parts and generate DRAM IDs for trondo.
BUG=None
TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2e89ecaf73a30595ed48ac9ce94ccbd4bb7ed3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45164
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the current timeout of 1000 cycles of 100 microsecond would see
timeout occurs on OCP Delta Lake if the log level is set to values
smaller than 8. Because the prink(BIOS_SPEW, ..) in ipmi_kcs_status()
creates delay and avoid the problem, but after setting the log level
to 4 we see some timeout occurs.
The unit is millisecond and the default value is set to 5000 according
to IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater
is recommended.
Tested=On OCP Delta Lake, with log level 4 cannot observe timeout
occurs.
Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory.c to support DDR4 memory types.
Use the new meminit_ddr() and variant_memory_sku() for eldrid variant
code on memory.c
The initial settings override the baseboard from volteer and fine tune
gpio.c and overridetree.cb on eldrid's configuration.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid
can boots. NOTE that tests the ddr4 side of the implementation.
Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Project: https://github.com/9elements/converged-security-suite
License: BSD-3
Tooling for Intel platform security features
Change-Id: I7421b30eb38e64cf6b77b7e1c485c5700728997b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows the AM335X to boot from the coreboot generated MLO by:
- Fixing the load address in the MLO header to be the start of SRAM
- Fixing the way that the bootblock size is calculated (which is
embedded into the MLO so that the MLO knows how much to load into
SRAM). The previous method relied on parsing cbfstool output - the
output has changed format since this was originally written so this no
longer works. Directly using the filesize of the built binary is
probably a more stable way of doing this.
As part of this, the start addresses of SRAM and DRAM were fixed to be
consistent with the AM335x Technical Reference Manual (spruh73, rev Q).
TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card
Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44381
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The console is initialized before mainboard_init, so the peripheral
should be initialized in bootblock_mainboard_early_init rather than
bootblock_mainboard_init.
Change-Id: I9f4ba29798eb0b1efea76f5ade4a234fb35a2f83
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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They are not referenced anywhere.
Change-Id: Iff2d3b0063da5796e0bff1ada08b0a544c3f9a5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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- Fix relative path to spd folder.
- Add spd folder with empty files.
BUG=None
TEST=None
Change-Id: Iae88ff9c8255f60544312f0eeadf1ce617437baf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Allow comments prefixed with '#' in mem_parts_used csv file.
BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments
Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.
Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.
Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This ports Linux commit 71f677a91046599ece96ebab21df956ce909c456
"Handle configuration without P2A bridge".
Quote:
The ast driver configures a window to enable access into BMC
memory space in order to read some configuration registers.
If this window is disabled, which it can be from the BMC side,
the ast driver can't function.
Closing this window is a necessity for security if a machine's
host side and BMC side are controlled by different parties;
i.e. a cloud provider offering machines "bare metal".
P2A stands for primary to AHB.
Tested on Prodrive Hermes, which uses an AST2500. The machine still
boots, has a high resolution framebuffer working in EDK2, and its
boot time has been reduced by 2.5 seconds as it no longer runs into
a timeout due to disabled P2A bridge.
Change-Id: I3293dc35ae89c010154e02eff904ec3a68c96683
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fixes complains about missing INT configuration by the pciexp kernel
modules.
Tested with Linux 5.5 on Prodrive Hermes.
Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do
not define MAX_CPUS, which would then default to 1. Since this is most
likely an oversight, use the same value as other Apollo Lake boards.
To ensure this does not happen again, factor out MAX_CPUS to SoC scope.
Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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APL does not support Hyper-Threading, and has at most four CPU cores.
Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both Gemini Lake boards in the tree use the same value.
Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.
Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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List of changes:
1. Select FSP_HEADER_PATH
2. Select FSP_FD_PATH
3. Select PLATFORM_USES_FSP2_2
4. Select UDK_202005_BINDING
Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Update critical and passive policy for TSR0.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45057
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sushi is not a real product, just a test of the new_variant program.
The effort to keep it up-to-date with the rest of Hatch is no longer
worth it. Remove the variant.
BUG=b:168030592
TEST=build bot is successful, hatch-cq builds successfully
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CB:44774 introduced the non-existent SPD path. This is preventing the
device from booting up.
BUG=b:168053219
TEST=Build and boot drawcia board to OS.
Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL.
Also add NULL terminator at end of pci_device_ids.
Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45140
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCI IDs for Intel's Image Processing Unit (IPU) for ADL.
Also add NULL terminator at end of pci_device_ids.
Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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SMBus code is linked unconditionally since commit 0e3c59e. This change
drops that obsolete part from the help text.
Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Instead of generating hexdumps, output binary SPD files since we plan to
convert all hex SPD files to binary. Also adjust the file extension
where needed.
Test: compared generated binaries with converted binaries from hex files
Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Passing binary SPD files to apcb_edit can lead to an encoding error,
since the files were read in text mode. To fix this, read SPD files
always in binary mode and only decode them, when `--hex` is set.
Tested by comparing output files from the same SPDs in both, binary and
hex mode.
Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested=On OCP Delta Lake, with FSP WW36 dmidecode -t 11 can see the
SPD register vendor ID
String 7: b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000
Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Most of them are needed for SMBIOS type 17 creation.
Tested=With FSP WW36 verified the printed hob values match
with FSP hob data.
Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Support SPI flash dual read funciton which change spi mode (1-1-1)
to dual mode (1-1-2).
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44852
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds NULL check inside get_ifd_version_from_fcba()
function to fix Klocwork issue.
BUG=b:153888802
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Intel CPX-SP FSP ww36 release has following changes:
* Update FSP header version to change among FSP releases.
* Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11
(OEM strings) generation.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To minimize the quirks the kernel has to apply, the headset mic is set
to its correct value in coreboot.
Tested on lemp9, audio is functional.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43631
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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