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2020-10-21mb/google/dedede/variants/drawcia: update PL1 max and min power valuesSumeet R Pawnikar
Update PL1 max and min power values BUG=None BRANCH=None TEST=build and verify on dralat system Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mrc_cache: Remove unnecessary data checksum calculationShelley Chen
When MRC_SAVE_HASH_IN_TPM is selected, we can just use the TPM hash to verify the MRC_CACHE data. Thus, we don't need to calculate the checksum anymore in this case. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I1db4469da49755805b541f50c7ef2f9cdb749425 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20mrc_cache: Add tpm_hash_index field to cache_region structShelley Chen
Pull selection of tpm hash index logic into cache_region struct. This CL also enables the storing of the MRC hash into the TPM NVRAM space for both recovery and non-recovery cases. This will affect all platforms with TPM2 enabled and use the MRC_CACHE driver. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami and lazor Change-Id: I1a744d6f40f062ca3aab6157b3747e6c1f6977f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20security/vboot: Add new TPM NVRAM index MRC_RW_HASH_NV_INDEXShelley Chen
Add new index for MRC_CACHE data in RW. Also update antirollback functions to handle this new index where necessary. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I2de3c23aa56d3b576ca54dbd85c75e5b80199560 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20security/vboot: Make mrc_cache hash functions genericShelley Chen
We need to extend the functionality of the mrc_cache hash functions to work for both recovery and normal mrc_cache data. Updating the API of these functions to pass in an index to identify the hash indices for recovery and normal mode. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I9c0bb25eafc731ca9c7a95113ab940f55997fc0f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driverShelley Chen
This CL would remove these calls from fsp 2.0. Platforms that select MRC_STASH_TO_CBMEM, updating the TPM NVRAM space is moved from romstage (when data stashed to CBMEM) to ramstage (when data is written back to SPI flash. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I3088ca6927c7dbc65386c13e868afa0462086937 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-20mrc_cache: Add config MRC_SAVE_HASH_IN_TPMShelley Chen
Use this config to specify whether we want to save a hash of the MRC_CACHE in the TPM NVRAM space. Replace all uses of FSP2_0_USES_TPM_MRC_HASH with MRC_SAVE_HASH_IN_TPM and remove the FSP2_0_USES_TPM_MRC_HASH config. Note that TPM1 platforms will not select MRC_SAVE_HASH_IN_TPM as none of them use FSP2.0 and have recovery MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic5ffcdba27cb1f09c39c3835029c8d9cc3453af1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20acpi: Skip writing references for disabled devices in Type-C configTim Wawrzynczak
When emitting ACPI tables for the Type-C connector class, skip writing out a device reference if it is to a disabled device. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/45877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()Felix Singer
Clean up ahci_initialize() by using pci_dev struct. Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20cpu/x86/mtrr: add support for address space higher than 16TiBJonathan Zhang
On DeltaLake server, there are following entry in MTRR address space: 0x0000201000000000 - 0x0000201000400000 size 0x00400000 type 0 In this case, the base address (with 4k granularity) cannot be held in uint32_t. This results incorrect MTRR register setup. As the consequence UEFI forum FWTS reports following critical error: Memory range 0x100000000 to 0x183fffffff (System RAM) has incorrect attribute Uncached. Change appropriate variables' data type from uint32_t to uint64_t. Add fls64() to find least significant bit set in a 64-bit word. Add fms64() to find most significant bit set in a 64-bit word. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-10-20libpayload/storage/ahci: Use pacc pointer to read device classFelix Singer
The PCI bus gets already scanned while gathering system information. Therefore, use the pacc pointer from sysinfo_t to read the device class of PCI devices instead of rescanning the bus. Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20libpayload/arch/x86: Introduce pacc pointer in sysinfo_t structFelix Singer
Currently, the PCI bus gets scanned multiple times for various reasons (e.g. to read the device class). Therefore, and in preparation to CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan the PCI bus while gathering system information. Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20payloads/coreinfo: Rename pci_scan_bus()Felix Singer
Rename pci_scan_bus() since the name is already used in libpayload. Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20mb/google/volteer/var/terrador: Configure board specific DPTF parametersDavid Wu
Configure board specific DPTF parameters for terrador and todor BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-20mb/google/volteer/variants/lillipup: add generic SPDsNick Vaccaro
Add generic LPDDR4x SPD support for the following three memory parts: • K4U6E3S4AA-MGCR • H9HCNNNBKMMLXR-NEE • MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-203rdparty/blobs: advance submodule pointerFelix Held
The 3 commits commits from the blob repository this patch pulls in remove executable flags from files in the repo that shouldn't have those flags set: * pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit * Remove execute permission from all binaries * Remove execute permission from plaintext files Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-20cpu/intel/model_{2065x,206ax}: fix AES-NI lockingMichael Niewöhner
MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped, not package-scoped. Thus, move locking from SMM to core init, where the code gets executed once per core. Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20soc/amd/picasso: Use readelf to find bootblock size and locationZheng Bao
The Picasso build describes the DRAM region where the PSP places our bootblock. Rather than relying on Kconfig values, make the build more robust by using the actual size and target base address from the boot block's ELF file. Sample output of "readelf -l bootblock.elf" is: ------------------ Elf file type is EXEC (Executable file) Entry point 0x203fff0 There is 1 program header, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000 Section to Segment mapping: Segment Sections... 00 .text .data .bss .reset ------------------ We can extract the information from here. BUG=b:154957411 TEST=Build & boot on mandolin Change-Id: I5a26047726f897c57325387cb304fddbc73f6504 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20sb/intel/ibexpeak: Align to coreboot's coding styleAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/google/dedede: Add P-sensor for Botenalec.wang
Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/google/dedede: add PEN for Botenalec.wang
Update devicetree of boten that enable stylus BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFSAngel Pons
I often find myself having to increase the CBFS size so that TianoCore fits. Raise the default CBFS size to 2 MiB to alleviate this issue. Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variantBill XIE
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20mb/google/asurada: Init dram in romstageHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20soc/mediatek/mt8192: Do dram fast calibrationHuayang Duan
Load params from flash and use those params to do dram fast calibration. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-20ec/google/chromeec: Add wrappers to get/set the voltageYidi Lin
Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-19soc/intel/cnl: lock AES-NI feature if selectedMichael Niewöhner
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of AES-NI enablement as precaution, as suggested in Intel document 325384-070US. Locking is enabled by default (as already done in SKL and Arrandale) and may be disabled by the newly introduced Kconfig in the parent change. Tested by checking the MSR. Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: add a Kconfig to control AES-NI lockingMichael Niewöhner
Add a Kconfig to be able to disable locking of AES-NI for e.g debugging, testing, ... Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: only lock AES-NI when supportedMichael Niewöhner
Add a check to only lock AES-NI when AES is supported. Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: rework AES-NI lockingMichael Niewöhner
Simplify the AES-NI code by using msr_set and correct the comment. Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu codeMichael Niewöhner
Copy the AES-NI locking function to common cpu code to be able to reuse it. This change only copies the code and adds the MSR header file. Any further rework and later deduplication on the platforms code is done in the follow-up changes. Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19libpayload/storage: Enable STORAGE_64BIT_LBAFelix Singer
32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB capacity. Therefore, enable the 64-bit support. Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19libpayload/storage: Enable all AHCI controllers by defaultFelix Singer
Since the list of tested controllers is not actively maintained, enable all AHCI controllers by default. Also, improve the readability of its help text by adding a comma to it. Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19soc/amd/picasso: Skip SmmInfo to PSP on S3 resumeMarshall Dawson
The PSP does not accept the SmmInfo command during a resume so remove the call. BUG=b:163017485 TEST=Run SST on trembyle, verify error message goes away BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19soc/amd/picasso: Fix typo in SMU argument baseMarshall Dawson
Correct the base address. This should have no noticeable effect, as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The argument writes were not getting to any target. BUG=b:171037051 TEST=Run SST on morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-19mb/siemens/chili: Add Chili variantNico Huber
This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Factsheets/englisch/SINA_Workstation_H_Client_V_Factsheet_EN_Web.pdf Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19soc/rockchip/rk3288/include/soc/display.h: Add missing includesElyes HAOUAS
Change-Id: I3e4824722d3add989a352122b365c2a73f3f703b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macrosElyes HAOUAS
Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19src/soc/samsung: Move common headers to "common/include/soc"Elyes HAOUAS
Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19mb/siemens/chili: Add new mainboardThomas Heijligen
The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up. Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19mb/google/octopus/variants/ampton: Add G2Touch touchscreen supportJames Chao
BUG=b:170703029 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-10-19soc/intel/*: drop useless XTAL shutdown qualification codeMichael Niewöhner
The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is ↵Michael Niewöhner
disabled" This reverts commit e5269a8fd975fa0cba0655cd41f7f8cc99a1feb8. Reason for revert: BIOS spec says, it's recommended to always enable emulation (regardless of the OS version). Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19util/abuild/abuild: Do not check out submodulesAngel Pons
This force-downloads the qc_blobs repository, whose license is then automatically accepted. This may also cause race conditions with git. Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45607 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19Documentation: Fix spelling of *assumptions*Paul Menzel
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19sb/intel/ibexpeak: Use ARRAY_SIZE macroAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46529 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19superio/nuvoton: Factor out equivalent Kconfig optionAngel Pons
There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19superio/nuvoton: Correct NCT6791D COM A mux toggleAngel Pons
Bit 6 of global CR 0x2a toggles the mux for COM B. Bit 7 works just like on the other two Nuvoton Super I/Os, so fold the conditionals together. Change-Id: I8cebe35587ae68cac93ed392342662678621efd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19util/supermicro: Always include commonlib/bsd/compiler.hNico Huber
We rely on `compiler.h` for definitions like `__packed`. Without it, `smcbiosinfo.c` simply declared a global struct with that name, but nothing was packed. Found-by: reproducibility test Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19volteer+vendorcode: Retrieve Cr50 version only via SPIJes Klinke
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.hShelley Chen
As ongoing work for generalizing mrc_cache to be used by all platforms, we are pulling it out from fsp 2.0 and renaming it as mrc_cache_hash_tpm.h in security/vboot. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19soc/intel/skylake: Do not let FSP set the subsystem IDsBenjamin Doron
The subsystem ID registers are read/write-once. Writes by coreboot will not take effect if FSP sets them. Note that FSP sets one device ID for the SA devices and another for PCH devices. coreboot will copy individual vendor and device IDs if subsystem is not provided. Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19soc/intel/cannonlake: Fix memory corruptionsJohn Zhao
Coverity detects source memory is overrun. Fix this issue by using the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption. Found-by: Coverity CID 1429762 1429774 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19soc/intel/common/acpi: correct indentationMichael Niewöhner
Test: built google/volteer with `abuild --timeless` - SHA1 hashes match Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency"Rob Barnes
This reverts commit c4a5acdabc28778b49a1c088b0736bac83e2ab51. Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible. TEST=Boot Dalboz BUG=b:159823235, b:169940175 BRANCH=zork Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-19mb/google/dedede/var/waddledee: Enable GPIO based I2C MultiplexerKarthikeyan Ramasubramanian
The camera sensor component chosen for UFC and WFC have an address conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also configure the GPIO that is used as select line. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19drivers/i2c/gpiomux: Add chip driver for multiplexed I2C busKarthikeyan Ramasubramanian
This chip driver adds ACPI identifiers for multiplexed I2C bus that are selected using GPIO. The multiplexed bus device defines the address to select the I2C lines. These ACPI identifiers are consumed by the i2c-mux-gpio kernel driver: https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html BUG=b:169444894 TEST=Build and boot to OS in waddledee. Ensure that the ACPI identifiers are added in appropriate context. Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, Zero) // _ADR: Address } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA1) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, One) // _ADR: Address } } Change-Id: If8b983bc8ce212ce05fe6b7f01a6d9092468e582 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19drivers/i2c: Add chip driver for GPIO based I2C multiplexerKarthikeyan Ramasubramanian
Add identifiers in ACPI tables for GPIO based I2C multiplexer. The multiplexer device defines the GPIO resource used to select the adapter/bus lines. The multiplexer adapter device defines the address to select the adapter/client lines. These ACPI identifiers are consumed by the i2c-mux-gpio kernel driver: https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Here is the output SSDT: Scope (\_SB.PCI0.I2C3) { Device (MUX0) { Name (_HID, "PRP0001") // _HID: Hardware ID Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x02) { Package (0x02) { "compatible", "i2c-mux-gpio" }, Package (0x02) { "mux-gpios", Package (0x04) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero } } } }) } } Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19soc/amd/common/acpi: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I3d5f595ebbc865501b086aebee1f492b4ab15ecd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19lib/imd: move struct definitions to a new header fileJakub Czapiga
Make IMD private structures definitions accessible by other units. To test IMD API correctness there is a need to access its internal structure. It is only possible when private implementation is visible in testing scope. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-19vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376Ronak Kanabar
The headers added are generated as per FSP v2376. Previous FSP version was 2295. Changes Include: - add GpioOverride UPD in Fspm.h - add new header FirmwareVersionInfo.h Cq-Depend: TBD Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45899 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19amd/picasso/verstage: replace rsa accel with modexpKangheui Won
Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp. Instead of using hardware acceleration for whole RSA process, acclerating only calculation part(modexp) increases transparency without affecting boot time. BUG=b:169157796 BRANCH=zork TEST=build and flash, check time spent on RSA is not changed Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/volteer: Enable USB4 retimer driverDuncan Laurie
Enable the USB4 retimer driver with GPP_H10 as the power control. Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie
The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/kukui: Support SKU from camera EEPROMHung-Te Lin
To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19drivers/camera: Add config CHROMEOS_CAMERAYu-Ping Wu
Add cros_camera_info struct for camera information, and check_cros_camera_info() for checking the magic, CRC and version. BUG=b:144820097 TEST=emerge-kukui coreboot BRANCH=kukui Change-Id: I1215fec76643b0cf7e09433e1190e8bd387e6953 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46042 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/volteer/elemi: Add memory.c for DDR4Wisley Chen
Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/purism/librem_skl: Clean up FSP-M RCOMP settingsAngel Pons
There's no need to use static functions to fill these settings in. Also, add missing include for <stdint.h> and initialize `mem_cfg` in one line. Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46252 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19mb/google/zork/var/vilboz: update dptc stapm timeJohn Su
Update dptc setting: Stapm_time_constant 1400 BUG=b:170696020 BRANCH=zork TEST=emerge coreboot and check "Stapm_time_constant" Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-10-19soc/intel/tigerlake: Reflow long linesSridhar Siricilla
Use the 96 character limit. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-10-19soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cbMarc Jones
platform_fsp_silicon_init_params_cb is called by the fsp driver and calls mainboard_silicon_init_params which sets the mainboard PCH GPIOs. Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner
Drop the Kconfig for hyperthreading to be always able to check at runtime if hyperthreading is supported. Having a Kconfig for this doesn't have any benefit. Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-17libpayload/libpci: Introduce device class attribute in pci_devFelix Singer
The device class is read at different places and it is read from the hardware directly. Therefore, and in preparation to CB:46416, introduce the device class attribute in the pci_dev struct. With this, there is only one interaction with the hardware and it's also more user friendly. Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46347 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17libpayload/libpci: Clean up pci_alloc()Felix Singer
Clean up pci_alloc() and return pointer to allocated memory directly. Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-17superio: Add newline to log message about disabled mouse controllerPaul Menzel
A newline is missing at the end of the informational message. PNP: 002e.5 init nct5572d_init: Disable mouse controller.PNP: 002e.5 init finished in 0 msecs PNP: 002e.307 init Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Fixes: 6ff1078990 ("superio: Log if mouse controller is disabled") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17mb: AMD CIMx boards: Fix typo in *is defined* in commentsPaul Menzel
The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/' Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17vendorcode/amd: Fix typo in *is defined* in commentsPaul Menzel
The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. $ git grep -l "is define at" src/vendorcode/amd/ | xargs sed -i 's/is define at/is defined at/' Change-Id: Ia26c87aecb484dcb55737e417367757d38ce3b56 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17AGESA mb: Replace tab with space in macro definition for consistencyPaul Menzel
With a tabulator length of eight spaces, the alignment is the same, but the other macro definitions are using a space, so do the same for consistency, better alignment in diff views. git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g' Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17vc/amd/Kconfig: Add missing dot in AMD domain www.amd.comPaul Menzel
Fixes: b266c6b5 ("AMD Steppe Eagle: Add binary PI vendorcode files") Change-Id: Id317b53cfafaae629c2a94144c419e2112eaf7a9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17superio/nuvoton: Only set bit 7 of global CR 0x2a for COM APaul Menzel
Currently, when selecting SUPERIO_NUVOTON_NCT*_COM_A, the whole global control register 0x2a is written to 0x40. CR 0x2a defaults to 0xc0, so indeed bit 7 is cleared, but the device early init code might have set other bits in that control register, so setting it to 0x40 might override already set bits. So, only clear bit 7 and leave the other bits untouched. Fixes: f95daa510d ("superio/nuvoton: Add back Nuvoton NCT6776 support") Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-17intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons
Due to platform-specific constraints, it is not possible to enable DPR by programming the MCH's DPR register in ramstage. Instead, assume it has been programmed earlier and check that its value is valid. If it is, then simply configure DPR in TXT public base with the same parameters. Note that some bits only exist on MCH DPR, and thus need to be cleared. Implement this function on most client platforms. For Skylake and newer, place it in common System Agent code. Also implement it for Haswell, for which the rest of Intel TXT support will be added in subsequent commits. Do not error out if DPR is larger than expected. On some platforms, such as Haswell, MRC decides the size of DPR, and cannot be changed easily. Reimplementing MRC is easier than working around its limitations anyway. Change-Id: I391383fb03bd6636063964ff249c75028e0644cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]Angel Pons
The BIOS ACM will check that enabled variable MTRRs do not cover more than the ACM's size, rounded up to 4 KiB. If that is not the case, launching the ACM will result in a lovely TXT reset. How boring. The new algorithm simply performs a reverse bit scan in a loop, and allocates one MTRR for each set bit in the rounded-up size to cache. Before allocating anything, it checks if there are enough variable MTRRs; if not, it will refuse to cache anything. This will result in another TXT reset, initiated by the processor, with error type 5: Load memory type error in Authenticated Code Execution Area. This can only happen if the ACM has specific caching requirements that the current code does not know about, or something has been compromised. Therefore, causing a TXT reset should be a reasonable enough approach. Also, disable all MTRRs before clearing the variable MTRRs and only enable them again once they have been set up with the new values. Tested on Asrock B85M Pro4 with a BIOS ACM whose size is 101504 bytes. Without this patch, launching the ACM would result in a TXT reset. This no longer happens when this patch is applied. Change-Id: I8d411f6450928357544be20250262c2005d1e75d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44880 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACMAngel Pons
When caching the BIOS ACM, one must cache less than a page (4 KiB) of unused memory past the end of the BIOS ACM. Failure to do so on Haswell will result in a lovely TXT reset with Class Code 5, Major Error Code 2. The current approach uses a single variable MTRR to cache the whole BIOS ACM. Before fighting with the variable MTRRs in assembly code, ensure that enough variable MTRRs exist to cache the BIOS ACM's size. Since the code checks that the ACM base is aligned to its size, each `one` bit in the ACM size will require one variable MTRR to properly cache the ACM. One of the several BIOS ACMs for Haswell has a size of 101504 bytes. This is 0x18c80 in hexadecimal, and 0001 1000 1100 1000 0000 in binary. After aligning up the BIOS ACM size to a page boundary, the resulting size is 0x19000 in hexadecimal, and 0001 1001 0000 0000 0000 in binary. To successfully invoke said ACM, its base must be a multiple of 0x20000 and three variable MTRRs must be used to cache the ACM. The MTRR ranges must be contiguous and cover 0x10000, 0x8000, 0x1000 bytes, in order. The assembly code is updated in a follow-up, and relies on these checks. Change-Id: I480dc3e4a9e4a59fbb73d571fd62b0257abc65b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46422 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17trogdor/sc7180: Clarify USE_QC_BLOBS requirementsJulius Werner
This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-10-16include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner
msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MSR header files. Thus, replace the helper by versions which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way commit 64a6b6c was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get added. The few uses of msr_set_bit have been replaced by the new version, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16libpayload/x86: Add some more CPUID helpersNico Huber
Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-16acpi/acpigen_dsm: fix I2C HID DSM to report correct function supportJosie Nordrum
Fix DSM function 0 (query function) to correctly report function support for its revision. Revision 1 should return 0x3 because I2C HID supports only 1 additional function. All other revisions should return 0. BUG=b:170862147 BRANCH=Zork TEST=ensure no dmesg errors; disassemble and verify SSDT Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Iee082ef5cf44c4cf7ab304345af56f3b5173ca56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46429 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16mb/google/zork: disable eMMC per FW_CONFIG for berknipKevin Chiu
Berknip has SSD/eMMC SKU, we should turn off eMMC　if storage is NVMe SSD. BUG=b:170592992 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-10-16mb/intel/adlrvp: Enable Hybrid storage modeSubrata Banik
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices. Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Enable PCIE RP11 for optaneSubrata Banik
A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width. Optane memory module shows up as 2 NVMe devices in x2 config: - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs because of same M.2 slot. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Fix SSD detection issue on ADL RVPSubrata Banik
Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP. TEST=Able to detect WD SSD card over PCH SSD RP9. Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Program GPIO for M.2 PCH SSDSubrata Banik
This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-15lib and libpayload: Add popcnt functionsAngel Pons
Add 32-bit `popcnt` and 64-bit `popcnt64` helpers. Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-15soc/intel/xeon_sp: Add get_system_memory_map()Marc Jones
Prepare for common ACPI. Add get_system_memory_map() helper function to soc_util.c and use it in the SRAT ACPI code to match the cpx code. Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15ec/google/chromeec: Update ec_commands.hYidi Lin
This change copies ec_commands.h from Chromium OS EC repo at 7b6cb69db. The change also drops unneeded empty lines and coverts license header to SPDX style. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I9816dab5edb418e76896355a0802c59307c664c4 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-15Update bit field helpers to support more bit field operateHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I8f182fff45806912da2390939a6652932501d7c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-10-15MAINTAINERS: add Michael Niewöhner to mb/clevoMichael Niewöhner
Add Michael Niewöhner as another maintainer for Clevo mainboards. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Id3b35ddda13119149321e8c883e151176d8c520d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43655 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPEArthur Heymans
This needs to be saved and restored, otherwise the BSP might have an inconsistent MTRR setup with regards to the AP's which results in weird errors and slowdowns in the operating system. TESTED: Fixes booting OCP/Deltalake with Linux 5.8. Change-Id: Iace636ec6fca3b4d7b2856f0f054947c5b3bc8de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15nb/intel/haswell: Account for DPR region in memory mapAngel Pons
While MRC.bin does not allocate any memory for DPR by default, it can be patched to do so. However, the current northbridge code does not account for DPR and will, among other things, place CBMEM inside it. Even though this may seem like a good thing, it renders TianoCore unable to boot and clashes with Intel TXT support (the reason to enable DPR to begin with). Update memmap.c so that CBMEM top does not fall within DPR. Also, report DPR as reserved, so that OSes know that the DPR memory is not to be used. Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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