Age | Commit message (Collapse) | Author |
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Initialize the input_hertz and uart_pci_addr fields of the lb_serial
struct to prevent later undefined reads in lb_add_serial(). This was
done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c:
Init new serial struct variables), and this patch finishes the rest.
Note that not all of the drivers can have the UART PCI address
configured at build time, so a follow-up patch will be needed to correct
those ones.
Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1354778
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Below new functions are added:
* send_hmrfpo_enable_msg() - Sends HMRFPO Enable command to CSE. This
API sets ME in SEC_OVERRIDE mode. The mode prevents CSE to execute SPI I/O
cycles to CSE region, and unlocks the CSE region to perfom updates to it.
* send_hmrfpo_get_status_msg() - Sends HMRFPO Get Status command to CSE
TEST=Verified sending HMRFPO_ENABLE & HMRFPO_GET_STATUS HECI commands on
CML RVP & hatch board
Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Add DPTF based thermal control for ambient sensor for CML based
Helios system. Also, update other sensor names information.
BUG=b:139335207
BRANCH=None
TEST=Build and Boot on Helios board and check all sensor details.
Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update DPTF thermal temperature threshold values for CML based
Helios system. This updates CPU active cooling temperature
threshold to appropriate values which addresses the issue of
running the Fan at lower CPU temperature as per bug.
Also, added active cooling temperature thresholds for other
TSR sensors.
BUG=b:141087272
BRANCH=None
TEST=Build and boot on Helios board to check the fan functionality.
Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34203
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I72afb0c0d34157d1d2d9fe4ae6704cd2502f724d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34202
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It won't build though, since current_time_from() has
been removed.
Change-Id: I2f7788f626c0504e6354a08b7986e4d18be140a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34201
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no board named X11SSH+-TF.
Change-Id: Ide01a8d59c09747dfe7d59fd9e17bd5194fb14e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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In interactive payloads, the USB stack's poll procedure is implicitly
called from the UI loop. Since all USB control transfers are handled
synchronously, polling hubs with these slows the UI significantly down.
So switch to interrupt transfers that are done asynchronously and only
perform control transfers when the hub reported a status change.
We use the interrupt endpoint's max packet size instead of the theo-
retical transfer length of `(bNrPorts + 1) / 8` as Linux' code mentions
hubs that return too much data.
Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add SKU#18 to config power sequence below:
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:134854577,b:137033609
BRANCH=octopus
TEST=build
Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds SPD files for Drallion. Use spd_index
matrix to correspond mem_id. This can save the dummy spd index
to reduce the size of SPD.bin.
BUG=b:139397313
TEST=Compile successfully
Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implementing logic to detect SKU model and enable ISH accordignly.
BUG=b:140748790
Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Source: Pin Schematics
BUG=b:139370304
Signed-off-by: Varun Joshi <varun.joshi@intel.com>
Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35175
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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../bd82x6x/early_usb.c: While ibexpeak needs an equivalent of this
code, it is not currently hooked up.
../common/gpio.c: Already linked in common/Makefile.inc
Change-Id: I980601e2302f2c412e823fef5fb9a69b9e151322
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35437
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found by Coverity Scan #1405310
Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35433
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device
is hotplugged into it, so the hotplug capability should be enabled on
PCIe port #5.
TODO: find the correct gpio pin to detect the Thunderbolt controller
at runtime.
There are 3 variants of mainboard for Thinkpad T430s: Basic type
(Wistron LSN-4 11263-1), Boards with an additional discreet GPU,
Boards with an additional TB controller (Wistron LSN-4 11271-1),
each of which has a different schematic.
The gpio27 on the last type is set as set as GPIO-INPUT, compared
with GPIO-OUTPUT-HIGH on the basic type boards.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This Kconfig symbol is set at a default of 36 in cpu/x86 and is now
only used in the romcc bootblock to set up caching to upgrade the
microcode. It's not mainboard specific.
Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35436
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix regression after commit
21160a7 Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h>
Builds with VBOOT_STARTS_IN_ROMSTAGE=y would evaluate
ENV_ROMSTAGE_OR_BEFORE incorrectly for verstage-class.
Follow-up changes for CBMEM console and timestamps, where
defined(__PRE_RAM__) tests are replaced, are likely to have
caused regressions such that VBOOT console and timestamps
are missing.
Change-Id: Idc274409c495efea95eeecd0538b2f8b847970ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For pcengines/apu2 variants we do not even send
DRAM ready message to PSP.
Possibly some GFX/DRM depends of running PSP but
these devices are headless. And we don't support
fTPM inside PSP either.
Reduces blob footprint in SPI from 466 KiB to 234KiB.
Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Move it above 'AGESA' to increase the maximum
continuous free space in CBFS from 5.3 MiB to 5.8 MiB.
Also fixes build for cases where CBFS_SIZE < ROM_SIZE,
thus allowing FMAP regions.
NOTE: Due to off-by-one error in binaryPI, offset
0xFFFA0000 that amdfwtool advertises fails
for xHCI firmware loading.
Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter.
Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional cleanup - Unify "Inc" to "Inc." and "LLC." to "LLC"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie03a3ce1f6085494bd5f38da76e2467970cf301a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We generally try to stay away from ascribing attributes to (future)
devs. "Rookie guide" refers to the reader, while "tutorial" refers
to the material.
In the same spirit, move from "lessons" to "parts". It's not school :-)
Change-Id: I11a69a2a05ba9a0bc48f8bf62463d9585da043ec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Iff6df888a293b525d436a5be215e8972ae2dd46a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's been some time and there are 1420 new commits. Including one that
allows reproducible builds \o/ and one that breaks building with empty
$(CC) :-/
Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TESTED=UP Squared
Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34838
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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send_heci_reset_req_message() is defined in multiple places,
hence move it to common code.
TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards.
Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33528
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set BL31 platform to mt8183 to link with ARM Trusted Firmware.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui with more patches in ATF.
Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change overrides USB port settings for kohaku.
Some port settings are same with baseboard, but I'd like to describe all
settings here to be aware of current setting and usage of USB ports on
kohaku.
BUG=none
BRANCH=none
TEST=built and measured SI of USB ports internally
Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I6658c53213127db5a46f2ea330d85a3a537c3276
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This adds SATA parameters for SpinUp, HotPlug and TestMode to the
Skylake FSP 2.0 interface.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Make microcode lib available in bootblock. Now that microcode.c is compiled
in bootlock no need to include it explicitly, hence remove its references.
Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35278
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9240043d2c15b68aabe154b289a961d8d48d3e5f
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I4f38be28d81c0c01c0389210552232e63ea55545
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34934
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9db59d5db2ed3e792251a94b67fb277d9160e4e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33734
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8578cf365addc47550e27c9ebed08de340d70ede
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33531
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33529
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5dff9b7c157b2aba596e95b5fb18a84f7c4e9365
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.
It is found on the ark page of e.g. the Intel i3-4130 CPU.
Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Every vga init implementation needs to cache the framebuffer state
to be able to fill the lb_framebuffer struct later on in the
fill_lb_framebuffer call. Showing the bootsplash afterwards
guarantees to have the same interface into all the vga drivers.
This is by far from ideal, as it only allows for a single driver at
compile-time and should be adapted in the future.
It was tested on the wip razer blade stealth using vgabios @ 1280x1024
and also in Qemu @ 1280x1024.
By default the qemu framebuffer will be initialized in 800x600@32.
This can be overwriten by configuration by setting
CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES .
Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The PCO_HDA0 device contains the "ATI" vendor ID 0x1002 and was
incorrectly added to this file. It isn't anticipated that the
device will need special handling, so remove it from the list
of supported IDs.
Change-Id: I306a806dc510e3a4ee3d9c0663306dc93b1d936d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Change-Id: Iaa56e7b98aad33eeb876edd7465c56c80fd1ac18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Iae31569f16168ba00ce272e4777f3a69bcd6ee94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35390
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unused and declaration conflicts with the one
amdfam10-15 uses in romstage.
Change-Id: Icd454431285b7c423a4f78d2a0085497d052adc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35394
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unused since commit d46b8d5.
Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Information based on superiotool dump.
Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enables and configures GPIOs in the NCT6791D chip. The values for
registers taken from the superiotool dump.
Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35369
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).
Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.
NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.
Tested on GOOGLE_KEVIN (rk3399).
Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This was implemented for LATE_CBMEM_INIT support which
has already been deprecated.
Change-Id: I39225ba675bc3389e051e15b400a905431969715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allocation of new table always happens in romstage.
Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35374
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibaeda2762c733fdbe48979b635cc0cfd7ee4295d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Guards are required due to different PCI accessor
signatures.
Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35381
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:140008849, b:140573677
TEST=verify eMMC SKU and SSD SKU will bring up normally.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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replace multiple existing FW_CFG_* defines with enum fw_cfg_enum.
Change-Id: I9699df4aeb2d8b18f933bb9aaed16008d10158ad
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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In FSP-S, the driver constructs its pointer to UPD using the offset
in the header. Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.
Add sanity checks for unexpedted configuration and UPD header
conditions.
TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081
Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Leverage already used eax register in bootblock_protected_mode_entry.
Avoid another register ebx just for preserving eax value as it is not
needed and is not used at all after moving the value into mm0.
Allow EBX to be preserved for other usage.
Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Exclude FSP-M loading from the timestamps used for
RAM detection and training process.
Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.
TEST=Build and boot arcada_cml
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.
TEST=Boot to OS on WHL platform
Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Even though GT7375P programming guide rev0.4 only requires a reset delay
of 120ms, in practice, we have to increase the reset delay to 500ms, or
Goodix FW update would fail.
This is a workaround. In the long run, we hope Goodix can fix the power
sequence in touch firmware.
BUG=b:138795891, b:138796844
TEST=boot helios board and verify Goodix FW update succeeded
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the raw register definitions with device numbers and macros
for determining the register offsets. Rewrite the source to refer
to AOAC device numbers instead of a structure.
Remove the calculated offset for the console UART. Picasso's UARTs
are not contiguous so handle them separately.
Change-Id: Iffc87f39ebe38394a56d41bb0940e9701fd05db9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483
TEST='compile successfully'
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.
TEST=Build and boot sarien/arcada.
Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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With the current devicetree the kernel doesn't provide any serial
after serial init.
Update the devicetree to resolve this issue.
Tested on HiFive Unleashed.
Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id0b9fd9cd248c83b00bc84e9d21abc6b095ecf76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33731
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33730
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is necessary to get rid of a .c include.
Also do some cosmetic fixes to a table, now that the line length limit
has been raised.
Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs,
hence move it to common. Also add below helper function,
* wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE".
It's a special CSE mode, the mode ensures CSE does not trigger any
spi cycles to CSE region.
* set_host_ready() - Clears reset state from host CSR.
TEST=Verified CSE recover mode on CML RVP & Hatch board
Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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BUG=b:140545315
TEST=builds Kodama image and verify display working properly
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change-Id: Ifcd75630e562af302312f93bdf180aa90f18d21d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate timestamp_sync_cache_to_cbmem() as it is only
used with ENV_ROMSTAGE.
Change-Id: Ibe18a5ecf09b2b87d8ee3e828728ad6a8a262206
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35280
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:133000685
Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.
BUG=b:133000685
Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.
BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot
Without this CL:
Total Time: 929ms
With this CL: (TSEG marked as WB)
Total Time: 910ms
For test marked TSEG as WP/WC:
Total Time: ~920ms
Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes dedicated function call to make TSEG region cache
from soc and refers to postcar_enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This reverts commit fdb9805d6884090fd7bf62dbdf9c858692e55fb4.
CB:33252 wasn't reviewed by a TPM maintainer and breaks abstraction
layers (pulling TSS-details into TSPI, completely changing
interpretation of the arguments to tlcl_extend() based on TSS version).
It's also not clear why it was implemented the way it was (should have
been much easier and cleaner ways to achieve the same thing).
Since the author is not reacting, let's revert it for now. It can be
cleaned up and resubmitted later. (Not reverting the header changes
since those are not objectionable, and there are later patches dependent
on it.)
Change-Id: Ice44f55c75a0acc07794fe41c757a7bca75406eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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futility is built for the host. However, when cross-compiling,
the target's pkg-config is called to get the library paths which
can add paths from the cross-compilation tree instead of host.
e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config
. /build/elm/usr/bin/pkg-config adds the paths specific to the
cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib.
This causes linker to complain that files in library paths do not
match the architecture. BFD produces a warning while LLD errors out.
Fix this by passing PKG_CONFIG from host when building futility.
BUG=chromium:999217
TEST=coreboot builds
BRANCH=None
Cq-Depend: chromium:1778519
Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000.
Refer to FSP integration guide to know the exact FSP requirement.
BUG=b:140268415
TEST=Build and boot CML-Hatch and ICL.
Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new API for enabling caching for the TSEG region
and setting up required MTRR for next stage.
BUG=b:140008206
TEST=Build and boot CML-Hatch.
Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Create dratini variant
BUG=b:140610519
TEST=emerge-hatch coreboot, and boot into chromeos on proto board
Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drallion uses the same touch panel as Sarien. Copy the deivce
from Sarien.
BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ITR2 is specified twice here, which leads to the following error message
in Linux:
[ 0.263591] ACPI BIOS Error (bug): Failure creating named object
[\_SB.PCI0.LPCB.SIO0.ITR2], AE_ALREADY_EXISTS (20190509/dsfield-633)
Add comments and fix duplicated field.
As there are no users of this code yet, just rename the fields.
Tested on Supermicro X11SSH-TF.
Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35294
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifc3825119c8463a7d17a5c162330f49612ae1b85
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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