summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-12-13mainboard/google/reef: implement phase enforcement pinAaron Durbin
On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17803 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-13vendorcode/google/chromeos: provide acpi phase enforcement pin macrosAaron Durbin
In the factory it's helpful for knowing when a system being built is meant for release with all the security features locked down. Provide support for exporting this type of pin in the acpi tables. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: Iec70249f19fc36e5c9c3a05b1395f84a3bcda9d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17802 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-13rockchip: rk3399: change emmc clk to 148.5MHzZiyuan Xu
Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could improve stability like kernel. CQ-DEPEND=CL:386527 BUG=chrome-os-partner:54377 BRANCH=none TEST=build and boot on kevin Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2 Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1 Original-Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386865 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17790 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13vendorcode/google/chromeos: zero out SHARED_DATA regionPatrick Georgi
BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has a zeroed out SHARED_DATA region if it exists. Change-Id: Ib1e6fd62bcf987872890c6d155287dcedb0b1f40 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8a88bf744f44d034f8606a556014e2bee37eda1 Original-Change-Id: I0b59f1f0e2f8645000f83cb3ca7f49e4da726341 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417821 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/17789 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13vendorcode/google/chromeos: Fill in firmware ID regionsPatrick Georgi
Chrome OS images have three firmware ID regions, to store version information for the read-only and the two read-write areas. Fill them with a suitable default and allow configuring a different scheme. There's already an override in google/foster and google/rotor to match the naming scheme used so far (in depthcharge). BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has the expected values in the regions. Change-Id: I5fade5971135fa0347d6e13ec72909db83818959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417320 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/17788 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13util/cbfstool: Enable filling fmap regions with a given valuePatrick Georgi
So far, cbfstool write, when used with the -u/-d options (to "fill upwards/downwards") left the parts of the region alone for which there was no new data to write. When adding -i [0..255], these parts are overwritten with the given value. BUG=chromium:595715 BRANCH=none TEST=cbfstool write -u -i 0 ... does the right thing (fill the unused space with zeroes) Change-Id: I1b1c0eeed2862bc9fe5f66caae93b08fe21f465c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: baf378c5f2afdae9946600ef6ff07408a3668fe0 Original-Change-Id: I3752f731f8e6592b1a390ab565aa56e6b7de6765 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417319 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/17787 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13lenovo: Don't use extern with functionsKyösti Mälkki
Change-Id: I8313ba1d93922297e5061701dad47d07617d1dcd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13pc80: Move set_boot_successful()Kyösti Mälkki
Don't implement arch or driver -specific code under lib/, Change-Id: If75980ec5efc622582e2b5e124ad0e7ee3fa39a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17793 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13util/cbfstool: require -i argument for cbfstool add-intPatrick Georgi
We never specified what value add-int should write by default. Change-Id: I240be4842fc374690c4a718fc4d8f0a03d63003c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/17796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-13intel MMA: Enable MMA with FSP2.0Pratik Prajapati
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13vendorcode/amd/agesa: Remove flawed warningŁukasz Dobrowolski
The compilation would fail if CFG_MEMORY_LRDIMM_CAPABLE == FALSE and BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE. Change-Id: I1be37e368bc4ed07e59d0f0bb967bed11143a65b Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io> Reviewed-on: https://review.coreboot.org/17354 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-13nb/intel/gm45: Use lapic udelay in SMMMartin Roth
This is a follow-on patch to commit 10141c30 - (nb/intel/gm45: Use LAPIC udelay instead of custom version) which removed the custom udelay from everywhere except SMM. This patch removes it from SMM as well, and gets rid of the gm45/delay.c file. Change-Id: I7970bb5205f4aa10b38172ab5b9f8bcd6766c4e7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17330 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-13mb/lenovo/*00: Remove Roda/RK9 specific codeNico Huber
Change-Id: Iacf2e1c0b8003a3588ccbf79e17500ed12f39503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-12lint/kconfig_lint: Make sure all symbols have a type definedMartin Roth
Show an error if a symbol does not have a defined type. This caused a problem of an undefined symbol in check_defaults, so we just skip those symbols there as we can't verify the default pattern without knowing the type. Change-Id: I28711a77962e16f6fc89789400363edd0fdd0931 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17345 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12util/lint: add check for auto-included headersMartin Roth
Since we've removed them from the tree, add a check to keep them out. Change-Id: I2995da765fee8796a297963d54a1c34f56376efe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12Kconfig: Change symbol override from warning to noticeMartin Roth
Overriding symbols within a .config is pretty common when doing automated builds with various different options. The warning text makes it sound like this is an issue, so change it to say 'notice' instead. We could get rid of it completely, but it's not a bad thing to know that we have two copies of the same symbol in the .config. BUG=chrome-os-partner:54059 TEST=copy a disabled kconfig option to the end and set it to y. See notice text instead of warning. Change-Id: I9f575b2275233f638e42676263348c807e6515bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-12util/docker: Add a makefile for common docker tasksMartin Roth
Commands for working with docker images: build-coreboot-sdk - Build coreboot-sdk container upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com build-coreboot-jenkins-node - Build coreboot-jenkins-node container upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com clean_coreboot_containers - remove all docker coreboot containers clean_coreboot_images - remove all docker coreboot images Commands for using docker images docker_build_coreboot <BUILD_CMD=target> - Build coreboot under coreboot-sdk docker_abuild <ABUILD_ARGS='-a -B'> - Run abuild under coreboot-sdk Change-Id: I3a75b0615747d32f593948f53eab076f303271bf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16388 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12google/pyro: Set PL2 override to 15000mWKevin Chiu
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17779 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-12Makefile.inc: Update what-jenkins-does targetMartin Roth
- Update the junit.xml target to make it less util specific - Add builds of coreboot internal payloads: nvramcui and coreinfo Change-Id: I97fda909065659ab7fa4c8ee00d936d97b255bf7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17014 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12util/abuild: Add more error handling for command line optionsMartin Roth
- Show an error if a directory is added after the command line options to catch scripts using the old parameters. - If an invalid parameter is specified, show the parameter. Change-Id: Ie8948361f1c51e89a99bdb13df8c554747cd521d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17741 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12util/abuild: Add argument -R to specify root directoryMartin Roth
cbroot was previously specified by just adding it to the end of the command line with no explicit identifier. This change allows it to go anywhere in the command line and adds the -R or --root identifier. This makes the command line more consistent. Most of the time, this argument isn't even needed, as the automatic detection finds cbroot. Change-Id: I1d6fd8f51765d0d8b29be8af1e8105e06dd44cc8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17740 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12util/abuild: Clean up usageMartin Roth
- Indent with spaces for consistency - Change lbroot to cbroot - Remove incomplete list of options from usage line - Capitalize first word of all option text - Alphabetize options other than version and help - Move version and help options to the end Change-Id: Id5bd4db8d7e3705cbbb93895a46a3608cd1b09e2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17724 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-12util/abuild: Fix or disable shellcheck warningsMartin Roth
This cleans up the shellcheck warnings in abuild. Warning count: 1 Unexpected ==. 1 Use "${var:?}" to ensure this never expands to / . 1 VARIABLE appears unused. Verify it or export it. 1 Use "$@" (with quotes) to prevent whitespace problems. 2 Consider using { cmd1; cmd2; } >> file instead of individual redirects. 2 Expressions don't expand in single quotes, use double quotes for that. 3 Prefer [ p ] || [ q ] as [ p -o q ] is not well defined. 4 $/${} is unnecessary on arithmetic variables. 5 Check exit code directly with 'if mycmd;', not indirectly with $?. 5 Use cd ... || exit in case cd fails. 11 Declare and assign separately to avoid masking return values. 13 Use $(..) instead of legacy `..`. 20 Don't use variables in the printf format string. 104 Double quote to prevent globbing. Change-Id: I9c77e122435ba87ce3a4aee76b5022f7265f9ef2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-11drivers/intel/fsp2_0: Include stddef.h in soc_binding.hFurquan Shaikh
soc_binding.h includes FSP headers which define NULL macro. Because of this, including stddef.h after soc_binding.h results in NULL being re-defined. Thus, include stddef.h in soc_binding.h to avoid having users include stddef.h along with soc_binding.h. Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17773 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11nb/intel/i945: Make pci_mmio_size a devicetree parameterArthur Heymans
Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16856 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-11ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP defaultKyösti Mälkki
Except fo nehalem, K8, f10 and f15 (non-AGESA) romstage ramstack is placed in CBMEM and ramstage loader takes care of tiny backup. Change-Id: I8477944f48ed2493d0a5e436a4088eb9fc3d59c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17358 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11ACPI S3: Hide acpi_slp_typeKyösti Mälkki
Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/10360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/nehalem: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I2085fc3a17d32cfbdab9ec0b7afbc01031e75b47 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/i945: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With this change, CBMEM region is set early-on as WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel i945 gm45 x4x: Apply cbmem_top() alignmentKyösti Mälkki
Force modest 4 MiB alignment to help with MTRR assignment. Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17780 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11x86 SMM: Fix use with RELOCATABLE_RAMSTAGEKyösti Mälkki
The value for _size was not evaluated correctly if ramstage is relocated, make the calculation runtime. While touching it, move symbol declarations to header file. Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10cpu/intel/lga775: Do not select model_6ex CPUArthur Heymans
Model 6ex are Core Solo and Core Duo CPUs (yonah) that never existed with a LGA775 socket. This reduces the size of the microcode from 180k to 168k. Change-Id: Ic5b3d0e7c8009dab2dca477010c328274a818fed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17120 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-10cbfs: Add API to locate a file from specific regionPratik Prajapati
This patch adds an API to find file by name from any specific region of fmap. Change-Id: Iabe785a6434937be6a57c7009882a0d68f6c8ad4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10intel 82801dx/gx/ix: Commit SMM relocation code to DRAMKyösti Mälkki
Make sure relocation code reaches DRAM before issuing any SMIs. Snooping and cache coherency may have undefined behaviour as CPUs do not have uniform MTRR layout yet. Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17712 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09postcar_loader: Support LATE_CBMEM_INIT boardsKyösti Mälkki
Create postcar_frame object without placing stack in CBMEM. This way same cache_as_ram.inc code can be used unmodified. Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09intel/sandybridge: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake. Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09mainboard/google/reef: fill in NHLT ACPI OEM header fieldsAaron Durbin
Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to differentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17772 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-09mainboard/google/reef: add board SKU'ing supportAaron Durbin
There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-09abuild: Build saved config filesMartin Roth
Update abuild to allow for building saved miniconfig files. If one or more config files exist for a platform under coreboot/configs, they will be built instead of the automatically generated default config. The config filename needs to start with "config.$VENDOR_$BOARD" to be picked up by the abuild script. - Update to version 0.10.0 - Add -d parameter to specify the saved config file directory - Break 2nd half of create_config function into update_config to set the payload for saved config files. - Unset new payload Kconfig options that could be set in a saved config file. - Update a bunch of MAINBOARD variable names to BUILD_NAME since the build name isn't necessarily the same as the mainboard name. - Split build_target into two functions - build_target and build_config because one mainboard can now build multiple configurations. - Update remove target and call it directly from build_target() instead of from build_targets() Change-Id: I1a276d3e507b178f7dcd9dc125fa9c59f1ab47bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17590 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-09util/kconfig/conf.c: Fix newline in error printfMartin Roth
For some reason the \n in the defconfig save error was not escaped. Change-Id: I6a76b258f461a194fe17aae2b4fa04326b46d8d6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17742 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-12-09util/lint: Add check to verify saved configs are miniconfigsMartin Roth
Change-Id: Ifc5ec645dd27663c1b1fde9ff16d48534606a554 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17600 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-09configs: Add some sample default configuration filesMartin Roth
Test some config options that don't typically get tested. Change-Id: Ie05c99411c8ce6462a6f5502b086ee2b72a4324b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17591 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-08google/eve: Add ASL code to describe SPI FPC1020 controllerDuncan Laurie
There is ongoing work to link SPI bus and devices in to the devicetree so this can be generated, but for now put in the raw ASL code to describe this controller so it can be used by the factory. BUG=chrome-os-partner:55538 TEST=successfully load fpc1020 kernel module on eve board Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08soc/intel/apollolake: Move privilege drop to later stageAndrey Petrov
Previously privilege drop was happening "too early" and that caused some PMC IPC programming (performed in FSP) to fail because sideband was already locked out. This change set moves privilege drop to later stage, after last FSP notify call. BRANCH=reef BUG=chrome-os-partner:60657 TEST=iotools rdmsr X 0x121, make sure they can't be read. Also dmesg|grep -i IPC to make sure there are no errors related Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17769 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08cpu/x86: allow AP callbacks after MP initAaron Durbin
There are circumstances where the APs need to run a piece of code later in the boot flow. The current MP init just parks the APs after MP init is completed so there's not an opportunity to target running a piece of code on all the APs at a later time. Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows the APs to perform callbacks. BUG=chrome-os-partner:60657 BRANCH=reef Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17745 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2016-12-08bootstate: add arch specific hook at coreboot exitAaron Durbin
The bootstate machine allows one to schedule work at the boundaries of each state. However, there are no priorities by design. As such if there are things that need to be performed that are interdependent between callbacks there's no way to do that aside from explicitly putting the call in one of the callbacks. This situation arises around BS_OS_RESUME, BS_PAYLOAD_LOAD, and BS_PAYLOAD_BOOT as those are the states where coreboot is about to exit. As such, provide an architecture specific hook at these key places so that one is guaranteed any work done in arch_bootstate_coreboot_exit() is after all callbacks in the state machine. BUG=chrome-os-partner:60657 BRANCH=reef Change-Id: Icb4afb341ab15af0670501b9d21799e564fb32c6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17767 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-08mainboard/google/reef: Set PL2 override to 15000mWSumeet Pawnikar
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17730 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08soc/intel/apollolake: Set PL2 in RAPL registerSumeet Pawnikar
This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08commonlib: provide incoherent region deviceAaron Durbin
The MRC cache uses an incoherent mechanism for updating the cache contents in that it assumes memory mapped boot device access for checking against latest data for update. However, it uses another driver for updating the underlying storage area. In order to aid in moving the MRC cache over to using region_devices for updates provide an implementation of a region_device which performs reads and writes to different region_devices so that different drivers can be used transparently. BUG=chrome-os-partner:56151 Change-Id: I30e858245c30cbccd6313aff5ebecd3fd98d7302 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17716 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-08drivers/spi: provide a mechanism to obtain the SPI flash boot deviceAaron Durbin
The MRC cache wants to be able to access the SPI flash boot device. Allow an easy way to provide that so that there isn't duplicate spi_flash objects representing the same device. BUG=chrome-os-partner:56151 Change-Id: Iba92e8bb8a6060cdd327b10f5f8ec23ac61101e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-08lib: add region file supportAaron Durbin
The region file library is added to provide the underpinnings for other libraries that support appending updates when the data changes. The most recent written data is deemed the latest data associated with that "file". A good example is the MRC cache which in a follow-up patch utilizes this library. BUG=chrome-os-partner:56151 Change-Id: Ic3caf1edbb6f11dbbe27181a87b7b19d1224fffa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17713 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-08lib/compute_ip_checksum: mark data buffer as constAaron Durbin
compute_ip_checksum() doesn't manipulate the data it is passed. Therefore, mark it as const. BUG=chrome-os-partner:56151 Change-Id: I54cff9695a886bacd6314aa441d96aaa7a991101 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17714 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08google/beltino, tidus: simplify led_power_on() functionMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Remove unnecesary function param, includes for Tidus. Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17744 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-08drivers/r8168: Read default MAC address from CBFSDamien Zammit
This driver applies to 10ec:8168 Previously, this driver resetted the nic and set a hardcoded MAC address. Now the driver reads a default MAC address from CBFS in the form of a string: echo -n "xx:xx:xx:xx:xx:xx" > macaddress and store the macaddress file in CBFS with the same name. TESTED on GA-G41M-ES2L and GA-945GCM-S2L: MAC address was detected Change-Id: If1af91120fa3efca3f1406334a83ed1e59fbdaf9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17672 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-08libpayload: Add Cougar Point PCH's AHCI to whitelistNico Huber
Change-Id: Ie8ca342a32323be4c26c236a5209052ec724317f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17353 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08nb/intel/sandybridge: Lock PAVPCDennis Wassenberg
This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt to lock it nevertheless. Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: https://review.coreboot.org/17352 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08sb/intel/bd82x6x: Add TCO_Lock in finalize stepDennis Wassenberg
CHIPSEC found that the TCO_Lock was not set. This is used to prevent changing the TCO_EN bit. Change-Id: I42364dbef2511e656662566cf94591e76c6847ed Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: https://review.coreboot.org/17351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07soc/broadwell: set EM4/EM5 registers based on cdclkMatt DeVillier
The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17718 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07google/beltino: fix LED, simplify function for Tricky variantMatt DeVillier
Simplify set_power_led() by consolidating switch and setting values as needed inline based on LED state. Fix non-off LED polarity for Tricky using correct value from Chromium source TEST: power on Tricky, observe LED lit / solid Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17719 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07autoport: Fix romstage generatorKyösti Mälkki
Prototype changed here: e258b9a intel sandy/ivy: Improve DIMM replacement detection Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17711 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07src/device: Get device structure by path typeSubrata Banik
Add helper function to find a device by path type in the device tree. Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc Credits-to: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Dhaval V Sharma <dhaval.v.sharma@intel.com> Reviewed-on: https://review.coreboot.org/17731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07soc/intel/apollolake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17562 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07spi: Clean up SPI driver interfaceFurquan Shaikh
1. Add new structure spi_ctrlr_buses that allows platform to define a mapping from SPI controller to buses managed by the controller. 2. Provide weak implementations of spi_init and spi_setup_slave that will be used by platforms using the new interface. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17561 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/intel/skylake: Remove unwanted spi_release callFurquan Shaikh
Skylake uses a special SPI Flash controller and does not require spi_claim_bus and spi_release_bus functionality. This was a leftover call from earlier cleanup, so remove it. Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17729 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/intel/skylake: Remove redundant BootLoaderTolumSize assignmentSubrata Banik
BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size() inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment. Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07lib: Add time stamp when starting to finalize chipsPaul Menzel
Add the new time stamps *finalize chips* to track, when the method `dev_finalize_chips()` is called, so that the real time of `write_tables()` is known. Change-Id: I65ca0ec4c07c2eaa14982989cb206d23d8a2293f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07sio/ite/it8783ef: New super i/o chipNico Huber
This will be used by new Roda boards. Four UARTs and PS/2 keyboard and mouse are exposed to ACPI. Since our boards only use the environment controller part, most of the usual pnp interfaces are untested. Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODENico Huber
ITE super-i/o chips need a fourth byte and have a special register to exit config mode. Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07sio/ite/common: Export pnp_enter/exit_conf_state()Nico Huber
Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17285 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07soc/mediatek/mt8173: Do not initialize static variables to 0Furquan Shaikh
Change-Id: Ibf0bd772bfdb3bbf6482a0ec9ff90a5c0a8945d2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17765 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07AMD fam10 binaryPI: Remove invalid PCI ops on CPU domainKyösti Mälkki
Device is of type CPU_CLUSTER, while pci_dev_set_resources() expects PCI_DOMAIN. Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07mainboard/google/reef: adjust chromeos.fmd regionsAaron Durbin
- Drastically reduced RW_MRC_CACHE size to hold one update. Now that this area isn't changing after every S5 entry there's no need make it so large. - ELOG area reduced by 4KiB for subsequent area alignment. In practice this doesn't matter because the elog library only uses 4KiB bytes. 16KiB->12KiB is a nop. - Moved RW_NVRAM for subsequent alignment. - Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries and sized to 64KiB multiples. This ensures updates don't need a read-modify-write that could force a system into recovery if an inopportune power event occurred. BUG=chrome-os-partner:60492 BRANCH=reef Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17727 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06buildgcc: Be less restrictive when trying to build GNATNico Huber
It turned out that newer GNAT versions can build our current (5.3.0) GNAT without bootstrapping. So adapt the version enforcement. Change-Id: Ie7189e8bcadeee56cf5c2172e8c0ae7cd534685a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06buildgcc: Fix function prototype in GCCNico Huber
With some newer versions of GCC (experienced with GCC 6.2.1 on Arch- Linux) the first stage of a boostrapping fails due to a mismatching function prototype. Also add a missing `static` to the signature. Change-Id: Ia927036ccd725550f1191890515578bc80c74f80 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06Bob: Update the memory ramid of bobShasha Zhao
Update the memory ramid. Move to one CA training pattern. BUG=chrome-os-partner:59454 BRANCH=firmware-gru-8785.B TEST=Build firmware passed Change-Id: Ic05cbc1700a13e372f63d5202459add0e984f9d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1030a78af3d489d13508f17a79df1e65bd5afa3b Original-Change-Id: Ibe8acb5b698cec1adcdddbb13d35a5e20a5b8c0d Original-Reviewed-on: https://chromium-review.googlesource.com/414664 Original-Commit-Ready: Shasha Zhao <Sarah_Zhao@asus.com> Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Change-Id: I0ae46e496cd18492a2b6c7167081798c2f2479b1 Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411645 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17679 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06Bob: add bob in corebootShasha Zhao
Add bob in coreboot and update as necessary. 1. Add bob HWID 2. Add supported memory source BUG=chrome-os-partner:59454 BRANCH=firmware-gru-8785.B TEST=Build firmware passed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: Iad03a293bdbbb89450f0fea0822e34a4be7064bf Original-Commit-Id: bff788c71a43403bff2c23b38e69cc27fb869559 Original-Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411083 Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf) Original-Reviewed-on: https://chromium-review.googlesource.com/413744 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17678 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06rockchip/rk3399: sdram: use register to calculate sdram sizesLin Huang
We may support different sdram sizes on one board in future, so we need to calculate sdram sizes from sdram drvier. BRANCH=None BUG=None TEST=boot kevin Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411600 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06google/gru: Power-cycle USB ports in developer/recovery modesJulius Werner
Gru only uses USB 2.0 in firmware to avoid all the madness associated with Type-C port orientation and USB 3.0 tuning. We do this by isolating the SuperSpeed lines in the Type-C PHY so it looks like they aren't connected to the device. Unfortunately, some devices seem to already get "locked" into SuperSpeed mode as soon as they detect Rx terminations once, and can never snap out again on their own. Since the terminations are already connected during power-on reset we cannot disable them fast enough to prevent this, and the only solution we found to date is to power-cycle the whole USB port. Now, Gru's USB port power is controlled by the EC, and unfortunately we have no direct host command to control it. We do however have a command to force a certain USB PD "role", and forcing our host into "sink" mode makes it stop sourcing power to the port. So for lack of a saner solution we'll use this to work around our problem. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Booted Kevin in recovery mode, confirmed that my "problem stick" gets detected immediately (whereas previously I had to unplug/replug it). Booted Kevin to OS in both developer and normal mode and confirmed that USB still seems to work. Change-Id: Ib3cceba9baa170b13f01bd5c01bd413be5b441ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd695eda33299e50362f1096c46f2f5260c49036 Original-Change-Id: I2db3d6d3710d18a8b8030e94eb1ac2e931f22638 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413031 Reviewed-on: https://review.coreboot.org/17628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06google/chromeec: Add command to control USB PD roleJulius Werner
Normally firmware should have no business messing with the USB PD role (source/sink/whatever) in the EC. But, as so often happens, ugly issues crop up that require weird work-arounds, and before you know it you need to do this for some reason that only makes sense in context. I do now, so add this function to send the necessary host command in the simplest possible fashion. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Used it in a follow-up patch. Change-Id: I07d40feafd6a8387a633d6384efb205baf578d76 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8b71767caccff9b77d458182ce8066f7abf6321c Original-Change-Id: Ie8d0be98f6b703f4db062fe2f728cd2588347202 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413030 Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/17627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/cpu.h: Drop excessive includesKyösti Mälkki
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17734 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Move SMM prototypes under x86Kyösti Mälkki
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17732 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06PCI ops: Remove pci_mmio_xx() in ramstageKyösti Mälkki
MMCONF operations are already the default so these would never be used. Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17691 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Rename pcie_xx() to pci_mmio_xx()Kyösti Mälkki
Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17530 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Remove conflicting duplicate declarationsKyösti Mälkki
The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06mb/lowrisc/nexys4ddr: Read RAM information from the config stringJonathan Neuschäfer
Change-Id: I9147eca0b536b6267d58f6e8baa37b6950b35160 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>