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2018-06-11mb/google/poppy/variants/nami: Add EC_ENABLE_TBMC_DEVICEShelley Chen
Add tablet motion control config to nami devices. BUG=None BRANCH=None TEST=run evtest make sure tablet switch value is 1 in tablet mode and 0 when not in tablet mode Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26970 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/google/poppy/variants/nocturne: enable nvmeNick Vaccaro
- configure GPP_B7 (PCIE_NVME_CLKREQ_ODL) for NF1 - enable root port 9 - add nvme register settings to devicetree BUG=b:78122599 BRANCH=chromeos-2016.05 TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage', boot to kernel, and verify /dev/nvme* entries exist. CQ-DEPEND=CL:1090070 Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-11Fizz: Remove BJ adapter configurationDaisuke Nojiri
This patch removes BJ adapter configuration, which has been moved to the EC. BUG=b:109762580 CQ-DEPEND=CL:1089328 BRANCH=none TEST=Verify BJ adapter is set expectedly on Teemo. Change-Id: I3041b984e7f02624b94ba2713b084d001fa155f9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/26965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11crossgcc: Update to clang 6.0 & cmake 3.11.3Martin Roth
Change-Id: I1a0db60b527c2f7ffe77743c0d75b78a7c8bc4cc Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26877 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-09sb/intel/lynxpoint: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-09sb/intel/fsp_bd82x6x: Use pci_devfn_t instead of device_tElyes HAOUAS
Change-Id: I775f5482970905134bb395b03845eb798d88d209 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-08soc/intel/skylake: Enable low power S0Idle capabilityHaridhar Kalvala
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0 if S0ix is enabled for the platform. BUG=b:79559085 TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table - FADT.Flags[21] bit. Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210 Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/26940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-08util/sconfig: Get rid of rescnt in struct deviceFurquan Shaikh
This change gets rid of rescnt member in struct device since it is redundant. "res" member can be used to determine if resource list is present or not. BUG=b:80081934 TEST=Verified that static.c generated with and without this CL is exactly the same for all boards built using abuild. Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08util/sconfig: Re-factor device structure in parse treeFurquan Shaikh
This change re-factors the device structure in parse tree to be able to support multidev devices just like non-multidev devices. With this change, every device has a bus under it which is the parent of all devices that fall on the bus. If there are duplicate entries in the devicetree, then there will be multiple buses under the device and each bus will have its own set of children. The tree starts out with a root device which has a root bus under it. This is a special device which is created statically and its parent is its own root bus. When parsing the device tree file, devices get added under the root bus as children. Since this change re-organizes the way devicetree is represented, it gets rid of latestchild and next_sibling pointers from struct device. Also, the tree traversal to generate static.c is changed to breadth-first walk instead of using the next_sibling. BUG=b:80081934 TEST=Verified using abuild that all boards compile successfully. Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08util/sconfig: Make queue handling more generic within main.cFurquan Shaikh
This change updates queue handling routines to be more generic so that it can be used by more than just chip queue. Additionally, it provides functions to dequeue element from head and peek head of a queue which will be used in a follow-up commit. BUG=b:80081934 TEST=Verified that abuild compiles successfully for all boards. Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08mainboard/google/kahlee: Turn on backlight for all SKUsMartin Roth
Careena uses a different keyboard backlight method, so let the EC handle the different SKUs and backlight methods. BUG=b:80106042 TEST=None Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08src/mainboard/kahlee: Use common mainboard and romstage filesMartin Roth
Until these need to be separated out, use a common file for mainboard and romstage to make upkeep easier. BUG=b:80106042 TEST=Build Grunt and Careena Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08southbridge/intel/lynxpoint: add hard_reset to postcarPatrick Georgi
This fixes the following failure on certain google/peppy configs: build/postcar/lib/reset.o: In function `__hard_reset': /home/pgeorgi/coreboot/src/lib/reset.c:24: undefined reference to `do_hard_reset' Change-Id: I448a8702a30108f1fc82179a766cbdd209336df7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26986 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08mainboard/google/kahlee: Use 66MHz SPI clock for fast readMartin Roth
Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08sconfig/main.c: Fix number of arguments in fprintfMaulik V Vaghela
During compilation sconfig/main.c gives an error regarding number of arguments passed in fprintf. BUG=none BRANCH=none TEST=check if compilation warning has been fixed Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26972 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08arch/x86: Drop leftover ROMCC console supportKyösti Mälkki
Change-Id: I3e52569a34e1f7bfea8be9da91348c364ab705e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-08util/sconfig: Get rid of unused parameter to walk_device_treeFurquan Shaikh
This change gets rid of unused 3rd parameter chips to the function walk_device_tree. BUG=b:80081934 TEST=Verified that abuild compiles successfully for all boards. Change-Id: I255ff030562073b16310fc22a0981808bf2c062f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
Change-Id: Ia637d32ffaa5d280320955d34141eddc8b7df981 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22222 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-083rdparty/libgfxinit: Update submodule pointerArthur Heymans
Update to current master. This includes: - G45 support - fixes scaling on eDP (needed for working textmode on eDP) - gfx_test drawing and moving cursors - Adding support for Tiling on <= Haswell - Allow changes to the framebuffer configurarion without resetting the pipe. Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26823 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI sourceDaniel Kurtz
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake the AP from S3 on keyboard presses. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) press a key on the internal keyboard => system resumes from S3 Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-08amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOsDaniel Kurtz
By default we use a 1:1 mapping between GEVENT bits and the corresponding SCI_MAP entry. However, we still must program the SCI_MAP entries with the GEVENT number. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) move finger on touchpad for ~1 second => system resumes from S3 Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26930 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/octopus: Fix GPIO to GPE mappings in devicetreeFurquan Shaikh
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus variants) changed the GPE mappings to accomodate for WiFi wake pin. However, this resulted in TPM interrupt pin being removed from the GPIO to GPE mapping. Since we do not support true interrupts in coreboot, GPE_STS registers are used to identify if an interrupt has triggered. Change in GPE mapping resulted in this information to be lost when talking to TPM thus resulting in "Timeout wait for tpm irq". This change fixes the above issue by assigning GPIO block for TPM interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to DW3. DW3 was mapped to NW_31_0 which only has debug header pins and CNVI pins (none of them are used for reading GPE_STS or as wake sources). BUG=b:109824918 TEST=Verified that there are no "Timeout wait for tpm irq" messages when talking to TPM. Change-Id: I30768177a838a684948f7485d760c8b83c3190f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-06-07soc/intel/common/pch: Add pch lockdown codeSubrata Banik
pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy: Select right TPM interfaceNaresh G Solanki
TPM over SPI/I2C config selection got changed in https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the same. BUG=None BRANCH=None TEST=Build for Soraka & make sure that TPM is probed over I2C interface rather than SPI. Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26890 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07Makefile.inc: Skip -fconserve-stack flag if running scan-buildMartin Roth
Scan-build refuses to run if the -fconserve-stack flag is added to cflags. It fails with the cryptic message "could not find clang line". Change-Id: Ib1b56ef7d217138a1a195fe993d8e8dd965bd855 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for SonaAmanda Huang
Since there are two cameras on Nami and only one camera on Sona. We need to disable rear camera/DMIC on all Sona sku. BUG=b:109710674 BRANCH=master TEST=Verify if only front camera/DMIC shown on Sona Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for PantheonAmanda Huang
Since there are two cameras on Nami and only one camera on Pantheon. We need to disable rear camera/DMIC on all Pantheon sku. BUG=b:109720689 BRANCH=master TEST=Verify if only front camera/DMIC shown on Pantheon Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07Documentation/release: Add some of the things we added since 4.8.1Patrick Georgi
From here on, changes should directly touch the release notes, but these are notable, too. Change-Id: I602d67f8dd38391663094212cdb4609cdad458ee Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-07console/hw-debug_sink: Do not cache state of log levelNico Huber
As we suppress output now before console_init() is done, the log level read at start of ramstage is always -1. Change-Id: Ia078d647c47aaa41ca9f2df9cf8506148ef86538 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07Documentation: inject the current git revision into the websitePatrick Georgi
Change-Id: I79cceca7373f8bdf9bbfba5d84b8fa589afa838b Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07util/docker/doc.coreboot.org: Add git to the imagePatrick Georgi
Required to get a current version string onto doc.coreboot.org Change-Id: Iac54c4be2d4e783b7bf9ed529a431e72c67abab7 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07util/docker: rename docs.c.o to doc.c.oPatrick Georgi
Make the directory name match the name of the subdomain. Change-Id: I2dcf2385e6d953b7fe02caef72413149a332ec24 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26887 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07util/docker/docs.coreboot.org: reduce container sizePatrick Georgi
We don't need the .deb files in the image forever Change-Id: I67a56faf8f9466e5162f7662708a5abb2971d2f9 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07util/docker/docs.coreboot.org: Downgrade sphinxPatrick Georgi
Sphinx >= 1.6 can't use recommonmark. debian/stable is ancient enough to have an older version. Change-Id: I287deab9168ab6124b05d0c6d6e8cdbd7fdc2eec Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07mediatek: Move uart, timer and cbmem code to a common directory.Tristan Shieh
This patch moves uart, timer and cbmem code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-07mediatek: Refactor to sharing code among similar SOCsTristan Shieh
This patch refactor cbmem and timer code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26881 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mediatek: Refine whitespace and formating changesTristan Shieh
This patch fix whitespace and formating issues: 1. Using two spaces between code and single line comment. 2. No space after asterisk. 3. Fix checkpatch error. 4. Remove spaces after cast operators. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07tint: change the tint download link from HTTP Debian to HTTPS FSFMike Banon
Last time there was a request to change a link from HTTP to HTTPS, also it seems more ethical to use a link to the Free Software Foundation server. SHA1 is the same - 7fcaa428c6d0de7096d1e4fbfd14848096ae5aad. Change-Id: I55147ee2668de03ba6e9feb84936de24b2a001df Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07tint: fix the "Paused - Press any key to continue" message for pauseMike Banon
Earlier this message has not been shown even at the corner of screen. This fixes it by refreshing the screen, and moves it to the center. Change-Id: If4e33e884c00c17f19ab330167d9293c8396ff3e Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07tint: make it possible to reboot by pressing 'q' key two timesMike Banon
Earlier it was impossible to exit without pressing the power button. Change-Id: Ia56d639fa8e563047fb3d2723695626a449ead40 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23853 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07tint: upgrade the outdated tint payload from 0.03b to 0.04+nmu1Mike Banon
Fixes two buffer overflows and opens a road to further improvements. All the previous adjustments to libpayload_tint.patch (including the latest "use the current time as random seed") have been preserved. Change-Id: I22e65d18a0b1551f7049c4afe7f95868f584cf9b Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23852 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07arch/x86/smbios: Conditionally call SMBIOS opsNaresh G Solanki
Check whether device is enabled before calling smbios ops. BUG=None BRANCH=None TEST=Build & boot Soraka. Change-Id: I79681c10679e1de3a2d177503f29239968d0c157 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07google/chromeec: Set proper dev opsNaresh G Solanki
For enable_resource & set_resource, use default DEVICE_NOOP so that they are not reported as missing during enumeration. BUG=None BRANCH=None TEST= Build & boot soraka. Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07util/lint: Add filename checkerMartin Roth
Check that filenames have only alphanumeric characters plus underscore, dash, and period. Change-Id: I7bf0be15d588aa1a5ece628b56e871662d6af44b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07Documentation: Rename file with space in filenameMartin Roth
Change-Id: I10203de578c4dd0b8915dad4b0d456531049328f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06mb/google/octopus: Update GPIOs as per latest schematicsFurquan Shaikh
Update GPIOs in baseboard to match latest schematics: 1. Get rid of STEST GPIOs(GPIO_{62,84-89}) 2. Get rid of SD_CD_ODL(GPIO_134) 3. Get rid of KB control GPIOs(GPIO_{144-146}) 4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the configuration for other pen GPIOs. BUG=b:109764138 Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26874 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06mb/*/*: Add a few VBT filesArthur Heymans
These files are directly extracted from the vendor firmware. Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06drivers/intel/gma: Include mainboard data.vbtArthur Heymans
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path to point to the mainboard dir and to select INTEL_GMA_ADD_VBT_DATA_FILE by default. Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06arch/x86: Always select RELOCATABLE_MODULESKyösti Mälkki
All boards except those with NO_RELOCATABLE_RAMSTAGE or explicit select already had this feature built. Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
Choose codepath as if ROMCC_IF_BUG_FIXED was set. Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06Documentation/releases: Add release notesMartin Roth
This adds the release notes for all of our old releases that have notes to the documentation directory. The release notes for the next release, 4.9 is added here as well. I would request that people document their changes for the next release themselves if they wish them to be in the release notes. Change-Id: I7440a3130f2f7d80c4434d2b5a918e62bbd08fbb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06mb/lenovo: Add ThinkPad W530 supportEvgeny Zinoviev
Tested and working: - Wi-Fi - Ethernet - WWAN ? (interface is created in linux, didn't actually test it, should work) - Bluetooth - Speakers - Internal mic - SD card reader - Suspend and resume - Keyboard, touchpad, trackpoint - Fan - Webcam - 4 RAM slots - All USB ports - mSATA - VGA ROM (FIXME: black screen after resume from s3) - Native graphics initialization (FIXME: probably incorrect panel frequency, etc. in GRUB; in linux everything's fine incl. resume from s3) - libgfxinit - GRUB payload - SeaBIOS payload - Internal flashing using flashrom Not tested yet: - Fingerprint reader - Colorimeter - Smart card reader - Docking station - VGA output - Optical disc drive - Discrete graphics TODO: - Test BDC detection Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/26136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
To flip the Kconfig default, flag some platforms with NO_RELOCATABLE_RAMSTAGE. Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Use fixed size limit with RELOCATABLE_RAMSTAGEKyösti Mälkki
With RELOCATABLE_RAMSTAGE, variables RAMBASE and RAMTOP have no meaning any more. Change-Id: I711fe98a399177c2d3cb2a9dcdefba61031fb76d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06hp/compaq_8200_elite: Fix TPM not visible in OSPatrick Rudolph
Chip sections must be covered by a PCI device. Fixes chip_ops not being executed and TPM shows up in OS. Change-Id: Id0ecd2f2f3e303f2228743369a8025b327bee61d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06mb/google/octopus: Fix invalid IOSSTATE settings for 1.8V pinsShamile Khan
When the normal termination is None, the standby termination is none also as per Doc# 572688. So when termination is only needed in standby, use the IOSSTATE setting that drives low/high via the Tx mode instead. Also disabled Speaker in Standby state to save power. BUG=b:79874891, b:79982669 BRANCH=None TEST=Compiled and flashed image on Bip. Checked that suspend_resume cycles pass. Checked that bluetooth is functional on resume. On Yorp, checked that speaker is functional after a suspend/resume cycle. Change-Id: I6a3852548f944176a80feb32e9885b03b8af25db Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06mb/google/poppy/variants/atlas: update HP IRQ pin's pad configSathyanarayana Nujella
Issue observed on the board is: too many jack interrupts. cat /proc/interrupts | grep da7219 58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad Updated pad configuration for Jack IRQ pin to fix the issue. BUG=b:109655907 TEST=Jack insertion & removal detection is working. Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/poppy/variants/nami: Add delay to enable_gpio during Elan power onShelley Chen
During measurement of signals during Elan touchscreen power on, saw that the enable_gpio delay was not sufficient as there is a +1.5 ms delay during power on. Adding more delay to take this into account. BUG=b:78311818 BRANCH=None TEST=probe power on signals to ensure meet timing requirements Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/poppy/variants/nami: Fix Elan touchscreen power off sequenceShelley Chen
Power off does not seem to use the ACPI _OFF function, but rather the smihandler. Creating variant_smi_sleep function for nami to handle the power off sequence during reboot/power off. BUG=b:78311818 BRANCH=None TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled Make sure delays are consistent with spec Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06arch/x86: Drop leftover ROMCC supportKyösti Mälkki
Remove the last bits of building romstage with romcc. Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cbNaresh G Solanki
Name i2c device structure based on that in devicetree.cb Now log looks like: I2C: 01:0a (WCOM Touchscreen) I2C: 03:13 (Realtek RT5663) I2C: 03:39 (SSM4567 Right Speaker Amp) I2C: 03:3a (SSM4567 Left Speaker Amp) BUG=None BRANCH=None TEST=Build & boot Soraka Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06cpu/intel/model_{6xx,f2x,f3x,f4x}: Remove unneeded includeElyes HAOUAS
Change-Id: I7d5843aada364b557e0618268ad48c650aa54d1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-06soc/intel/common/block: Move i2c common functions into block/i2cSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/i2c. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Move gspi common functions into block/gspiSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/gspi. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNLSubrata Banik
This patch creates a glue layer between SOC and common block IPs in terms of PCH. All common IP blocks now can be selected based on SOC_INTEL_COMMON_PCH_BASE config option. BUG=none BRANCH=b:78109109 TEST=Build and boot Cannonlake RVP and EVE. Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/pch: Make infrastructure ready for pch common codeSubrata Banik
This patch is intended to make Intel common PCH code based on Gen-6 Sunrisepoint PCH (SPT). All common PCH code blocks between Gen-6 till latest-PCH should be part of soc/intel/common/pch/ directory. A SoC Kconfig might select this option to include base PCH package while building new SOC block. Currently majority of common IP code blocks are part of soc/intel/common/block/ and SoC Kconfig just select those Kconfig option. Now addition to that SoC might only selects required base PCH block to include those common IP block selections. BUG=none BRANCH=b:78109109 TEST=soc code can select PCH config option Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/octopus: Enable wake-over-wifi for octopus variantsFurquan Shaikh
This change enables wake-over-wifi functionality for all octopus variants by making the following changeS: 1. Configure GPIO_119 as SCI active-low 2. Update GPE0_DW1 to include the group that GPIO_119 falls under 3. Add wake property to wifi device BUG=b:77224247 TEST=Verified that wake-over-wifi works on yorp. Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06soc/intel/apollolake: Add missing entries to pmc_to_gpio_route for GLKFurquan Shaikh
This change adds missing entries in PMC to GPIO route mapping for GLK. BUG=b:77224247 Change-Id: I66cadaa23b8bd4518a199733c8fba81168e60323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06soc/intel/apollolake: Fix macro name for GPIO_GPE_NW group 2Furquan Shaikh
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit 64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect this. BUG=b:77224247 Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Get rid of nextdev member in struct deviceFurquan Shaikh
Now that chips and devices are treated differently and the device tree actually contains only devices, next and nextdev are exactly the same for all devices in the tree. This change gets rid of nextdev pointer and updates all uses of nextdev to next. BUG=b:80081934 TEST=Verified that static.c generated for all boards built by abuild is same with and without this change. Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Get rid of struct headerFurquan Shaikh
Now that chips and devices are treated differently in sconfig, this change gets rid of struct header and add_header function which were responsible for maintaining list of headers that need to be added to static.c. Instead, struct chip is re-factored into struct chip and struct chip_instance, where chip is a list of unique chips required by the mainboard whereas chip_instance is an instance of the chip. One chip can have multiple instances dependending upon the devices in the system. Also, struct device is updated to hold a pointer to chip instance instead of the chip structure. This unique list of chips is then used to add appropriate headers to static.c BUG=b:80081934 TEST=Verified using abuild that all boards compile successfully. Change-Id: I6fccdf7c361b4f55a831195adcda9b21932755aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26739 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05util/sconfig: Add helper function for allocating memoryFurquan Shaikh
Add a helper function s_alloc (sconfig alloc) that allocates memory using calloc to get 0 initialized memory and checks to ensure it is not NULL. BUG=b:80081934 Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Get rid of bus pointer in device structureFurquan Shaikh
The only reason bus pointer existed in device structure in sconfig was to allow a node to point to the parent which could be a chip and bus which is the true parent in device tree hierarchy. Now that chip is no longer a device, there is no need for separate bus and parent pointers. This change gets rid of the redundant bus pointer in struct device in sconfig. BUG=b:80081934 TEST=Verified that static.c generated for all boards built by abuild is same with and without this change. Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Re-factor emitting of headers to static.cFurquan Shaikh
This change removes call to add_header from parsing functions and moves it to a local function within main.c. It also adds a new function emit_headers that is responsible for creating the linked list for chip headers and emitting those to static.c BUG=b:80081934 TEST=Verified that static.c for all files compiled using abuild is the same with and without this change. Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Re-factor sconfig to not assume chip as deviceFurquan Shaikh
This change adds a new structure "struct chip" to identify elements of type chip rather than re-using the structure for device. Until now chip was treated as a device while generating the parse tree and then device tree postprocessing skipped over all the chip entries in children and sibling pointers of device nodes. With this change, the device tree will only contain struct device in the parsed tree. It helps by avoiding unnecessary pointers to chip structure as children or next_sibling and then skipping those elements in post processing. Every device can then hold a pointer to its chip. When generating static.c, chip structure is emitted before device structure to ensure that the device structure has chip within its scope. Externally, the only visible change in static.c should be the order in which chip/device elements are emitted i.e. previously all chips under a particular device were emitted to static.c and then the devices using those chips. Now, all chips are emitted before all the devices in static.c BUG=b:80081934 TEST=Verified that abuild is successful for all boards. Also, verified that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is unchanged from before in node definitions. Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05mb/google/poppy/variants/nami: Disable rear camera/DMIC for vayne skuid 3A67Van Chen
Since Vayne added one more skuid 3A67, we need to disable rear camera/DMIC for vayne skuid 3A67. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera/DMIC shown on Vayne Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26855 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/{apollolake, geminilake}: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for APL and GLK. Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05soc/intel/cannonlake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for CNL. Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05soc/intel/skylake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05northbridge/amd/lx: Fix function setShadowRCONFIru Cai
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical `&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise `&`. Also fix off-by-one error with the bitmasks. Change-Id: I7d7720121d4730254542372282f5561739e7214b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20808 Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05amd/geode_lx: Fix .c includesKyösti Mälkki
Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2018-06-05amd/geode_lx: Remove most boardsKyösti Mälkki
There is active work to convert remaining two boards, PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT. Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans
Tested on Google Peppy (Acer C720). Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26793 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans
Also removes some non-POSTCAR_STAGE functions, since those are unused now. Change-Id: I439bffbe39411186355d374eed7d5efd63fb02e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26792 Reviewed-by: Matthias Gazzari <mail@qtux.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin. Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05cpu/intel/car/non-evict: Improve a few thingsArthur Heymans
This improve the following: - Improve readability for clearing fixed MTRR's - Compute PHYSMASK high during runtime - Cache the whole ROM_SIZE instead of XIP_ROM_SIZE Change-Id: Ifaed96b41fab973fa541de1c4f005d6f0af5254f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE supportArthur Heymans
Prepare a common cache as ram for CPU's featuring a Non eviction mode MSR. Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26789 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26788 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05cpu/intel/car/core2: Improve a few thingsArthur Heymans
This changes the following: - compute amount variable MTRR's during runtime - Wait for all CPU's to be in Wait for SIPI state after sending init INIT IPI to all AP's - compute the PHYSMASK high during runtime and preload it to the MTRR_PHYS_MASK msr's Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 13:46:26 +0000