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2019-02-15SMBIOS: Update BIOS Information (Type 0) to version V3.2.0Elyes HAOUAS
Add Extended BIOS ROM Size field. Change-Id: Iec35c8c66210f0ddc07a2ca6f976a1f8fc53037d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-15SMBIOS: Add new MEMORY_{TYPE,TECHNOLOGY,OPERATING} macrosElyes HAOUAS
Change-Id: I4e466614d0a9e8c89f298594a5785af775b22a95 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-02-15include/smbios.h: Align values for readabilityElyes HAOUAS
Change-Id: I362292e95557586e0e24a62a12a9ccc98143ef9c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-15Documentation: Add KASAN to the project ideas listWerner Zeh
Adding the Kernel Address Sanitizer feature to coreboot would help to find bugs. Change-Id: If00010e81147ec50e037678230df17c6888e40a2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15soc/amd/common: Move PI refcode loaderKyösti Mälkki
The moved functions are only about locating and loading the refcode blobs. Separate them from the actual calls into the blob. Eventually previous binaryPI blobs should be unified to share same loader code. Change-Id: I68885e7f855b195c178e746c8f3f0f49166d0def Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-15crossgcc: Update binutils to version 2.32Elyes HAOUAS
Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15mb/google/hatch: Enable DPTF functionalitySumeet Pawnikar
Enable DPTF functionality on hatch platform. Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15SMBIOS: Update BMC Interface Type fieldElyes HAOUAS
Change-Id: I68a8515adf5b29a080f8c5c5b7a96b28bca74676 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-02-15soc/amd/stoneyridge: Expand 48MHz for both osc out signalsRichard Spiegel
There are typically two configurable oscillator outputs available on APUs or FCHs. Convert the enable function to work with either one. BUG=b:none. TEST=Build and boot grunt. Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-15src: Use macro `ACPI_FADT_LEGACY_FREE`Paul Menzel
Replace all instances, where 0 is used by the macro/define `ACPI_FADT_LEGACY_FREE`. Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/31289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-15soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11Kane Chen
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors. BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15soc/intel/cannonlake: Define VR settingsRoy Mingi Park
Define VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/31405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-15mb/google/octopus: Fix USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix the device configuration in the devicetree. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15drivers/i2c/max98373: Set default bus speed as I2C_SPEED_FASTFurquan Shaikh
This change sets default bus speed as I2C_SPEED_FAST instead of I2C_SPEED_STANDARD when board does not provide any speed. This makes it similar to all other i2c drivers in coreboot. BUG=b:124403846 BRANCH=nocturne,atlas Change-Id: I877d837eea2dfebf78ad7d97a32ee2071500625e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-15mb/google/sarien: Set ELAN as the default for touch panelChris Zhou
According to request of comment 35, setting ELAN as the default. BUG=b:122019253 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945 Reviewed-on: https://review.coreboot.org/c/31430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-15mb/google/sarien/variants/sarien: Enable Elan touchscreenChris Zhou
Eanble Elan touch for sarien EVT build BUG=b:119763054 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a Reviewed-on: https://review.coreboot.org/c/31413 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-14binaryPI: Fix cache coherency use for AP CPUsKyösti Mälkki
The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-14superio/nsc/pc87417: Use common early_serialPeter Lemenkov
Change-Id: If32fa5970ca7ca634833a0e39da66c1f89ed33fe Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-14superio/nsc/pc87366: Use common early_serialPeter Lemenkov
Change-Id: I1f03182cd760ea63df78ef3e2b2604c3322b4f3f Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-14superio/nsc/pc87360: Use common early_serialPeter Lemenkov
Change-Id: Id866c30d676e3c3ff53bfc2547abffce6e9b5e07 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-14superio/nsc/pc87309: Use common early_serialPeter Lemenkov
Change-Id: If856ec6d5bcf4951d0e09464526239f5a508d4b0 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-14superio/nsc/pc87392: Use common early_serialPeter Lemenkov
Change-Id: I9437ee3f8830dc831aacfc62b9dd1943b73b98d4 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31333 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-14superio/nsc: Introduce common early_serialPeter Lemenkov
Change-Id: I0860e95258b87f059a3a9c31e382d758403d0428 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-14util/ifdtools: Make EC region readable to BIOS/CPUBora Guvendik
Allow EC region to be readable by BIOS/CPU so that flashrom can read it. BUG=b:123199222 TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, run firmware_LockedME test. Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/31377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13mb/google/hatch: Bump up the BIOS region to 28MiBFurquan Shaikh
This change bumps up the BIOS region to 28MiB to use the hole between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only the top 16MiB actually gets memory mapped. Thus, the change ensures that only RW_LEGACY lies in the 12MiB that is not memory mapped. BUG=b:123443737 TEST=Verified that hatch still boots up. Ensured that fmap dump looks correct. Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-13mb/google/poppy/var/rammus: Enable mode change wake source for S3/S0ixFurquan Shaikh
This change enables mode change as a wake source for S3 and S0ix. Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-13soc/intel/cannonlake: Configure serial debug uartRonak Kanabar
Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose The default value of SerialIoDebugUartNumber is 2 by default it selects UART 2 so it needs to be initialized as per board config BUG=b:123702398 Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31375 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13mb/google/sarien: Support multiple touchscreen at same addressDuncan Laurie
The Sarien board may have different touchscreen devices that use the same I2C slave address but have different requirements such as needing a special driver or ACPI configuration. In order to support this the devicetree may be configured with multiple devices at the same address and at boot time the unused devices will be disabled. Because there is no GPIO for selecting the device that is present it can instead be selected with Kconfig, or by setting a VPD key to the HID of the touchscreen device that is present. The default for Sarien devices is to not enable a touchscreen for the OS. The touchscreen selection is currently limited to the Sarien variant but this also adds the touchscreen HID for Arcada to Kconfig so it would not complain about the key not being set. BUG=b:122019253 TEST=This was tested on a Sarien board by adding a second entry to the devicetree at the same address. Without this change the SSDT is not loaded by the kernel because of the address conflict. After this change no touchscreen is enabled by default, but one can be selected with Kconfig or by setting the 'touchscreen_hid' VPD key. Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1John Su
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H15 for DVT1John Su
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1. BUG=b:123342945 TEST=Built and tested on sarien system Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13coreboot: check Cr50 PM mode on normal bootKeith Short
Under some scenarios the key ladder on the Cr50 can get disabled. If this state is detected, trigger a reboot of the Cr50 to restore full TPM functionality. BUG=b:121463033 BRANCH=none TEST=Built coreboot on sarien and grunt platforms. TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and then the platform boots normally. TEST=Performed Cr50 rollback to 0.0.22 which does not support the VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and the coreboot log captures the unsupported command. Tested-by: Keith Short <keithshort@chromium.org> Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13mb/google/hatch: Configure GPIO pad for non-inversionAamir Bohra
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16) pad in non-inversion mode i.e Rx PAD state is not inverted as it is sent from GPIO to IOAPIC. BUG=b:123315212 TEST=Tested for below: -> Verify touchpad is working fine. -> TPM init is successful and boot with fixed boot media. Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-13cpu/intel/common: Add Nehalem for FSB detectionKyösti Mälkki
Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31339 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13cpu/intel/common: Split get_ia32_fsb()Kyösti Mälkki
It is desireable to not have printk() inside a function body that can be used for udelay(). This avoids potential infinite recursion. Change-Id: Ie67fc2a8da8351f22794e4d36c55b887c298e8ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-13soc/intel/icelake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-13soc/intel/baytrail: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30511 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13soc/intel/broadwell: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Idca207b4f05d1844ce6612dbecaad6faeb68725a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-13soc/intel/cannonlake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-13libpayload/sys/types.h: Add definition for off_tNico Huber
`off_t` is supposed to be signed, but has no (minimum) width specified. We'll assume 32-bit minimum, like a `signed long int`. Also include `sys/types.h` in `libpayload.h` so everything is available through the latter. Change-Id: I6c0c1bc1a959db7863cbad2ba29318da162431be Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4Uwe Poeche
This patch enables TPM2 on LPC and adds the needed devicetree entry for TPM for mc_apl4. Test=mc_apl4 flashed, booted into Linux and checked via dmesg if TPM is present Change-Id: I9af7e1a8623302eca46f5ecd8e498678ccda92ad Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/31344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-13siemens/mc_apl2: Remove double entry from devicetreeMario Scheithauer
Remove a double entry for LPC device from devicetree. Change-Id: Ib5b4f760251236d6a8b4aba719666daa97e7813d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-13riscv: Add initial support for 32bit boardsPhilipp Hug
* Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage. This should probably be changed later. TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands: util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-02-12cpu/x86/mtrr: Fix _FROM_4G_TOP() macroNico Huber
This macro was unnecessarily complex. Trying to avoid an overflow for unknown reasons, and instead shifted the result into the sign bit in C. Using a plain number literal that forces C to use an adequate integer type seems to be safe. We start with 0xffffffff, subtract `x` and add 1 again. Turned out to be a common pattern and can't overflow for any positive 32-bit `x`. Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-12sb/intel/common: Remove CAR_GLOBAL useArthur Heymans
We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30506 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12nb/intel/nehalem: Remove CAR_GLOBAL useArthur Heymans
We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30505 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12postcar: Make more use of postcar_frame_add_romcache()Nico Huber
Some similar calls to postcar_frame_add_mtrr() were added in the meantime or were under review while postcar_frame_add_romcache() was introduced. Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-12binaryPI: Drop nested northbridge in devicetreeKyösti Mälkki
SPD data needs to remain within same chip -block with device 0:18.2. Change-Id: Ic12481b637ee5f5119faec3239b477f613e4e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-12mb/google/octopus/casta: Tune usb2eye settingSeunghwan Kim
It needs to tune usb2eye setting for these ports: USB2[4] - type-c port USB2[6] - camera BUG=b:122878632 BRANCH=octopus TEST=built and passed usb2eye SI test Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12soc/amd/common: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I422d5637caa1b55fa6bad30d25f5e34cbba40851 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-12soc/amd/common: Remove redundant ACPI S3 testKyösti Mälkki
Possible allowance to do wakeup is already evaluated early in romstage, so these tests are redundant. Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/27276 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12google/kahlee: Remove unneeded HAVE_ACPI_RESUME guardKyösti Mälkki
We leave it to linker garbage collection to drop unreferenced code and symbols from final object files. Function declarations and definitions are to be guarded with preprocessor directives only as a last resort. Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-11soc/intel/bdw: Remove spurious commentNico Huber
Change-Id: I45f2ca809a6acfcb80a742d29c045d04888e4d7f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-11libpayload: add memchr to libcPhilipp Hug
libfdt requires memchr. Add missing function to libc. Change-Id: I872026559d16a352f350147c9d7c4be97456a99f Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-11device/pci_ops: Apply some symmetry in headersKyösti Mälkki
To make PCI driver side arch-agnostic, function declarations have to be in symmetrical header file locations. From the driver side, the correct file to include is now <device/pci_ops.h> Change-Id: I8076a4867fd7472beaae0a021dcf0d9c7c905871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-11device/pci_ops: Move common pci_mmio_cfg.hKyösti Mälkki
It is expected that method of accessing PCI configuration register space via memory-mapped region is arch-agnostic. Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-11mb/intel/galileo: Drop the FSP1.1 optionArthur Heymans
This board is EOL and has FSP2.0 support, so drop the older version. Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-11soc/intel/baytrail: Use non-evict CAR setupArthur Heymans
The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this. Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-11Revert "cpu/x86/mtrr: Fix sign overflow"Nico Huber
This reverts commit 6bbc8d8050b1d51ec4bf15003a2da54e20d476c7. The macro is used in assembly where integer suffixes are not portable. Also, it is unclear how this can overflow as it's already the macros purpose to avoid the overflow. Change-Id: I12c9bfe40891ae3afbfda05f60a20b59e2954aed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-11ec/lenovo/h8/Kconfig: increase ps2 kbd timeout from 3000 to 5000msMichael Bacarella
On my Thinkpad T420 the default 3000ms SeaBIOS timeout is too short, it takes nearly 5000ms for my keyboard to become ready. Timing out before it's ready leads to pretty bad behavior: I cannot use my keyboard at all to control SeaBIOS, nor the subsequent GRUB instance. Linux is fine though, possibly because it does its own keyboard init. Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2 Reviewed-on: https://review.coreboot.org/c/31279 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11soc/intel/fsp_broadwell_de: Move FSP_DEBUG_LEVEL option hereNico Huber
It is not mentioned in the FSP spec and doesn't seem to be implemented for any other FSP than the Broadwell-DE one. Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-11mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQEdward Hill
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. On this platform, interrupts are routed via the GPIO controller so need to be registered using GpioInt instead of Interrupt. BUG=b:123750725 BRANCH=grunt TEST=MKBP events still received (with matching EC and kernel changes) Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-11Documentation: remove the upcoming events chapter from the conferences pageMartin Kepplinger
I think our docs inside of the codebase might not be the ideal place to announce future events. First, they might be scheduled so shortly before the conference that the change, if at all done, would barely make it to the repo and the web. Also, _if_ really maintained, it would churn the docs unnessesarily. But, I doubt that anyone of us would want to maintain this here at all. Lastly, I think that nobody out there would _look for_ upcoming events in coreboot's documentation. We have bigger problems in the Documentation directory than this :) Change-Id: I918e17a427405a05722c6e0d61dc422f94cac809 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31266 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11Documentation: add the most recent talks to the conferences pageMartin Kepplinger
Add Philipps great 35c3 talk and Davids and Andreas fosdem talk to the conferences page. linuxboot adds those to their website too but they can't be linked to too often :) Change-Id: I1e7ce078020dc5e9c9d9d47210c70ee16ef2f82e Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31265 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11Documentation: add link to chromebookdb.com to distribution pageMartin Kepplinger
As suggested by Philipp, let's add this link. Change-Id: I6ff21f37a04dc5a9c3db1ff7ac9a786fb0b51211 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-11Documentation: add the Heads project to the list of distributionsMartin Kepplinger
As this is a unique, actively maintained project, we should probably point there too. The text is just copied parts of the http://osresearch.net/ website. Change-Id: Ib2a8e4b28bc94c5dc6a1ae9388f96ad2c502ccab Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11amd: Remove unused definesPeter Lemenkov
grep -ER \(FAM10_SCAN_PCI_BUS\|FAM10_ALLOCATE_IO_RANGE\) shows nothing. Change-Id: Id0d321c80a9a393fcc0d9c2a5a675dba48516160 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31288 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11src/mainboard/pcengines/apu2/OemCustomize.c: Enable CPB featureMichał Żygowski
Enable Core Performance Boost feature in automatic mode. Also enable C6 state which is a dependency for proper CPB operation. CPB allows to raise single core frequency from 1000MHz to 1400MHz during high load if other cores idle. The processor has additional boosted P-states when CPB is enabled, but these are hidden from OS. TEST: Higher single-core CPU performance is indicated by increased memory bandwidth as reported by memtest86+. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2 Reviewed-on: https://review.coreboot.org/c/31229 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11device/pci_ops: Move questionable pci_locate() variantsKyösti Mälkki
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>. There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-11device/pci_early.c: Drop some guardsKyösti Mälkki
With PCI_DEV() always defined it is no longer necessary to exclude this code from building. Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-11device/pci: Always define PCI_DEV()Kyösti Mälkki
This has uses outside ARCH_x86 and/or __PRE_RAM__. Change-Id: I2eec674ec5ba4ffe03a20db0f73cf87e5e4b4d0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-10arch/x86: Drop stale commentKyösti Mälkki
Change-Id: I1ba6dfb502ff053ccf82d2acc5fefbbfe09d647b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31294 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-10nb/via/vx900: Replace pci_mod_configX()Kyösti Mälkki
If clr_mask == 0, use pci_or_configX(). If clr_mask != 0, invert mask and use pci_update_configX(). Change-Id: I4ae64e9b635b3759e4cffc4bbdf029411a4e0f42 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31272 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-10cpu/intel/car/*/cache_as_ram.S: Add brackets around operandArthur Heymans
Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31291 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-10sb/amd/sb800: Drop comments about pci_locate_device()Kyösti Mälkki
Change-Id: I28a32d5c6dee792b6882e7ff45be6339016ad6ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-10arch/x86: Drop some ROMCC remainsKyösti Mälkki
Change-Id: I62da8d0461774db8256e82deae0d5fe075f3faed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-10nb/intel/sandybridge: Use pcidev_on_root()Kyösti Mälkki
Change-Id: I959dfd1c10bc1ab85c6392e0090b022934468770 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31292 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-09riscv: Use correct argument in a1 when invoking payloadPhilipp Hug
Fix a bug introduced by: 820dcfceb3901dbb00bb90c876e374126ca14e20 riscv: Simplify payload handling Put fdt into a1 correctly. Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31287 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08mb/google/hatch: Replace part-specific SPD files with generic onesShelley Chen
Traditionally, we have always allocated 1 DRAM ID per part number. However, on nami, we have run out of DRAM IDs because we have supported so many different parts. We are now adopting the use of generic SPD files that are feature-based rather than specific to each part, allowing us to support multiple parts with a single SPD. The common SPDs were created by taking current SPDs in Nami (which is using the same DDR4 parts as Hatch) and zeroing out all the manufacturer information and part names. Additionally, we zeroed out bytes 128 (raw card extension, module nominal height), 129 (module maximum thickness), and 130 (reference raw card used) after verifying that they are not used in FSP. We verified with these fields zeroed out, all nami devices could boot up without errors. We also verified on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic SPDs boot properly. BUG=b:122959294 BRANCH=None TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4 devices that we currently have. Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08x86/acpi: Use PM_TABLET where appropriateDuncan Laurie
Instead of having SYSTEM_TYPE_DETACHABLE and SYSTEM_TYPE_TABLET use PM_MOBILE have them use PM_TABLET instead. Change-Id: If0ce51e522d36420ecd5b51bdfec6cca11c00333 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-08cpu/intel/model_1067x: Check for lock bit on IA32_FEATURE_CONTROLArthur Heymans
df7aecd "cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR" introduced a regression because it unconditionally writes to IA32_FEATURE_CONTROL, which if it is already locked results in an unhandled exception. The lock bit is already set on a system reboot. Change-Id: I7d2df9e1b9d767809da7a61ccd877c6c40f132eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31255 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08mb/ocp/wedge100s: Fix devicetreePatrick Rudolph
Match devicetree what's present and in use. Tested on wedge100s: All PCI devices show up. Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-08mb/{asrock,intel,kontron}: Include missing <arch/io.h>Elyes HAOUAS
Also includes lines sorted Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31267 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08drivers/gpio_keys: Remove redundant is_wakeup_source flagKarthikeyan Ramasubramanian
"is_wakeup_source" flag is used to indicate if the concerned device can trigger a wakeup. This flag is redundant with the "wake" GPE event definition. So remove the redundant flag and use the "wake" GPE event to mark the wakeup source. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source in SSDT if wake GPE is configured. Ensure that the system can suspend and the device acts as a wakeup source Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08mb/*/*/romstage: curly braces after the function definitionPeter Lemenkov
See Documentation/coding_style.md, specifically "Placing Braces and Spaces" section. Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-08drivers/keyboard: Fix spelling of *interface*Paul Menzel
`git grep iterface` shows that these are the only two occurrences. Change-Id: I838a60c95c5d0fc3dee902f0b72761dd60c36221 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/31286 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-07Documentation: Mention PC Engines as ships-with-coreboot hardwarePatrick Georgi
Change-Id: I9d57abcff9c2472cc58b7fbca00441cd38a7f1a1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-07mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_padsFurquan Shaikh
This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-07soc/intel/cannonlake: Configure GPIOs again after FSP-S is doneFurquan Shaikh
FSP-S is currently configuring GPIOs that it should not. This results in issues where mainboard devices don't behave as expected e.g. host unable to receive TPM interrupts as the pad for the interrupt is re-configured as something else. Until FSP-S is fixed, this change adds a workaround by reconfiguring GPIOs after FSP-S is run. All mainboards need to call cnl_configure_pads instead of gpio_configure_pads so that SoC code can maintain a reference to the GPIO table and use that to re-configure GPIOs after FSP-S is run. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-07soc/intel/cannonlake: Add Whiskeylake SoC kconfigSubrata Banik
This patch performs below tasks 1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig. 2. Allow required SoC to select this kconfig to extend CANNONLAKE SoC support and add incremental changes. 3. Select correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC 4. Add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-06Makefile.inc: Create a default SMMSTORE regionArthur Heymans
Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06Makefile.inc: Make sure the BIOS region is 64K alignedArthur Heymans
If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and CONSOLE could end up non aligned. Currently this is only possible if the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be safe than sorry. Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30420 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06Makefile.inc: Optimize generating the default x86 fmapArthur Heymans
Put the FMAP FMAP region right above the coreboot CBFS region. The other regions like RW_MRC_CACHE and CONSOLE often have alignment requirements so it makes sense to put those on top. This also simplifies the code the generate the default fmap a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30419 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06mb/google/hatch: Configure I2C busesFurquan Shaikh
This change enables I2C bus 2, 3 and 4 in devicetree and configures GPIO pads for the same. It also configures pads for I2C5 as no-connect. BUG=b:123711244 TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS. Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31237 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06mb/google/reef: Expand the coreboot RO sectionMathew King
Current coreboot size is not adequate for adding new features. Note for cros: This change is for merge to ToT only and should not be cherry-picked into reef's firmware branch. BUG=chromium:903833 TEST=emerge-reef coreboot Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/31230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-06libgfxinit: Add options to limit framebuffer sizeNico Huber
Add maximum width and height options and set the default to 2560x1600 (WQXGA). The framebuffer will be scaled up to the displays' native resolutions. So this should help with tiny fonts on high-DPI displays. For laptops, reasonable defaults can be set at the mainboard level. Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06Hook up Kconfig Ada spec fileNico Huber
We generate a $(obj)/cb-config.ads once and copy it per stage that uses it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The Ada package is called `CB.Config`. As there was no `CB` package yet, add that too. Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-06Documentation: update/improve distribution listingMatt DeVillier
- improve descriptions of Purism and ChromeOS hardware - add entry for Libretrend Librebox - improve description of Mr Chromebox and John Lewis' 3rd party ChromeOS firmware offerings Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-06nb/intel/gm45: Use a common romstageArthur Heymans
This moves a lot of the common romstage boilerplate code to a common location, while adding a few mainboard specific hooks. Another difference is that the settings for enable_igd and enable_peg are now based on the static devicetree settings. Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-06mb/lenovo/x200/gpio.c: Unclutter the codeArthur Heymans
Some settings don't make sense like specifying input/output on native ports or high/low on input ports. Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31187 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 19:21:59 +0000