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2018-01-17AGESA f15 boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
Boards that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Removed boards: amd/dinar tyan/s2886 supermicro/h8scm supermicro/h8qgi Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-17soc/intel/cannonlake: Add option to select FSP_CARSubrata Banik
This patch provides an option for non-chrome devices to make use of FSP-T for performing cache-as-ram initialization. Majority of IOTG users are using FSP-T for CAR implementation and aren't able to select FSP_CAR Kconfig from SoC without conflicting with existing CAR config. TEST=Ensure that both the Chrome platform and non Chrome OS platform can select either CAR implementation based on Kconfig options FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose FSP_CAR by default. Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16soc/intel/cannonlake: Program DMI PCR settingsLijian Zhao
According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16soc/intel/apollolake: Set ACPI_FADT_LOW_PWR_IDLE_S0 for S0ixShaunak Saha
This patch sets the ACPI FADT flag ACPI_FADT_LOW_PWR_IDLE_S0 if S0IX is enabled for the platform. TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table. Change-Id: Ibb43d5c8024dcdf753416e4bd2a457991cc7a433 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i5000 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i5000 Mainboards: mainboard/supermicro/x7db8 mainboard/asus/dsbf Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i855 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i855 Mainboards: mainboard/lanner/em8510 Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel sch board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/intel/sch Mainboards: mainboard/iwave/iWRainbowG6 Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/dmp/vortex86ex Mainboards: mainboard/dmp/vortex86ex Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15AMD GX2 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15mb/google/poppy/variants/nami: Enable elan touchpadvan_chen
BUG=b:71838954 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: Elan Touchpad Change-Id: I14471d1473a3b3ecf15aaf362b47874704cd3bf0 Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-15payloads: add support lz4 compressionAntonello Dettori
Add the option to use the lz4 compression method to compress payloads. Also sets LZ4 as the default compression method. Change-Id: Ic712f984f791d268440c8463eaea0d246aa31d99 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15inteltool: Dump Sunrise Point PCH-H GPIO groupsNico Huber
Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15inteltool: Support for nasty Primary to Sideband Bridge (P2SB)Nico Huber
The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15buildgcc: Add patch to work around Musl libc issueNico Huber
GCC includes `sched.h` after poisoning calloc(). This results in a build failure with Musl libc. We work around the issue by including `sched.h` earlier and throw around some void pointers so we only have to do it in one place. Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-01-15buildgcc: Drop libelf/elfutilsNico Huber
Looks like we were unnecessarily dragging this around for some time now. GCC's installation manual doesn't mention libelf as a requirement and a build of crossgcc-i386 doesn't show any sign of it being used. This also fixes a lot issues on non-GNU distributions that were intro- duced by switching to the elfutils version of libelf. Change-Id: Iff308a9bed9ae3842557d251b75d1faadfafe0da Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/crossgcc: Output apt-get commands on debianAlex Thiessen
In the buildgcc script, there is a check that the tools required are installed. When a tool is missing, a message is output suggesting an installation method, e.g. `sudo apt-get install foo` on debian-based systems. When run on a true, vanilla debian system, the error message provides only a generic hint because the `please_install()` function fails to detect the OS kind. Detection is based on definition of `ID_LIKE` in `/etc/os-release` yet such systems only define `ID` to `debian`. This commit closes the detection gap. Tested on debian 9 (stretch). Change-Id: I3c867837e9157bee13010bd0a005028c369ce55f Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15mb/lenovo/x200/dock.asl: Issue DOCK ACPI events based on Dock IDArthur Heymans
Some Dock events only need to happen based on the Dock Id (which functions as a presence detect GPIO). Inspired by vendor bios DSDT. This fixes undock ACPI events being issued when pulling out the power when docked or undocked (but still generates one when forcibly undocked) Tested on X200: pull power and see if undock events are generated in dmesg. Change-Id: I1eef971d49508bcd94d5d1cf2b70395b7cd80b1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: skip remap of high memory ranges if unnecessaryLubomir Rintel
If the DRAM does *not* actually overlap the PCI space, the remap code notices it is the case, but for some reason proceeds with the remapping, attempting to remap a negatively sized chunk. Bummer. With a single 1024M (two ranks of 512M) module: Nothing to remap Mem remapping enabled Remapstart 5120(MB) Remapend 6144(MB) Top of RAM 1024MB New top of RAM 2560MB Wrote remap map a0101 Mem remapping enabled Remapstart 4096(MB) Remapend 2560(MB) New top of memory is at 2560MB Needless to say, subsequent ram_resource() ruins the memory map for the OS -- Linux won't boot without a mem= argument and memtest quickly. TEST=memtest and Linux boot on HP t5550 with 1024M of memory Change-Id: Ic221723a26c5d1a03bf34c7722b0abe115f456ba Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: map the SPI controllerLubomir Rintel
This is required for Flashrom to work well. Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: fix format strings for DEBUG_RAM_SETUP=yLubomir Rintel
Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/superiotool: dump VT1211 registersLubomir Rintel
Change-Id: Id01b72a2194ebf3359a11c3ff382efaedf28f9e1 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/superiotool: distinguish between VT82C686 and VT1211Lubomir Rintel
They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/superiotool: recognize a VT1211 LPC superioLubomir Rintel
Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-14util/broadcom/secimage: Add OpenSSL 1.1 supportAlex Thiessen
The `secimage` utility uses OpenSSL to calculate HMAC, which it does in a rather unorthodox way, using deprecated `HMAC_CTX_init` API and repeated calling of `HMAC_Init_ex` without a clear reason. The former causes build errors with OpenSSL 1.1 while the rest of the `HmacSha256Hash` function is confusing and overly complex. Make `HmacSha256Hash` use a single OpenSSL API call. Test passed: resulting signed binary remains identical. Change-Id: Ib23c0ad96f9d8cc30ad357de8c0b0ba967c7d724 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-14mb/asrock/g41c-gs: Add IO decode range for SIO HWMONArthur Heymans
Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21464 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-14mb/asus/p5gc-mx/romstage.c: Remove unused IO decode rangesArthur Heymans
This source file was mostly copied from ga-945gcm-s2l but had different IO decode ranges. Change-Id: I54cb165000fad6984edf13fb33519fb9c9f0350f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14mb/*/*/romstage.c: Clean up targets with i82801gxArthur Heymans
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14AMD CIMx SB800: late.c: Use variable `device` from for loop conditionPaul Menzel
Use the variable `device` instead of `dev` in the predicate of the if condition, as `dev` is not changed in the for loop. The for loop was added in the following commit. commit 8fed77ae4c46122859d0718678e54546e126d4bc Author: Scott Duplichan <scott@notabs.org> Date: Sat Jun 18 10:46:45 2011 -0500 ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic Reviewed-on: http://review.coreboot.org/44 The assumption that the devices are ordered in the tree seem to hold in this case (although it is not ensured) and therefore at least with the ASRock E350M1 no (visible) change is experienced as the children are all of type `DEVICE_PATH_PCI`. Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/2562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-14mainboard/asus/am1i-a: add support for board ASUS AM1I-AGergely Kiss
Add code to support the board ASUS AM1I-A. Tested with multiple payloads and OSes with satisfactory results. S3 suspend/resume works fine with Linux but has issues with Windows (an exception is thrown). However, after manually rebooting, Windows resumes the suspended session. * Tested with: SeaBIOS 1.11 + Linux 4.10 - OK * Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK * Tested with: FILO 0.6.0 - hangs after showing the banner Details are going to be published on the board's status page. Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7 Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14util/superiotool: add support for chip ITE IT8623EGergely Kiss
Due to the lack of a datasheet, defaults are shown as "not available (NA)" in the register dump. Change-Id: I6baaf5dd95453fb1265425f357ea16c710c006ba Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-13mainboard/google/kahlee: Finish GPIO90 setup for GruntMartin Roth
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly, but these additional registers need to be set to use it as a GPIO. - Split structures into variant specific versions. These will be moved into the variant tree in a follow-on patch - Set GENINT_DISABLE bit - Disable interrupts for this GPIO. BUG=b:71867096 TEST=Build and boot grunt. Verify registers are set correctly. Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13soc/amd/stoneyridge: Add definition for GENINT_DISABLEMartin Roth
BUG=b:71867096 TEST=None Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13mainboard/google/kahlee: Fix GPIO tableMartin Roth
The GPIOs that are being set low had the wrong value getting set. FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE. BUG=b:70234300 TEST=Build and boot Grunt Change-Id: I16792b76252506a43aac92738b04096ae3fde01c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13google/kahlee/grunt: Add grunt touchpad ASLDaniel Kurtz
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD, respectively. Since grunt is the 'baseboard', put its configuration under baseboard, and include it from the grunt variant. BUG=b:71820409 TEST=Boot grunt to kernel, use evtest to test trackpad. TEST=Boot kahlee to kernel, use evtest to test trackpad. Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13google/kahlee/grunt: Add Grunt audio codec ASLDaniel Kurtz
Grunt and Kahlee have different audio codecs. Create a new audio .asl for the baseboard for grunt's codec, link to it from the grunt mainboard, and move the kahlee codec table from the baseboard mainboard to its own .asl in variant/kahlee. Note, we can't use the generic drivers due to the PCI scope expectation. The AMD I2C are not PCI devices. BUG=b:69397774 TEST=Codec driver loads. Check dmesg. Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23226 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13google/kahlee/grunt: Move ASL to variantsMarc Jones
Move the apci/ to the baseboard and move mainboard.asl to each variant. BUG=b:71873651 TEST=build BRANCH=none Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13soc/amd/stonyridge: Give I2C devices unique _UIDsDaniel Kurtz
The ACPI unique identifier (_UID) should be unique. This doesn't actually matter much for Linux, though, since the kernel can handle it when the BIOS doesn't get this right. See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-01-13Revert "soc/amd/common/pi: Fix issue in AGESA heap allocator"Marc Jones
This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b. This is not the correct fix for the heap allocator. It looks like the root cause is in the buffer size of the deallocate function. Change-Id: I33c479a30d89a665677d3e4914194ae8136504af Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-13mainboard/google/zoombini/variants/meowth: set GPD_2 to NF1Nick Vaccaro
Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must be set to use NF1 instead of gpio. BUG=b:64395641 BRANCH=none TEST=none Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/compulab/intense_pc: Change devicetree to correct CPU socketHal Martin
Intense PC uses FCBGA1023 socket, not rPGA989. Correct the socket in the devicetree. Change-Id: Ie657af2f51dfb7add90b19b26c0c37d312d59821 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-12mb/compulab/intense_pc: enable SuperIO UARTHal Martin
Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot boot messages from coreboot over the integrated RS-232 port (requires use of included dongle). Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-12mainboard/hp: Add Elitebook Revolve 810 G1Bill XIE
The code is based on autoport and that for 8470p. Tested: - CPU i5-3437U - Slotted DIMM 8GiB - Soldered RAM 4GiB from Hynix (There may be more models here) - Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera) - Mini pci-e on wlan slot - On board SDHCI connected to pci-e - USB3 ports - USB3 hub on dock (connected to USB3 port 1) - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from SeaBIOS, or Linux payload (Heads) Not work: - An "NFC" device connected to LPC Not implemented yet: - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/22972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-12mb/google/poppy/variants/nami: Fix DA7219 IRQ issueKaiyen Chang
Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to meet the requirement of DA7219 IRQ pin. BUG=b:70646770 BRANCH=none TEST=Use aplay and arecord to verify headphone function. Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23160 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-12soc/intel/common/block: Check for NULL before dereferenceShaunak Saha
We check for NULL from the return of function acpi_device_path before passing it to acpigen_write_scope to avoid NULL pointer dereference. Change-Id: I997461c9b639acc3c323263d304333d3a894267c Found-by: Klockworks Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/skylake: Override KBL IccMax settingsGaggery Tsai
According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeron/Pentium are different. This patch overrides the IccMax settings for KBL-U/R/Y since device tree could not handle all KBL-U/R combinations when multiple SKUs are adopted in a project. Besides, it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+------+-----+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | | | | | | 32A(i3/i5) | | | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | +----------------+-------------+---------------+------+-----+ BUG=b:71369428 BRANCH=None TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12ec/lenovo/h8: Add support for bluetooth on wifiPatrick Rudolph
The EC does enable bluetooth on wifi cards and BDC at the same time. Check the new Kconfig to support bluetooth on wifi in case no BDC is installed and the BDC detection fails. Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-12mb/google/fizz: update DPTF settingsKevin Chiu
TCPU: _CRT: 100 _PSV: 93 _TRT: 100/5(s) TSR0: _CRT: 83 _PSV: 70 _TRT: 100/10(s) TSR1: _CRT: 73 _PSV: 67 _TRT: 100/30(s) TCC: 6 for 94'C PL1: max: 15W min: 3W BUG=b:70294260 BRANCH=master TEST=build Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/google/fizz: Disable PCH LanKane Chen
Fizz has external Lan on PCIE port. The Lan device on PCH is not used. BUG=b:70889517 Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mainboard/glkrvp: Add EC_GOOGLE_CHROMEEC_SWITCHESShaunak Saha
This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we use the common switch.c file Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mainboard/glkrvp: Add RECOVERY_CACHESrinidhi N Kaushik
This patch adds recovery cache. TEST:glkrvp boots with this change and also FAFT test firmware_CorruptRecoveryCache passes. Change-Id: I9b32628d814693fb0591fc3750348d48cf9e26f1 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/23067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/google/poppy: Remove digitizer reset control from ACPIFurquan Shaikh
Digitizer power is not controlled by SoC. Also, since the digitizer uses I2C-HID driver in Linux kernel, the device is put into sleep anytime system is suspended. Thus, there is no need to control the reset gpio using ACPI power resource. TEST=Verified that digitizer device is properly detected on boot-up and after suspend/resume. Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/intel/kblrvp: Use common HDA codeDuncan Laurie
Instead of duplicating code in each mainboard that supports HDA use the common driver and provide the HDA verb table. This was compile tested for both variants with "abuild -t intel/kblrvp" Change-Id: Ie3bab7aabcfa040935062b7764853df8fb19b04d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/common: Add Intel HDA common block driverDuncan Laurie
There is common HDA code in soc/intel/common that provides generic HDA support functions, but it does not provide a driver. This change adds a common block driver for HDA that provides a ramstage driver for SOCs that need to initialize an HDA codec. This was tested on a board with an HDA codec to ensure that it properly detected it and ran the codec init steps. Change-Id: I41b4c54d3c81e1f09810cfaf934ffacafca1cf38 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12amd/stoneyridge: Keep SPI flash cacheable during POSTMarshall Dawson
A side effect of using the common MTRR assignment code is the flash device loses its WP setting and is no longer cacheable. After MTRR setup, reenable the setting for the duration of POST. TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate() BUG=b:70536683 Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-12mb/google/poppy/variants/nautilus: enable digitizer pen deviceSeunghwan Kim
- Add pen device property into devicetree.cb. - Set GPP_C9 to 0 as default. BUG=none BRANCH=master TEST=emerge-nautilus coreboot and check pen device operation Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Reviewed-on: https://review.coreboot.org/23010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12soc/amd/common/pi: Fix issue in AGESA heap allocatorMarc Jones
The heap allocator would try to split a buffer node that was too small for another node. In the failing case, the buffer node was 0x140 bytes and the requested size was 0x133 bytes. The logic would check that there was room for the header and buffer and try to split the buffer node. The buffer node header is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't leave room for another node header and a little space for a buffer. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: Iece5e12d5787415a335bb953985331a5dc312152 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-01-12mainboard/google/kahlee: Enable PCIe Lane 2Martin Roth
The Port initializer had been changed from PortDisabled to PortEnabled, but engine inializer hadn't been updated from PcieUnusedEngine to PciePortEngine. Update this so the port works. Also change disabled port to PcieUnusedEngine. BUG=b:71818026 TEST=PCIe device now shows up on D2F4 Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23210 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-11util/gitconfig: Refuse to commit on lint failureAlex Thiessen
After running `lint-stable` in the pre-commit hook, its result is ignored. This behavior was introduced in commit b18f522b (lint/gitconfig: Enable checkpatch.pl checking of commits) and it doesn't seem intentional. This issue was also mentioned in the revert discussion (https://review.coreboot.org/c/coreboot/+/17440). Enable `errexit` mode of the shell so that the hook fails when an error occurs in any of the tests. Also, enable `nounset` mode to catch typos easier. Change-Id: I749963167660ea6a1a04d40a14ad1113e82f0f86 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-11google/fizz: Dynamically set PsysPl2 MSR if using type-C chargerShelley Chen
If using type-C charger, then PsysPl2 may be lower than barrel jack value of 90W, so need to override value to the max power of type-C charger. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W when using proper barrel jack adapter on and i7. Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11intel/fsp2_0: Set boot mode default as per s3wake statusAamir Bohra
Currently bootmode default is set to FSP_BOOT_WITH_FULL_CONFIGURATION and bootmode UPD is updated in fsp_fill_mrc_cache based on mrc cache data validity. With current implementation in S3 resume path, if mrc cache data is invalid, the bootmode is not updated further and remains set at FSP_BOOT_WITH_FULL_CONFIGURATION. This results in fsp-m to get incorrect boot mode context and reinitialize memory in S3 resume path. In correct flow fspm should have correct bootmode context i.e. S3 resume and return error in case mrc cache data is invalid or not found. BUG=b:70973961 BRANCH=None TEST=Verify correct bootmode is set on S3 resume, even when mrc cache data is invalid. Change-Id: Idc0da6ffbfe5ce616d852908a9b0074dc8ce7cbe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/23156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-11intel/fsp2_0: Issue hard reset in S3 resume for invalid mrc cache dataAamir Bohra
In S3 resume, for cases if valid mrc cache data is not found or RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION. This gets memory to be retrained in S3 flow. Data context including that of imdr root pointer would be lost, invoking a hard reset in romstage post memory init. Issuing hard reset before memory init, saves fsp memory initialization and training overhead. BUG=b:70973961 BRANCH=None TEST=Verify S3 resume flows on soraka. Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-11mainboard/google/zoombini: map EC io space in devicetree.cbNick Vaccaro
BUG=b:64395641 BRANCH=none TEST=none Change-Id: I92969384cd32766be4595494aa70b4eb9c74f099 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: add gpio init to ramstageNick Vaccaro
-add initialization of gpio table to mainboard_silicon_init_params() -fix input parameter type for mainboard_silicon_init_params() for FSP2_0. BUG=b:69011806 BRANCH=chromeos-2016.05 TEST=none Change-Id: If8cba786a127a8704eb240380841362e3eb06552 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini/variants/meowth: map EC io spaceNick Vaccaro
Map EC io space in devicetree.cb BUG=b:69011806 BRANCH=none TEST=none Change-Id: Ic3806b5f9b7bf272a77360060cd71db9a03d5763 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini/variants/meowth: Disable EC SW syncNick Vaccaro
BUG=b:69011806 BRANCH=chromeos-2016.05 TEST=Compiles successfully using "./util/abuild/abuild -p none -t google/zoombini -x -a" Change-Id: I8276fa26af664557e9964cb6b8a5a076eacdf00c Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: add ec.c and ramstage.c to buildNick Vaccaro
-add ec.c to bootblock if CONFIG_EC_GOOGLE_CHROMEEC -add ramstage.c to ramstage. BUG=b:69011806 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' compiles correctly. Change-Id: I7ec1e22339f3e4d9a8d83093bcc2ce725c9c99e7 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini/variants/meowth: fix gpio settingsNick Vaccaro
-change GPP_C12 (H1 IRQ) to use GPI_SCI_LOW and level triggered -set gspi gpios to no connects if CONFIG_ZOOMBINI_USE_SPI_TPM not set BUG=b:69011806 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' succeeds Change-Id: Ida1d1050db12982c3c497656162cc84c62a77f70 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: enable USB and assign acpi irqNick Vaccaro
-add USB2 and USB3 to devicetree -add TPM_TIS_ACPI_INTERRUPT to Kconfig -map gpe0_dw0, gpe0_dw1, and gpe0_dw2 blocks BUG=b:64395641 BRANCH=chromeos-2016.05 TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-11mainboard/google/zoombini: fix spd makefilesNick Vaccaro
The spd.bin file was not getting generated properly, so moved logic to variant's makefile. BUG=b:64395641 BRANCH=none TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully and spd.bin is found when booting. Change-Id: I4642d6ddb5e65f721d1bde31ca0ca5b4438da554 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-10util/inteltool: Add Skylake Desktop NorthbridgeChristoph Pomaska
Add the 8086:191f North/Host Bridge to the list of definitions. Adding the definiton makes the Northbridge get recognized by inteltool. It is found in the Intel i5-6600K CPU: https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz Change-Id: Id746d1e8b3bb90b3b68a2f6c372890671dd61b5f Signed-off-by: Christoph Pomaska <cp_public@gmx.de> Reviewed-on: https://review.coreboot.org/23055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-10soc/rockchip/rk3399: Ensure full eDP init sequenceEge Mihmanli
This patch fixes 2 edp display issues: 1. When rk_edp_prepare fails >3 times, edp_init isn't run because while-condition is not satisfied. Then, only a partial init sequence is ran. This causes all aux transactions to fail. 2. If rk_edp_prepare never succeeds, coreboot never leaves link training stage due to infinite loop. Boot process is stuck. TEST=Boot past eDP initialization stage and make sure AP logs don't have show aux transaction fails. Change-Id: I44c3f53e8786558c43078d4afe9acde4d64796e7 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-10soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblockFurquan Shaikh
This change adds a call to gspi_early_bar_init in bootblock to allocate a temporary BAR for any GSPI buses that are accessed before resource allocation is done in ramstage. Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22781 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-10soc/amd/common/block/acpi: Add halt.cChris Ching
Creating initial common acpi and implement halt.h BUG=b:71575631 BRANCH=none TEST=put poweroff() call in Kahlee's mainboard_final and board turns off correctly Change-Id: Ie7dd9851dcb240c53f2487b4f4b8a3e51d6b98d6 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/23074 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-10util/lint: Check license headers of git hooksAlex Thiessen
Now that all the files under util/gitconfig have their license headers, enable lint-000-license-headers to check the directory too. Change-Id: I242256f72ac70553535509f83166c6d1ddb16fdc Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-10util/gitconfig: Add missing license headersAlex Thiessen
License header for the `gitconfig.sh` was copied from the Makefile it was extracted from in commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script). License header for the pre-commit hook names Patrick Georgi as the copyright holder as he is the original author. Change-Id: Ie051e5e6ae7571050ece383e6be8236ed7d1ddd9 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-10mainboard/google/kahlee: Update SPD MakefileMartin Roth
The .spd.hex text is added to the name by the build process. This was causing a failure because we were trying to add the files: 'file.spd.hex.spd.hex' to the build. Remove the additional .spd.hex text. BUG=b:71535311 TEST=Build Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-01-09mb/google/fizz: Turn off SATA SALPKevin Chiu
turn off SATA SALP to prevent 0x5A/0x5B error on Sandisk SSD in below conditions: 1. reboot stress 2. FAFT BIOS qualification BUG=b:70146894,b:69984821,b:70590720 BRANCH=master TEST=pass firmware_ConsecutiveBoot 2500 loops FAFT BIOS test pass Change-Id: I5d57dd8ef256d5f0a1027ab77f63da62c6c9ce74 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-09mainboard/google/zoombini/variants/meowth: add new boardNick Vaccaro
Add Meowth board, which derives from Zoombini, a CNL reference board. BUG=b:69011806 BRANCH=master TEST=Compiles successfully using "./util/abuild/abuild -p none -t google/zoombini -x -a" and boots Meowth. CQ-DEPEND=CL:22908 Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-09mainboard/google/zoombini: Provide memory configuration variant APINick Vaccaro
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-09soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik
This patch ensures all CannonLake CPUIDs are part of mp_init.h hence remove duplicate macro definitions from SoC code. TEST=Build and boot CannonLake RVP Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-09mb/google/poppy: Add internal pull-up on pen eject signalFurquan Shaikh
Since the current hardware revision does not have external pull on the pen eject signal, this change adds internal pull-up on it. Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-08soc/amd/stoneyridge/i2c: fix formatting and global symbolAaron Durbin
The i2c_bus_address array doesn't need to be a global symbol. Also, the array initializer had some weird indention and there was an extra new line. For consistency the first entry is multiplied by 0 so the formatting is similar. BUG=b:69416132 Change-Id: I74f6dca3a22a245759536f792ce04ac61735b6d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-01-08google/gru: switch to spi2 for all scarlet based boardsEge Mihmanli
Rainier, a scarlet derived board, was configured to use spi0 for tpm driver by default. This patch switches it to spi2 to reflect recent changes in scarlet-derived boards. Change-Id: Ib67109786512c068bb957890f456bccff7addc86 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-08soc/intel/cannonlake: Initialize DDI-A lane in Normal modeAbhay Kumar
Enable DDI-A (eDP) when pre-OS graphics is not Loaded or in normal mode. This will make sure that kernel will detect eDP. TEST=Edp should come up in normal mode. Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/22799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-08soc/amd/stoneyridge: Define CONSOLE_UART_BASE_ADDRESSArthur Heymans
The build system for the SeaBIOS payload needs this when DRIVERS_UART_8250MEM is set. Set it to the first uart controller, which the coreboot code also seems to do. Fixes: https://ticket.coreboot.org/issues/150 Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-07superio/ite/it8623e: add support for SIO chip ITE IT8623EGergely Kiss
This change adds basic support for the SuperIO chip ITE IT8623E. Due to the lack of a datasheet, defaults are shown as "not available (NA)" in superiotool's register dump. LDNs defined in it8623e.h are definitely correct and working as expected. Change-Id: I05832c4db7ab59541337f11200640316376e792e Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07soc/amd/common: Only load post-memory AGESA into RAM when split enabledDaniel Kurtz
CONFIG_AGESA_SPLIT_MEMORY_FILES controls whether AGESA is split into pre- and post-memory binaries when it is built. Building AGESA this way is required when doing the new "load post-memory AGESA binary into ram" feature. Thus, condition this new path on the CONFIG option being enabled. BUG=b:71641792 TEST=build and boot kahlee with CONFIG_AGESA_SPLIT_MEMORY_FILES disabled Change-Id: Ibec9db67437c57092e0f7acf0e3185865dc02688 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23141 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-07autoport: Add Intel PCIe Root Port and BridgesJean Lucas
- 0x0151: Xeon E3-1200 PCIe Root Port - 0x1e25: 7/C216 Series Chipset Family DMI to PCI Bridge - 0x2448: 82801 Mobile PCI Bridge - 0x244e: 82801 Desktop PCI Bridge Change-Id: I4111b73adc0f08d643c940cd43ab7fd4c0af7668 Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/22794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07soc/intel/cannonlake: provide LPDDR4 memory initNick Vaccaro
Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-073rdparty/blobs/soc/amd/stoneyridge: Use new location of stoneyridge blobRichard Spiegel
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it. BUG=b:69613465 TEST=Build and run kahlee. Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-07mainboard/ms7721: Fix temperature sensor configurationRenze Nicolai
This patch allows temperature sensors 1 and 2 to function by setting their type to be thermistor instead of BJT. Change-Id: I6491171eacc0c9848ba86ba7a62ec440226aae36 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07mainboard/nf81-t56n-lf: Add temperature sensor configurationRenze Nicolai
This patch adds the temperature sensor type device tree setting, configured to be the default value as stated in the Fintek f71869ad datasheet on page 60. bit 7-4: reserved (0) bit 3: T3_MODE 1 (default) = BJT, 0 = thermistor bit 2: T2_MODE 1 (default) = BJT, 0 = thermistor bit 1: T1_MODE 1 (default) = BJT, 0 = thermistor bit 0: reserved (0) This results in a default value of 0x0E This change is needed to make sure behaviour does not change after applying change 22935 which adds the temperature sensor type devicetree configuration option Change-Id: I42980988267621def6576f771f1d8a853500e867 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07superio/f71869ad: Add temperature sensor typeRenze Nicolai
This patch makes it possible to set the "Temperature Sensor Type Register" at index 6Bh from the devicetree, allowing the use of thermistors instead of BJT type sensors. Register documentation (from page 60 of the F71869 datasheet): 6.6.25 Temperature Sensor Type Register - Index 6Bh Bit 7-4: reserved Bit 3: T3_MODE (0: thermistor, 1: BJT [default]) Bit 2: T2_MODE (0: thermistor, 1: BJT [default]) Bit 1: T1_MODE (0: thermistor, 1: BJT [default]) Bit 0: reserved Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07intel/dcp847ske: Add superio ACPI declarationsTobias Diedrich
Tested on Linux 4.13.14: SuperIO resources show up as reserved in /proc/ioports and friends. Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07nuvoton/nct6776: Add ACPI declarationsTobias Diedrich
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Tested on Intel NUC DCP847SKE, Linux 4.13.14. Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-06superio/ite: add missing pnp_conf_mode fields in ops structFelix Held
This fixes the bug that the LDNs on the affected SIO chips didn't get configured, since the config mode wasn't entered. Change-Id: Ic468847571e164e4e1280428f08fc067b724464e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-05mainboard/google/zoombini: Add SoC acpi files to dsdt.aslNick Vaccaro
BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-05mainboard/google/zoombini: Fix some devicetree pci settingsNick Vaccaro
- Enable I2C #2, #3, and #5 - Enable UART #2 - Enable GSPI #0 and #1 - Disable SATA - Set pci 1f.0 to chromeec BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 21:05:34 +0000