| Age | Commit message (Collapse) | Author |
|---|
|
Updating from commit id b2c8984d:
2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM)
to commit id 87276ffe:
2019-11-07 17:46:09 +0800 - (futility: updater: Clean up hard-coded section names to preserve)
This brings in 48 new commits.
Change-Id: Iabaadc63227b856d0a2b7f3b23fe8c41b28d8eae
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This is currently an empty repo. The intention for amd_blobs may be
found in Documentation/soc/amd/amdblobs_license.md. A subsequent
patch will make the repo's init and checkout optional based on a
Kconfig symbol.
Change-Id: Ia93fb2711beaea4cb1c8e5d71dc3a9e0facc5485
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This includes a huge set of refactorings to support Core Display Clock
(CDClk) frequency switching based on the current mode requirements.
The CDClk is configurable since Haswell and runtime switching is suppor-
ted since Broadwell. Always using the lowest possible frequency setting
should allow some power-savings. While, on the upper end, we can support
higher resolution panels now, without having to change the static confi-
guration.
There have also been some smaller changes and fixes, including:
o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't
advertise a maximum link rate but only individual ones.
o DP support for Ibex Peak.
o Corrected limit for HDMI on G45 to 165MHz.
o Reworked GMBUS reset handling and timeouts, should help with
stalled GMBUS controllers when unimplemented ports were probed
by accident.
Tested on various boards from GM45 to KBL-R.
Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id 42cdeb93:
2019-09-13 12:09:21 +0000 - (Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration)
to commit id ace23683:
2019-09-27 09:54:27 +0000 - (Merge changes from topic "ld/stm32-authentication" into integration)
This brings in 83 new commits.
Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Updating from commit id 860fe2962:
2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.)
to commit id a1afae4e0:
2019-10-02 11:47:45 +0000 - (juniper: initial setup)
This brings in 1723 new commits.
Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Updating from commit id ce228ee:
2019-07-02 11:11:08 +0530 - (include: Bump-up version to 0.4)
to commit id e561c63:
2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators)
This brings in 44 new commits.
Change-Id: Ide6e3c2bb98e79750b40a9b8ca9f2f1d2c123628
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Updating from commit id e6700f4c:
2019-08-13 04:36:52 +0000 - (vboot: update vboot2 functions to use new vb2_error_t)
to commit id b2c8984d:
2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM)
This brings in 71 new commits.
Change-Id: Id7cefa3ad5b30c955d18e469494fec32f6f58a48
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
It's been some time and there are 1420 new commits. Including one that
allows reproducible builds \o/ and one that breaks building with empty
$(CC) :-/
Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).
Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.
NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.
Tested on GOOGLE_KEVIN (rk3399).
Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
These tools are used to manipulate open-power specific partitioning and
ecc algorithms.
Change-Id: I0657f76aab75190244d0e81c2b1a525e50af484d
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35007
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To make explicit when vboot2 error codes should be returned,
use the new vb2_error_t type on all functions which return
VB2_ERROR_* constants.
Additionally, add required vboot submodule commit id e6700f4c:
2019-07-31 14:12:30 +0800 - (vboot: update vboot2 functions to use new vb2_error_t)
NOTE: This patch was merged separately on the Chromium tree:
https://chromium-review.googlesource.com/c/1728499
BUG=b:124141368, chromium:988410
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1728292
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Updating from commit id 9c906110:
2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies)
to commit id a5afd01f:
2019-08-08 11:02:44 -0700 - (Minor fixes for clang)
This brings in 6 new commits.
Change-Id: Ic334ce8a5f24a0119fa2aaf000ce76c4c9e4932a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Update the 3rdparty/blobs submodule to the newest HEAD, which
contains the SPM binary for MT8183 platforms
( https://review.coreboot.org/c/blobs/+/34543 ).
Change-Id: I505ec9fffd9ddd62fffbe9514cbba50625825693
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34734
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id dac763c7:
2019-05-10 10:43:55 -0700 - (Make vboot -Wtype-limits compliant)
to commit id 9c906110:
2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies)
This brings in 68 new commits.
Change-Id: Ia96347d8ed94db6f0ec5f5108cb98ab0c4087bd4
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Update libgfxinit:
o Add support for ULX (CPU Y series) variants
o Add support for Kaby/Coffee/Whiskey/Amber Lakes
o Publish Read_EDID() procedure
o Fix certain GMBUS error conditions
o Fix DP training when clock recovery needed voltage-swing increase
o Fix scaling on eDP for BDW+
Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Use latest OpenSBI that include support for dynamic firmware loader.
That allows us to use OpenSBI similar to BL31 on aarch64:
* coreboot loads the payload
* coreboot loads OpenSBI ELF right before payload handoff
* OpenSBI does platform lockdown and provides runtime services
* OpenSBI hands control to already loaded payload
The uncompressed compiled OpenSBI code is about 41KiB.
Required to boot GNU/Linux on qemu-riscv as some instructions needs to be
emulated by SBI.
Change-Id: If7ed706bc54a75fb583a8aa46fdd61ae7d18c546
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Uprev the 3rdparty/blobs submodule to the newest HEAD, which
contains the SSPM binary for MT8183 platforms
( https://review.coreboot.org/c/blobs/+/32698 ).
Change-Id: I8a4dfa7eaace1ea473f5970596c3201342e48927
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34494
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40
github commit:
https://github.com/IntelFsp/FSP/commit/59964173e18950debcc6b8856c5c928935ce0b4f
Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33642
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Icc5ac0a8033e371ecf2b4b28ba45dab961e86b3f
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
|
The sandybridge systemagent-r6 blob is modified:
- To be more flexible about the location of the stack w.r.t. the heap
- Place the MRC pool right below the MRC_VAR region
- to work with the same DCACHE_RAM_BASE from the native raminit (could
make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native
bootpath and also allows for BIOS/memory mappeds region larger than
8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also
include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch uprevs the vboot submodule to the new upstream HEAD commit
dac763c782 Make vboot -Wtype-limits compliant
Change-Id: I363e218e019b25483bc4c06315ca4e0e34599daf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Beside one tiny fix for framebuffer scaling, this contains a major
refactoring of libgfxinit's configuration infrastructure. With this,
we are finally able to detect CPUs at runtime and only have to confi-
gure a CPU/GPU generation.
Change-Id: Iccf4557453878536f527e4a1902439a1961ab701
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Beside some refactorings that don't affect coreboot, this contains
bd0ed91 (Makefile: Revise support for generated sources) that fixes
an issue with upcoming libgfxinit configuration changes.
Change-Id: Ib47aeff8f6426ae27ddbc235a954e3bd60029072
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32735
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id 304aa429:
2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags)
to commit id e7edff66:
2019-05-03 07:02:32 -0700 - (vboot: implement DISPLAY_INIT context and SD flag)
This brings in 45 new commits.
Change-Id: I7493e43bddc553f9724de46130ccb4cb44e18573
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Update submodule pointer to pull in newly-updated Braswell FSP.
Adjust FSP_FD_PATH for soc/cannonlake due to filename case change.
Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
* Add opensbi for RISC-v
Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Updating from commit id 1e177741:
2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE)
to commit id 304aa429:
2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags)
This brings in 18 new commits.
Change-Id: Ie2889ed0217c38734eb2c496ca20f95b6a12b102
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31872
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Update SMU firmware for amd/stoneyridge
* Remove stale Sandy Bridge MRC binaries
Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Updating from commit id a32c930e:
2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO)
to commit id 1e177741:
2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE)
This brings in 11 new commits.
Change-Id: I59d83de49006a6d081b206716002697d39099aa4
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/31542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Updating from commit id 392211f0:
2018-04-23 13:07:25 -0700 - (Update Android signing to support signature scheme v2)
to commit id a32c930e:
2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO)
This brings in 159 new commits.
Change-Id: I7fea9ff1e4109d4dbc979289172191f677438933
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The microcode included for `model_6xx` was for a 660, that path has
changed.
Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Updates to current master.
This includes:
- A fix for textmode scaling on G45
- Refactor things to rely less on inline proving
- Increased width of modeline fields to 32 bits
Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30311
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A liara specific VBIOS was released and merged to blobs. Now coreboot
need to point to the updated blob, so it can use liara specific VBIOS.
Liara Chromebook Stoney VBIOS BRT39865
BRT39865.001 12/05/18,01:13:54 CL#1716128 @ 15.49.0.18 ATOMBuild#436504
Major Changes included:
1. First Stoney VBIOS released to Liara update eDP power up sequence.
BUG=b:120534087
TEST=none
Change-Id: I3b060b1ccfb311584afd0fb66258eb7cc942408d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
New VBIOS code has been added to blobs/mainboard/google/kahlee. It has been
merged, so now coreboot needs to use latest blob.
BUG=b:112618193
TEST=none
Change-Id: If430ee06f03e0f20806bf8fd2b649814251ffcf5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I0032e86755750755e7ae6e2a53863e1600f96a5b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
This includes the SplitFspBin.py script.
Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Like the 3rdparty/blobs repo this isn't checked out by default. Right
now you can manually check it out using
$ git submodule init --checkout
A follow up commit will add some automagic if USE_BLOBS and
MAINBOARD_USES_FSP2_0 are enabled.
Change-Id: Ie612495abc2a2d5947225e6ab54872aa72d4bec6
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/28303
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Include Cavium's CN81xx BL31.elf
* mainboard/google: Add folder kahlee for video binary
* Stoney Ridge: PSP bootloader update
* cpu/intel: remove microcode header files for model_306ax
Change-Id: Ie8f3b2e8db0692e95caee245733054e4e20f61ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
The two commits below are added to the BLOBs repository.
* fe7c6a3 pcengines/apu2: Disable ECC Exclusion range
* 3854ad2 cpu/amd/family_15h: Add latest AMD ucode file
The latest AMD microcode patches include Spectre mitigations.
Change-Id: I4729cc054fe8267549d7369cea4d26aa51861e1c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Update to current master.
This includes:
- G45 support
- fixes scaling on eDP (needed for working textmode on eDP)
- gfx_test drawing and moving cursors
- Adding support for Tiling on <= Haswell
- Allow changes to the framebuffer configurarion without resetting the
pipe.
Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26823
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update to current master. Beside a minor workaround for GCC 8
compatibility, this includes only refactorings and preparations
for G4x support.
Change-Id: I6b2aa6bd9d41b852dacd8e1dfe89d92c8a548121
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26420
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Includes the necessary changes to build with gcc 8.1
Change-Id: Ie8c3dede4d702ab7838162dbff09f94df34b7c91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Pull a minor update for GCC 8 compatibility.
Change-Id: I0a4af47d56f3ca0b8ed82533e84c44041661ca35
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26306
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds the following changes to the blobs repository:
78a02a7 cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
In short: Bump Intel microcode updates. They include spectre/meltdown
mitigations.
Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/26270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This reverts commit 0ff9daac45d604fa4864394616e335e20af26c3e.
It points to a stale commit under review; i.e. not to a commit on
blob.git's master branch like it's supposed to.
Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This moves the blobs submodule marker forward to include the following:
b45abbd cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
in short: bump Intel's microcode updates to the latest version. This
includes Spectre/Meltdown mitigations.
Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/25505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Updating from commit id e0b38418:
- image_signing: Add sha1sum of keys in keyset to VERSION.signer.
To commit id 392211f0:
- Update Android signing to support signature scheme v2
This fixes bulding with depthcharge master.
Change-Id: I07b570f54b26a937a5a7c53ade464e0c7a550312
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Update libgfxinit to current master. Changes include:
* a fix to decode the size stolen memory correctly on pre-SandyBridge
hardware,
* a PCI id based generation check, obsoleting the old check based
on PCH audio ids,
* some minor improvements around rarely used DDI ports (D and E), and
* added support for tiled and rotated framebuffers on Skylake+ hardware
(less interesting for coreboot, I guess?).
TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6
(Skylake) both with text and linear framebuffers and observed
FILO's prompt showing up.
Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25453
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.
BUG=b:70338633
TEST=build kahlee.
Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id 9fb10386a: 2017-06-21 04:19:06 -0700
(Poppy: Configure camera PMIC to low power mode.)
to commit id 927b64a0b: 2018-02-15 00:10:45 -0800
(meowth: zoombini: enable CONFIG_CMD_PD_CONTROL)
This brings in 1205 new commits.
Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Updating from commit id a5efee5:
2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs)
to commit id 19dea8d:
2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9)
This brings in 2 new commits.
Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23562
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
This patch updates the arm-trusted-firmware submodule from:
commit 9fd4a36c408a254d887106e6e3960d496456be2c
(Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
to
commit 693e278e308441d716f7f5116c43aa150955da31
(Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch)
This brings in 79 new commits.
Change-Id: Ieceb07760178f8ddbb5cafebabeb78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Updating from commit id f6780a36:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)
to commit id e0b38418:
2018-01-16 04:08:26 -0800 - (image_signing: Add sha1sum of keys in keyset to VERSION.signer.)
This brings in 25 new commits.
Change-Id: If60f19decd91eaafec1d555c1e7d3ca0249d8068
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Updating from commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
to commit id 9fd4a36c:
2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
This brings in 596 new commits.
Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were
moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob
to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it.
BUG=b:69613465
TEST=Build and run kahlee.
Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This is required at least on Skylake to be able to configure text mode.
3rdparty/libgfxinit is also updated by the single commit:
42fb2d065d gma: Add procedure to power up legacy VGA block
Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Updating from commit id 3b80572:
2017-10-12 16:35:30 -0700 - (tlcl, tpmc: extend GetVersion to report vendor specific data)
to commit id f6780a3:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)
This brings in 19 new commits.
Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22777
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Updating from commit id a52fc548
(image_signing: Remove legacy unified build feature)
to commit id 3b805725
(tlcl, tpmc: extend GetVersion to report vendor specific data)
This brings in 22 new commits.
Change-Id: I51e44490e0ffd2c5cc73d439c1f3f8831d816be9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Updating from commit id 3f3a496a 2017-09-01 09:20:19
(image_signing: Fix loem.ini pattern for unibuilds)
to commit id 753e34e9 2017-08-31 10:12:40
(futility: Make rwsig sign command produce EC_RW image)
This brings in 5 new commits.
This also updates Depthcharge stable commit ID.
Updating from a843f262 2016-08-16 08:41:04
(kahlee: select emmc boot first if available)
to commit id f3bb31fe 2017-08-15 17:15:33
(vboot: Support EC early firmware selection)
This brings in 14 new commits.
Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Besides some internal changes that won't have much effect on coreboot,
the newer version also supports building host tools on systems that
self-designate as i686.
Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Updating from commit id 8b714252 - 2017-07-18 02:36:16
(crossystem: Remove defunct sw_wpsw_bootfield)
to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700
(detachables: Skip "Enable Developer Mode" in DEV mode)
This brings in 6 new commits.
Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Updating from commit id 04b3835b:
2017-06-12 06:47:41 -0700 - (Add a script to generate a keypair for signing Rose RW firmware.)
to commit id 8b714252:
2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field)
This brings in 19 new commits.
Change-Id: Ib68068b1afc5a264623021325e19644e8b63f8f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Updating from commit id 3944adca:
2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes)
to commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
This brings in 373 new commits.
Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Update from commit bcffec7fd - reef: Cleanup battery code
to commit 9fb10386a - Poppy: Configure camera PMIC to low power mode.
Brings in 794 new commits from Jan 2, 2017 to Jun 21, 2017
Change-Id: I864679360bd3b211b6883a662e20812b49aefbba
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update blobs pointer to bring in the AGESA.bin changes for
amd/00670F00/FP4 and amd/00670F00/FT4.
Change-Id: I739124090e41edaf76210cda6189b2c7545cdf58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update from commit a1c5f7c0
vboot_reference: Add support for 3072-bit exponent 3 keys
to commit 04b3835b
Add a script to generate a keypair for signing Rose RW firmware
This brings in 34 new commits.
Change-Id: Ifa304af5c2cf0bcc466dfc4878dd9d08436eec75
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Update libgfxinit to the latest master. Changes:
* Remove trailing whitespace in debug output.
* Change some types to make it verify with SPARK Pro.
* Add Broxton (Apollo Lake) support for eDP/DP/HDMI.
* Add Linux user-space test tool `gfx_test`.
* Add a README describing libgfxinit and the build process.
TEST=Booted lenovo/t420 and verified that internal and
external displays are working.
Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Update libhwbase to the current master. Some noteworthy changes:
* Add prerequisites for upcoming Apollo Lake support in libgfxinit.
* Add some support for Linux user-space for libgfxinit's `gfx_test`.
* Fix compilation with GCC 7.
Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59
This brings in 241 new commits from the upstream arm-trusted-firmware
repository, merged to the upstream tree between December 30, 2016 and
March 18, 2017.
3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes
..
e0f083a0 fiptool: Prepare ground for expanding the set of images at
runtime
Also setup ATF builds so that unused functions don't break the build.
They're harmless and they don't filter for these like we do.
Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add the binaryPI file for the FT4 package and add SMU firmware to
be consumed by fanless OPNs.
Change-Id: I1c9b5ded6b494fac1553cc2ec7756a7a47386ecf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This brings in 70 new commits from the upstream vboot repository,
dated October 31, 2016 to March 2, 2017
Change-Id: Iac9c2b0389afbfa02c1cccc38d39a12dac4a5ac4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18953
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017
- Also add associated change to src/soc/rockship/rk3399 Makefile.inc
that is required to build the M0 Firmware.
Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Update to Chromium TOT with bcffec7f (reef: Cleanup battery code)
292 commits between Oct 28, 2016 and Jan 2, 2017
Change-Id: I6bc356b9e458bebaa5839375ff40dd7e0d6ccff1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18023
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Changes:
o Verification that the framebuffer matches the display mode
o Automatic upscaling if the framebuffer resolution is lower
than the display mode's
o VGA-plane support
o HDMI pixel rate is limited to hardware constraints
o Error tolerant handling of EDID header-pattern
Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17775
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Update the blobs submodule to bring in the binaries for 00670F00.
This also corrects some formatting in the various license.txt files.
Change-Id: I7a70d1168734d06ef6919d83dd73bc8f2bc4173c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17872
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins)
|
|
Add `libgfxinit` as another option for native graphics initialization.
For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has
to be called by the respective northbridge/soc code.
A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and
implement the Ada package `GMA.Mainboard` with a single function `ports`
that returns a list of ports to be probed for displays.
v2: Update 3rdparty/libgfxinit to its latest master commit to make
things buildable within coreboot.
v3: Another update to 3rdparty/libgfxinit. Including support to select
the I2C port for VGA.
Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`.
This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.
v2: Also update 3rdparty/libhwbase to the latest master commit.
Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16951
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Require new recovery reason for rec hash space lock failure in RO.
Change-Id: I606d1a1f51a3a4c127b2933f6fb00ba2ec4885fc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
`libgfxinit` is a SPARK library for graphics modesetting. It supports
Intel integrated graphics only, strictly speaking, the Core i processor
line.
Change-Id: Idf4b0e5fbf37a5d974075b2e44d1fa16dc428da3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16949
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
`libhwbase` is a SPARK library that contains some basic support for i/o
access, debugging, timers. Just what I put around `libgfxinit`, to make
it build standalone.
Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16948
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update to Chromium TOT with ea1a8699e96425806abdd532d04da254ae093f6e
Change-Id: I28b9f415a4d55442c294abd27c344a91608a06c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Update the chromeec submodule to current Chromium TOT.
Change-Id: Ia3d913703fdea0ece02074d8e2d4b30d97e9a97c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17179
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This pulls in the bdb support for futility so that rotor can build.
Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17061
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
We need to disable some regulators when the device goes into suspend.
This means that we need to pass some gpios to bl31, and disable these
gpios when bl31 runs the suspend function.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low
[pg: also update arm-trusted-firmware to match]
Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70
Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/374046
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The AGESA binary for PC Engines' APU2 board was just added to the blobs
directory. Update the submodule pointer to allow access.
Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16253
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
|
|
Half a year has passed. Fixes went in. Probably bugs, too.
However, nobody really supports our local vboot version anymore.
Change-Id: I5042f23686dfe98e540c482f744e9df2d7df3b19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16055
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
|
|
From: 388a7fa8 (Wed, 10 Feb 2016)
CR50: remove incorrect output length check in RSA decrypt
To: 83b6d697 (Mon, 1 Aug 2016)
g: increase usb console TX buffer size to 4K
676 commits
Change-Id: Ic80de8b6fd6d9eba2a092b1a3493931241a2e48b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16021
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
90 patches pulled in.
Change-Id: I3b893957cbd330e71d0f218262e768f577df4c66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15122
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: Ie57b0b7844f28671b8d6a8efe9231a47bfb8f805
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14745
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
It includes support for rk3399.
Change-Id: I326ef3dc3021313ee852395c302c076b3e3c8c5e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This is used in coreboot-side vboot code now, to keep booting from
the same RW section after wakeup - necessary when romstage is in RW
and its use of the RAM init configuration cache may differ between
versions.
Change-Id: Ie531cf3ddc980154f48772b3ff87e23473010721
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update ATF codebase to a version that supports passing a timestamp and
fix the format to what it accepts now (including quotes).
This provides reproducible builds.
Change-Id: I12a0a2ba1ee7921ad93a3a877ea50309136ab1ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Move submodule forward to a newer upstream master to fix the build on
paths containing "@", as can happen on jenkins.
Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13673
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Note that this is a manually added commit id (to get the CrEC fixes in
that are necessary for building outside cros_sdk), so it will probably
fail.
Change-Id: Idc15cf268c663ae49b209b92b198c9a4d122c7e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13546
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
It provides a few extensions to the API that are required, such as
vb2api_check_hash_get_digest()
Change-Id: Ib4d8bdc29751f51f0f7532376175490a0ffd84b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update the 3rdparty/blobs submodule to bring in the latest
CarrizoPI binaries.
Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Idc300472f8d8821dd362d6dd075150f285f1d09b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12207
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
