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Updating from commit id 33cc4f2:
2022-10-26 14:21:20 +0530 - (sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69)
to commit id a252198:
2023-05-23 11:00:31 +0000 - (sc7180/boot: Update qclib blobs binaries from 50 to 55)
This brings in 4 new commits:
a252198 sc7180/boot: Update qclib blobs binaries from 50 to 55
3fbd986 sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 50 to 69
7a3f064 sc7280/boot,shrm: Update qclib blobs binaries from 35 to 52
9884189 sc7280: Update AOP firmware to version 454
Change-Id: I938b768318d31d5e105d7c98823947cf8c02b195
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Updating from commit id e8efa5d:
2022-05-30 15:47:07 +0530 - (sc7180/boot: Update qclib blobs binaries from 44 to 46)
to commit id 33cc4f2:
2022-10-26 14:21:20 +0530 - (sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69)
This brings in 10 new commits:
33cc4f2 sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69
6c82214 sc7180/boot: Update qclib blobs binaries from 48 to 50
e570e02 Reland "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063"
6206ab8 Revert "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063"
82bbf78 sc7280/aop: Update aop blobs binaries and release notes version from 379 to 410
e3a760d sc7180/boot: Update qclib blobs binaries from 46 to 48
741abaa sc7280/boot/shrm: Update qclib blobs binaries from 30 to 35
436cb87 sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063
3f44ba0 sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes update from 044 to 050
eef51c6 sc7280/qcsec: Update qcsec blobs binaries and release notes for 27
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I72b91e384b74e4e44864ef5f29be78ebac4262fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Updating from commit id 9ab0f0b:
sc7280: Update AOP firmware to version 379
to commit id e8efa5d:
sc7180/boot: Update qclib blobs binaries from 44 to 46
This brings in 7 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5f0a9075cde90991e927f3bfb75246bdb9877837
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Updating from commit id 98db386:
2021-08-03 11:57:30 -0700 - (herobrine: Add gsi_fw_blobs and Release Notes)
to commit id 9ab0f0b:
2022-01-18 19:01:30 +0530 - (sc7280: Update AOP firmware to version 379)
This brings in 13 new commits:
9ab0f0b sc7280: Update AOP firmware to version 379
826cb9c sc7180/boot : Update qclib blobs binaries and release notes
ddf67d1 sc7280/ boot and shrm blobs updated
8592f11 sc7280: Update AOP firmware to version 364
aef8a0a sc7280/ boot and shrm blobs updated
c72bc4e sc7280/cpucp: Update cpucp blobs binaries and release notes version from 054 to 060
33e57fe sc7280/boot,/shrm : Update qclib blobs binaries and release notes version 13
511851b sc7180/boot : Update qclib blobs binaries and release notes version 30
f91d0ef herobrine: qc_sec blob update
8c50f78 sc7180/boot : Update qclib blobs binaries and release notes
8523ef4 sc7180/qtiseclib: Update version from 26 to 44
5b77a37 sc7280/qtiseclib: Update version from 33 to 44
4815cc2 sc7280: Update AOP firmware to version 360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I510141916900507fd29a0e9315a3f8d954bc0cab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Now that gsi_fw blob has landed, need to uprev the qc_blobs.
Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that cpucp blobs have landed, need to uprev the qc_blobs.
Change-Id: I62dc410cee7baf5efa5c0406f35ee05a535f49b1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Now that Boot blobs have landed, need to uprev the qc_blobs.
Change-Id: I510de2d1e4334612c81f35a082dea92d445da0bb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I18fc6443a6972e22c979daaf68d0b9c046d1866f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45057
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the 3rdparty marker to blobs.git commit 892a697
Change-Id: I8a51f301e08e49970b4747f004e0752617de8005
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9625
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8613
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This pulls in the Intel microcode from blobs, and allows us to move
forward with relocating microcode updates in blobs.
Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8356
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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'blobs' now contains the update for the BaldEagle binaryPI.
Change-Id: I7ed423b17cee926205792223d6355277bedad552
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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'blobs' now contains the update for the Mullins binaryPI.
Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).
Apply that commit again:
'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.
Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.
Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.
Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update the 3rdparty repo to the IPQ binary commit
This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c
Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: http://review.coreboot.org/7354
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry picked from commit cfa06c746023fbb79169260012539253811525aa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0
Reviewed-on: http://review.coreboot.org/7437
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Only one setting actually works (exact value depends on board). So
no need to show it.
Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Update the 3rdparty repo to the IPQ binary commit
Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7354
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The BLOBs repo has been updated with AMD PI header files, peripheral
BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for
Steppe Eagle, the Steppe Eagle video BIOS, and platform security
processor firmware.
Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5240
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It includes a sandybridge fix.
Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
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For new systemagent v6 binaries.
Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3567
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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For google/stout binaries
Apparently the actual marker got lost in the rebase / change of the
commit message.
Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change the OSC method to actually grant control of
PCIe capabilities to the OS instead of granting no
control. I believe the logic was backwards in the
original commit. Bits should be set when granting
control and cleared when not granting control. By
setting the return value to 0x00, we effectively
tell the OS that it cannot control any PCIe
capability. See section 6.2.9 of the ACPI spec
version 3.0 for more information.
This edit is a duplication of the OSC method that
is in the src/southbridge/intel/bd82x6x/pch.asl
file.
Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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For google/stout binaries
Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2635
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I59fca4427345c7e677138b944613a1554d5a8331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2110
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2025
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1879
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a
Reviewed-on: http://review.coreboot.org/1816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1242
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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The build system will make sure only to fetch this if
desired by the user.
Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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