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Updating from commit id dd98487:
2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path)
to commit id cc6399e:
2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP)
This brings in 8 new commits:
cc6399e IoT MTL-UH & MTL-PS PV (3471_49) FSP
193dfbe Merge branch 'master' of https://github.com/intel/FSP
c89f32a IoT ADL-S MR7 (4445_05) FSP
bd31c89 IoT ADL-P MR6 (4445_04) FSP
738e498 Copy TGL FirmwareVersionInfoHob.h
9e7be91 IoT ADL-S MR7 (4445_05) FSP
56fb36c IoT ADL-P MR6 (4445_04) FSP
4707bc7 Elkhart Lake IPU2024.2 FSP
Change-Id: Ifa21950d6088b561f923587ca0f797de2983b67d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Updating from commit id 507ef01:
2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP)
to commit id dd98487:
2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path)
This brings in 6 new commits:
dd98487 Fix EagleStreamFspBinPkg Path
fcf623b Fix MAX_VMD_STACKS_PER_SOCKET
e07f875 Fix EagleStream BSF File
85f37ab Idaville FSP - New UPDs for SSC
98e497f IoT RPL-P MR1 (4445_03) FSP
fc5e3c9 IoT RPL-P MR1 (4445_03) FSP
Change-Id: If7d852e1a92d8409a5161797c0aa3a55a71c8b49
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Updating from commit id bb12f17:
2023-10-31 16:00:43 +0800 - (Elkhart Lake MR7 FSP)
to commit id 507ef01:
2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP)
This brings in 11 new commits:
507ef01 IoT ADL-S MR6 (4115_09) FSP
43f7092 IoT RPL-S MR2 (4415_02) FSP
848c499 Eagle Stream FSP 1.1.1.316
27e8376 Add Eagle Stream FSP
297e085 Add Third-Party Licenses
554f240 IoT RPL-S MR2 (4415_02) FSP
5b72773 IoT ADL-N MR3 (4413_00)
3ab4b5a IoT ADL-PS MR4 (4115_09) FSP
8267065 IoT ADL-PS MR3 (4081_07) FSP
5e8dae0 IoT ADL-N MR2 (4282_00)
8beacd5 WhitleyFspBinPkg: Fix warnings when building with GCC
Change-Id: I03b32e52adcdcaa0ac7f919aca5d459ad53db3bf
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Updating from commit id 481ea7c:
2023-09-19 15:21:38 -0700 - (Move to RaptorLakeFspBinPkg.dec)
to commit id bb12f17:
2023-10-31 16:00:43 +0800 - (Elkhart Lake MR7 FSP)
This brings in 5 new commits:
bb12f17 Elkhart Lake MR7 FSP
0d6bf96 Elkhart Lake MR7 FSP
88845b6 IoT ADL-S MR6 (4115_09) FSP
8c99965 IoT ADL-P MR5 (4115_09) FSP
6c549ee IoT ADL-N MR2 (4282_00)
Change-Id: I9fe65d830061c93ceac549dc7f41e7a98646a0a3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Updating from commit id a72794810884 (2023-09-07):
IoT ADL-N MR1 (4172_00)
to commit id 481ea7cf0bae (2023-09-19):
Move to RaptorLakeFspBinPkg.dec
This brings in 9 new commits:
481ea7cf0b Move to RaptorLakeFspBinPkg.dec
55e25b819e Raptor Lake FSP C.1.BD.40
2b0aac4f64 Raptor Lake FSP C.0.BD.40
3fa75657aa Add Client Raptor Lake FSP
8d24189361 Add Alder Lake and Raptor Lake to README.md
98f4a1fe2f Rename to AlderlakeSiliconPkg
c78a6784cb Add FvLateSilicon for Alder Lake
849ce8261b Tiger Lake FSP A.0.7E.70
4b0b1eb4e3 Update SplitFspBin.py to latest from edk2
Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78189
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Updating from commit id 3beceb0:
2023-06-30 14:45:10 +0800 - (IoT ADL-S MR5 (4081_05) FSP)
to commit id a727948:
2023-09-07 10:50:08 +0800 - (IoT ADL-N MR1 (4172_00))
This brings in 6 new commits:
a727948 IoT ADL-N MR1 (4172_00)
5030738 IoT RPL-S MR1 (4115_04) FSP
46a88ff IoT ADL-N MR1 (4172_00)
1fdadea IoT ADL-PS MR3 (4081_07) FSP
3054701 Add New Fsp, IoT ArizonaBeach MR2 (4202_00)
b5bbf8d IoT ADL-N MR1 (4172_00)
Change-Id: I90bebdc5c15c96303d88a7bc362f534397471e06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77443
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 6f2f17f:
2022-12-14 12:36:46 -0700 - (Deleted old Release Notes and Integration Guides)
to commit id 3beceb0:
2023-06-30 14:45:10 +0800 - (IoT ADL-S MR5 (4081_05) FSP)
This brings in 24 new commits:
3beceb0 IoT ADL-S MR5 (4081_05) FSP
6076e6a IoT ADL-S MR4 (4021_00) FSP
d3f81b8 Merge branch 'master' of https://github.com/intel/FSP
ebe9a91 IoT ADL-P MR4 (4081_04) FSP
63ee94d Tiger Lake - IoT FSP 6033_00_MR8
0012fe4 Delete FspInfoHob.h
99ed823 Tiger Lake - IoT FSP 6033_00_MR8
78ad3c7 Tiger Lake - IoT FSP 6033_00_MR8
2fea9a2 Delete TigerLakeFspPcds.dsc
4818990 Delete TigerLakeFspBinPkg.dec
458c639 Delete GpioConfig.h
a7ecf36 Delete FusaInfoHob.h
cfdf71d Tiger Lake - IoT FSP 6033_00_MR8
cf40b9e IoT ADL-P MR3 (4021_00) FSP
72b10be IoT RPL-S PV (3492_03) FSP
3ae8ca8 Elkhart Lake MR6 FSP
95f32b7 Alder Lake FSP C.1.75.10
8759e77 Alder Lake FSP C.0.75.10
f130444 IoT ADL-PS MR2 (4022_00) FSP
244f852 Merge branch 'master' of https://github.com/intel/FSP
7882623 IoT ADL-N PV (4031_00)
d85493d Whitley 4.2.0.2A
9ff1570 Merge branch 'master' of https://github.com/intel/FSP
fe92019 Updated for Tiger Lake - IoT FSP 5505_01_MR7
Change-Id: I3b5208e3508476fffca73a09da7aa3c5b53ba1ba
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Updating from commit id 2047412:
2022-11-29 17:52:03 +0800 - (Elkhart Lake MR5 FSP)
to commit id 6f2f17f:
2022-12-14 12:36:46 -0700 - (Deleted old Release Notes and Integration Guides)
This brings in 6 new commits:
6f2f17f Deleted old Release Notes and Integration Guides
3868f73 Updated for SGXFlex - New UPDs available
a649f0f Whitley FSP 2.2.0.3A
f99be62 Merge branch 'master' of https://github.com/intel/FSP
1787bc7 Updated IoT ADL-PS MR1 (3404_00) FSP
1e833b0 Elkhart Lake MR5 FSP
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1dbd85ef06b057305428d42dd6cd6de0f2618439
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Here are the FSP updates with latest master:
- IoT EHL MR5
- IoT ADL-P MR2
- IoT ADL-S MR3
- IoT ADL-PS PV
- IoT TGL MR7
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If4a76fe25c7b7a2c34e5bb284418c01c77b22abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70153
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The latest master adds the missing MemInfoHob.h to IOT ADL-P &
ADL-S folders.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8ef998b2e414d3d63494e6177b4fde2dc26e9d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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Update 3rdparty/fsp submodule to include AlderLake FSP.
Hook up the Kconfig settings to point to Fsp.fd and headers for
ADL-S and ADL-P platforms which the FSP has been published for.
The FSP binaries are compliant with the specification revision 2.3
so update these settings accordingly.
Although FSP header is v2.3 compliant, the features set of the FSP
v2.3 is not being met.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from:
f4bbf5a Apollo Lake MR10 FSP
Updating to:
c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
This brings in 10 new commits:
* c607bab Whitley&CedarIsland: Fix link issue with newer toolchains
* 08c041d Alder Lake - P IoT FSP PV
* a3dc6c6 Alder Lake - P IoT FSP PV
* 2cedeba Alder Lake - S IoT FSP MR1
* 72266f6 Elkhart Lake MR3 FSP
* 48d4c23 Tiger Lake - IoT FSP 4391_03
* e86327d Alder Lake - S IoT FSP PV
* 478a80a Whitley FSP 2.2.0.3A
* cb94d31 Whitley FSP 2.2.0.3A
* d678813 Alder Lake - S IoT FSP PV
Change-Id: I2473bfa5718676e5b6c90b76a3b817cd9f55da4b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Updating from commit id 10eae55:
2021-08-24 21:11:18 +0800 - (Elkhart Lake MR1 FSP)
to commit id f4bbf5a:
2022-01-29 00:32:47 +0800 - (Apollo Lake MR10 FSP)
This brings in 20 new commits:
f4bbf5a Apollo Lake MR10 FSP
aab8be0 Apollo Lake MR10 FSP
45b935f Apollo Lake MR10 FSP
755e782 Signed-off-by: Wong <swee.heng.wong@intel.com>
da956c1 Whitley FSP 2.2.0.3A
7e3d894 Whitley FSP 2.2.0.3A
04ad3cd Tiger Lake - UP3 IoT FSP MR4
ccf7f35 Elkhart Lake MR2 FSP
4aa1275 Elkhart Lake MR2 FSP
8aa6a9a Cedar Island FSP 2.2.0.3A
2e2e740 Whitley FSP 2.2.0.3A
91a6117 Tiger Lake - UP3 IoT FSP MR3
2863499 Delete FspUpd.h
df41c58 Delete FsptUpd.h
0d420eb Delete FspsUpd.h
53cc56a Delete FspmUpd.h
ad51318 Tiger Lake - UP3 IoT FSP MR3
63273a4 Delete Fsp.fd
ce61eb3 Tiger Lake - UP3 IoT FSP MR3
f7f77a2 Delete Fsp.bsf
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6128b9703498dd36be73c19cbbfe349c206c6cf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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This includes the Cedar Island FSP which is used by xeon_sp/cpx.
Also updates EHL FSP to latest MR1 version.
Change-Id: I1c2d440ce0f20a0922e5d91f615771843281fca6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Newest master includes these changes:
1. Introduce the FSP package for Elkhart Lake SKUs
2. Introduce the FSP package for Tiger Lake IoT SKUs
3. Update the FSP package to latest version for Apollo Lake,
Comet Lake and Tiger Lake (client SKUs)
You can get further 3rdparty/FSP commit history here:
https://github.com/intel/FSP/commits/master
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55228
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Newest master introduces the FSP for Tiger Lake client SKUs.
Change-Id: Id437faf72f1b8c5bc5310596bdab980e64614fa0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48712
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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We had to role the `fsp` submodule back for a minute due to a regression
with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into
the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and
heap usage partitioned for FSP using coreboot's stack (config FSP_USES_
CB_STACK), it works again.
To make this even messier: We already selected this Kconfig option for
Whiskey Lake, which is supposed to use the very same FSP binary. So with
either submodule pointer, something was always broken :-/
Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
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With CB:37564 (3rdparts/fsp: Update fsp submodule) a regression
has been introduced to CFL platforms, such that the FSP-M fails/is
broken. This commit sets the commit to checkout in the submodule
FSP back to a working version.
Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37669
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The name for the CoffeeLake FSP.fd was changed to Fsp.fd.
Therefore the CoffeLake / WhiskeyLake default path was
changed.
Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40
github commit:
https://github.com/IntelFsp/FSP/commit/59964173e18950debcc6b8856c5c928935ce0b4f
Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33642
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update submodule pointer to pull in newly-updated Braswell FSP.
Adjust FSP_FD_PATH for soc/cannonlake due to filename case change.
Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This includes the SplitFspBin.py script.
Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Like the 3rdparty/blobs repo this isn't checked out by default. Right
now you can manually check it out using
$ git submodule init --checkout
A follow up commit will add some automagic if USE_BLOBS and
MAINBOARD_USES_FSP2_0 are enabled.
Change-Id: Ie612495abc2a2d5947225e6ab54872aa72d4bec6
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/28303
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the 3rdparty marker to blobs.git commit 892a697
Change-Id: I8a51f301e08e49970b4747f004e0752617de8005
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9625
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8613
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This pulls in the Intel microcode from blobs, and allows us to move
forward with relocating microcode updates in blobs.
Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8356
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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'blobs' now contains the update for the BaldEagle binaryPI.
Change-Id: I7ed423b17cee926205792223d6355277bedad552
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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'blobs' now contains the update for the Mullins binaryPI.
Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).
Apply that commit again:
'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.
Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.
Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.
Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update the 3rdparty repo to the IPQ binary commit
This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c
Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: http://review.coreboot.org/7354
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry picked from commit cfa06c746023fbb79169260012539253811525aa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0
Reviewed-on: http://review.coreboot.org/7437
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Only one setting actually works (exact value depends on board). So
no need to show it.
Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Update the 3rdparty repo to the IPQ binary commit
Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7354
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The BLOBs repo has been updated with AMD PI header files, peripheral
BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for
Steppe Eagle, the Steppe Eagle video BIOS, and platform security
processor firmware.
Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5240
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It includes a sandybridge fix.
Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
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For new systemagent v6 binaries.
Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3567
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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For google/stout binaries
Apparently the actual marker got lost in the rebase / change of the
commit message.
Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change the OSC method to actually grant control of
PCIe capabilities to the OS instead of granting no
control. I believe the logic was backwards in the
original commit. Bits should be set when granting
control and cleared when not granting control. By
setting the return value to 0x00, we effectively
tell the OS that it cannot control any PCIe
capability. See section 6.2.9 of the ACPI spec
version 3.0 for more information.
This edit is a duplication of the OSC method that
is in the src/southbridge/intel/bd82x6x/pch.asl
file.
Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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For google/stout binaries
Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2635
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I59fca4427345c7e677138b944613a1554d5a8331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2110
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2025
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1879
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a
Reviewed-on: http://review.coreboot.org/1816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1242
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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The build system will make sure only to fetch this if
desired by the user.
Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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