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Updating from commit id c45d2febb:
2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration)
to commit id 61fe7826d:
2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration)
This brings in 10 new commits:
61fe7826d Merge "feat(fvp): build delegated attestation in BL31" into integration
cf17f7c45 Merge "chore(rpi3): remove redundant code" into integration
70360382b Merge "docs(maintainers): add NPU driver owners" into integration
60c439435 docs(maintainers): add NPU driver owners
e504ce5fa Merge "fix(versal_net): Enable a78 errata workarounds" into integration
bcc6e4a02 fix(versal_net): Enable a78 errata workarounds
0271eddb0 feat(fvp): build delegated attestation in BL31
6047ab122 Merge "fix(versal): enable a72 erratum 859971 and 1319367" into integration
769446a68 fix(versal): enable a72 erratum 859971 and 1319367
2594759d2 chore(rpi3): remove redundant code
Change-Id: Ic32c0889961f529e1762b208ef118a94369c34e6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Updating from commit id 7805999e6:
2022-09-05 16:42:34 +0200 - (Merge changes from topic "st-nand-updates" into integration)
to commit id c45d2febb:
2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration)
This brings in 288 new commits.
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I4137cab0a1a352e94e21f105717ae0b6c515b75b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68386
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Updating from commit id e0a6a512b:
2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration)
to commit id 7805999e6:
2022-09-05 16:42:34 +0200 - (Merge changes from topic "st-nand-updates" into integration)
This brings in 1030 new commits.
Change-Id: I981956fbdcbcfa4ce185652478b9bb30d40f5686
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Updating from commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
to commit id e0a6a512b:
2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration)
This brings in 324 new commits.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I44bca36f4b05e08fe7d7de0966131be84c0a7d2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Updating from commit id 586aafa3a:
2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration)
to commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
This brings in 684 new commits.
Change-Id: I4173f3cb646839ad12c4e43e8c50b0be53364f04
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Updating from commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
to commit id 586aafa3a:
2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration)
This brings in 207 new commits.
Change-Id: Iaf8af5ffaf377070ee1430ed7cfdc51001a1ba6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56416
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 7ad39818b:
2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration)
to commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
This brings in 861 new commits.
Change-Id: I912545022e4320b86ab8a382144c02e315d0c835
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Updating from commit id a4c979ade:
2020-08-26 14:59:05 +0000 - (Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration)
to commit id 7ad39818b:
2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration)
This brings in 222 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id186df36d90563f94f17cc210a6f634adc4ec61e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Updating from commit id ace23683b:
2019-09-27 Merge changes from topic "ld/stm32-authentication" into
integration
to commit id a4c979ade:
2020-08-26 Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
This brings in 1825 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id26301dae421eec61c10a2d18842053f3228c557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 42cdeb93:
2019-09-13 12:09:21 +0000 - (Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration)
to commit id ace23683:
2019-09-27 09:54:27 +0000 - (Merge changes from topic "ld/stm32-authentication" into integration)
This brings in 83 new commits.
Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).
Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.
NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.
Tested on GOOGLE_KEVIN (rk3399).
Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch updates the arm-trusted-firmware submodule from:
commit 9fd4a36c408a254d887106e6e3960d496456be2c
(Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
to
commit 693e278e308441d716f7f5116c43aa150955da31
(Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch)
This brings in 79 new commits.
Change-Id: Ieceb07760178f8ddbb5cafebabeb78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Updating from commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
to commit id 9fd4a36c:
2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
This brings in 596 new commits.
Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Updating from commit id 3944adca:
2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes)
to commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
This brings in 373 new commits.
Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59
This brings in 241 new commits from the upstream arm-trusted-firmware
repository, merged to the upstream tree between December 30, 2016 and
March 18, 2017.
3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes
..
e0f083a0 fiptool: Prepare ground for expanding the set of images at
runtime
Also setup ATF builds so that unused functions don't break the build.
They're harmless and they don't filter for these like we do.
Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017
- Also add associated change to src/soc/rockship/rk3399 Makefile.inc
that is required to build the M0 Firmware.
Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We need to disable some regulators when the device goes into suspend.
This means that we need to pass some gpios to bl31, and disable these
gpios when bl31 runs the suspend function.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low
[pg: also update arm-trusted-firmware to match]
Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70
Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/374046
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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90 patches pulled in.
Change-Id: I3b893957cbd330e71d0f218262e768f577df4c66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15122
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It includes support for rk3399.
Change-Id: I326ef3dc3021313ee852395c302c076b3e3c8c5e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update ATF codebase to a version that supports passing a timestamp and
fix the format to what it accepts now (including quotes).
This provides reproducible builds.
Change-Id: I12a0a2ba1ee7921ad93a3a877ea50309136ab1ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I8dddeead3c23a03803e7d8d5b2bfb8a15c5c2807
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10645
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: I080c0a5954d3e4b2d6debdf2a77f32df7329841c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the 3rdparty marker to blobs.git commit 892a697
Change-Id: I8a51f301e08e49970b4747f004e0752617de8005
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9625
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8613
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This pulls in the Intel microcode from blobs, and allows us to move
forward with relocating microcode updates in blobs.
Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8356
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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'blobs' now contains the update for the BaldEagle binaryPI.
Change-Id: I7ed423b17cee926205792223d6355277bedad552
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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'blobs' now contains the update for the Mullins binaryPI.
Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).
Apply that commit again:
'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.
Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.
Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.
Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update the 3rdparty repo to the IPQ binary commit
This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c
Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: http://review.coreboot.org/7354
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry picked from commit cfa06c746023fbb79169260012539253811525aa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0
Reviewed-on: http://review.coreboot.org/7437
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Only one setting actually works (exact value depends on board). So
no need to show it.
Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Update the 3rdparty repo to the IPQ binary commit
Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7354
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The BLOBs repo has been updated with AMD PI header files, peripheral
BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for
Steppe Eagle, the Steppe Eagle video BIOS, and platform security
processor firmware.
Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5240
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It includes a sandybridge fix.
Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
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For new systemagent v6 binaries.
Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3567
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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For google/stout binaries
Apparently the actual marker got lost in the rebase / change of the
commit message.
Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change the OSC method to actually grant control of
PCIe capabilities to the OS instead of granting no
control. I believe the logic was backwards in the
original commit. Bits should be set when granting
control and cleared when not granting control. By
setting the return value to 0x00, we effectively
tell the OS that it cannot control any PCIe
capability. See section 6.2.9 of the ACPI spec
version 3.0 for more information.
This edit is a duplication of the OSC method that
is in the src/southbridge/intel/bd82x6x/pch.asl
file.
Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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For google/stout binaries
Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2635
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I59fca4427345c7e677138b944613a1554d5a8331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2110
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2025
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1879
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a
Reviewed-on: http://review.coreboot.org/1816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1242
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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The build system will make sure only to fetch this if
desired by the user.
Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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